select ARCH_HAS_BARRIERS if CACHE_L2X0
select ARCH_HAS_CPUFREQ
select ARCH_PROVIDES_UDELAY
+ select FIQ
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
obj-y += powergate.o
obj-y += suspend.o
obj-y += fuse.o
+obj-$(CONFIG_FIQ) += fiq.o
+
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_dvfs.o
--- /dev/null
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ * Brian Swetland <swetland@google.com>
+ * Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/iomap.h>
+#include <mach/fiq.h>
+#include <mach/legacy_irq.h>
+
+#include "board.h"
+
+void tegra_fiq_enable(int irq)
+{
+ void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100);
+ /* enable FIQ */
+ u32 val = readl(base + GIC_CPU_CTRL);
+ val &= ~8; /* pass FIQs through */
+ val |= 2; /* enableNS */
+ writel(val, base + GIC_CPU_CTRL);
+ tegra_legacy_unmask_irq(irq);
+}
+
+void tegra_fiq_disable(int irq)
+{
+ tegra_legacy_mask_irq(irq);
+}
+
+void tegra_fiq_select(int irq, int on)
+{
+ tegra_legacy_select_fiq(irq, !!on);
+}
--- /dev/null
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ * Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_TEGRA_FIQ_H
+#define __ASM_ARCH_TEGRA_FIQ_H
+
+/* change an interrupt to be an FIQ instead of an IRQ */
+void tegra_fiq_select(int n, int on);
+
+/* enable/disable an interrupt that is an FIQ (safe from FIQ context?) */
+void tegra_fiq_enable(int n);
+void tegra_fiq_disable(int n);
+
+/* install an FIQ handler */
+int tegra_fiq_set_handler(void (*func)(void *data, void *regs, void *svc_sp),
+ void *data);
+
+#endif
#define INT_GPIO_NR (28 * 8)
+#define FIQ_START INT_GIC_BASE
+
#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
#define INT_BOARD_BASE TEGRA_NR_IRQS