ARM: dts: Add support for the cpuimx25 board from Eukrea and its baseboard.
authorDenis Carikli <denis@eukrea.com>
Thu, 5 Dec 2013 14:56:56 +0000 (15:56 +0100)
committerShawn Guo <shawn.guo@linaro.org>
Sun, 9 Feb 2014 13:33:21 +0000 (21:33 +0800)
The following devices/functionalities were added:
 * Main and secondary UARTs.
 * i2c and the pcf8563 device.
 * Ethernet.
 * NAND.
 * The BP1 button.
 * The LED.
 * Watchdog
 * SD.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts [new file with mode: 0644]

index c7426e0e11467aebfade7a55213a3897e486890d..aec8aafd7d5f0cc971957785786d37b09b3b4fd4 100644 (file)
@@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
        armada-xp-matrix.dtb \
        armada-xp-openblocks-ax3-4.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
+       imx25-eukrea-mbimxsd25-baseboard.dtb \
        imx25-karo-tx25.dtb \
        imx25-pdk.dtb \
        imx27-apf27.dtb \
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
new file mode 100644 (file)
index 0000000..d6f2764
--- /dev/null
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx25.dtsi"
+
+/ {
+       model = "Eukrea CPUIMX25";
+       compatible = "eukrea,cpuimx25", "fsl,imx25";
+
+       memory {
+               reg = <0x80000000 0x4000000>; /* 64M */
+       };
+};
+
+&fec {
+       phy-mode = "rmii";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       status = "okay";
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       pcf8563@51 {
+               compatible = "nxp,pcf8563";
+               reg = <0x51>;
+       };
+};
+
+&iomuxc {
+       imx25-eukrea-cpuimx25 {
+               pinctrl_fec: fecgrp {
+                       fsl,pins = <
+                               MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
+                               MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
+                               MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
+                               MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
+                               MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                               MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
+                               MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
+                               MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
+                               MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
+                               MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
+                       >;
+               };
+       };
+};
+
+&nfc {
+       nand-bus-width = <8>;
+       nand-ecc-mode = "hw";
+       nand-on-flash-bbt;
+       status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
new file mode 100644 (file)
index 0000000..62fb3da
--- /dev/null
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx25-eukrea-cpuimx25.dtsi"
+
+/ {
+       model = "Eukrea MBIMXSD25";
+       compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
+
+       gpio_keys {
+               compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpiokeys>;
+
+               bp1 {
+                       label = "BP1";
+                       gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+                       linux,code = <BTN_MISC>;
+                       gpio-key,wakeup;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpioled>;
+
+               led1 {
+                       label = "led1";
+                       gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       sound {
+               compatible = "eukrea,asoc-tlv320";
+               eukrea,model = "imx25-eukrea-tlv320aic23";
+               ssi-controller = <&ssi1>;
+               fsl,mux-int-port = <1>;
+               fsl,mux-ext-port = <5>;
+       };
+};
+
+&audmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_audmux>;
+       status = "okay";
+};
+
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc1>;
+       cd-gpios = <&gpio1 20>;
+       status = "okay";
+};
+
+&i2c1 {
+       tlv320aic23: codec@1a {
+               compatible = "ti,tlv320aic23";
+               reg = <0x1a>;
+       };
+};
+
+&iomuxc {
+       imx25-eukrea-mbimxsd25-baseboard {
+               pinctrl_audmux: audmuxgrp {
+                       fsl,pins = <
+                               MX25_PAD_KPP_COL3__AUD5_TXFS            0xe0
+                               MX25_PAD_KPP_COL2__AUD5_TXC             0xe0
+                               MX25_PAD_KPP_COL1__AUD5_RXD             0xe0
+                               MX25_PAD_KPP_COL0__AUD5_TXD             0xe0
+                       >;
+               };
+
+               pinctrl_esdhc1: esdhc1grp {
+                       fsl,pins = <
+                               MX25_PAD_SD1_CMD__SD1_CMD               0x400000c0
+                               MX25_PAD_SD1_CLK__SD1_CLK               0x400000c0
+                               MX25_PAD_SD1_DATA0__SD1_DATA0           0x400000c0
+                               MX25_PAD_SD1_DATA1__SD1_DATA1           0x400000c0
+                               MX25_PAD_SD1_DATA2__SD1_DATA2           0x400000c0
+                               MX25_PAD_SD1_DATA3__SD1_DATA3           0x400000c0
+                       >;
+               };
+
+               pinctrl_gpiokeys: gpiokeysgrp {
+                       fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
+               };
+
+               pinctrl_gpioled: gpioledgrp {
+                       fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
+               };
+
+               pinctrl_lcdc: lcdcgrp {
+                       fsl,pins = <
+                               MX25_PAD_LD0__LD0                       0x1
+                               MX25_PAD_LD1__LD1                       0x1
+                               MX25_PAD_LD2__LD2                       0x1
+                               MX25_PAD_LD3__LD3                       0x1
+                               MX25_PAD_LD4__LD4                       0x1
+                               MX25_PAD_LD5__LD5                       0x1
+                               MX25_PAD_LD6__LD6                       0x1
+                               MX25_PAD_LD7__LD7                       0x1
+                               MX25_PAD_LD8__LD8                       0x1
+                               MX25_PAD_LD9__LD9                       0x1
+                               MX25_PAD_LD10__LD10                     0x1
+                               MX25_PAD_LD11__LD11                     0x1
+                               MX25_PAD_LD12__LD12                     0x1
+                               MX25_PAD_LD13__LD13                     0x1
+                               MX25_PAD_LD14__LD14                     0x1
+                               MX25_PAD_LD15__LD15                     0x1
+                               MX25_PAD_GPIO_E__LD16                   0x1
+                               MX25_PAD_GPIO_F__LD17                   0x1
+                               MX25_PAD_HSYNC__HSYNC                   0x80000000
+                               MX25_PAD_VSYNC__VSYNC                   0x80000000
+                               MX25_PAD_LSCLK__LSCLK                   0x80000000
+                               MX25_PAD_OE_ACD__OE_ACD                 0x80000000
+                               MX25_PAD_CONTRAST__CONTRAST             0x80000000
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX25_PAD_UART1_RTS__UART1_RTS           0xe0
+                               MX25_PAD_UART1_CTS__UART1_CTS           0xe0
+                               MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
+                               MX25_PAD_UART1_RXD__UART1_RXD           0xc0
+                       >;
+               };
+
+               pinctrl_uart2: uart2grp {
+                       fsl,pins = <
+                               MX25_PAD_UART2_RXD__UART2_RXD           0x80000000
+                               MX25_PAD_UART2_TXD__UART2_TXD           0x80000000
+                               MX25_PAD_UART2_RTS__UART2_RTS           0x80000000
+                               MX25_PAD_UART2_CTS__UART2_CTS           0x80000000
+                       >;
+               };
+       };
+};
+
+&ssi1 {
+       codec-handle = <&tlv320aic23>;
+       fsl,mode = "i2s-slave";
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       fsl,uart-has-rtscts;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       fsl,uart-has-rtscts;
+       status = "okay";
+};