ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
authorJon Hunter <jon-hunter@ti.com>
Sun, 23 Sep 2012 23:28:27 +0000 (17:28 -0600)
committerPaul Walmsley <paul@pwsan.com>
Sun, 23 Sep 2012 23:28:27 +0000 (17:28 -0600)
Some instances of the DMTIMER peripheral on OMAP devices have the ability
to interrupt the on-chip DSP in addition to the ARM CPU. Add a DMTIMER
attribute to indicate which timers can interrupt the DSP. By using the
omap_dm_timer_request_by_cap() API, driver will now be able to allocate
a DMTIMER that can interrupt the DSP based upon this attribute and not require
the driver to know which instance has this capability.

DMTIMERs that have the ability to interrupt the DSP on OMAP devices are as
follows ...

- OMAP1 (OMAP5912/16xx/17xx) devices - All 8 DMTIMERs
- OMAP2/3/4 devices - DMTIMERs 5-8

Please note that for OMAP3+, timer8 has the ability to interrupt the DSP and
generate a PWM output.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap1/timer.c
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/plat-omap/include/plat/dmtimer.h

index aa81593db1af9f054058f2c1ed87d295e15bbafd..cdeb9d3ef64096f7ca3a2082ccb6c72038dce995 100644 (file)
@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
 
                pdata->set_timer_src = omap1_dm_timer_set_src;
                pdata->timer_capability = OMAP_TIMER_ALWON |
-                               OMAP_TIMER_NEEDS_RESET;
+                               OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
 
                ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
                if (ret) {
index 32c778bf8f08484ff6e6ecd78371d7daf2993095..de39017d2e28eceabc567ae672ac454928dc6f16 100644 (file)
@@ -240,6 +240,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+       .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
 /* timer1 */
 
 struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -328,6 +333,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -346,6 +352,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -364,6 +371,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -382,6 +390,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
 
index da6eca0ff79bb05bb3cf05876259b74bade97590..5ef9007ace50597e299d8d2694f7d7727f9f0d96 100644 (file)
@@ -171,6 +171,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+       .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+       .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
        .name           = "timer1",
@@ -254,6 +264,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -271,6 +282,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -288,6 +300,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -305,7 +318,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                },
        },
-       .dev_attr       = &capability_pwm_dev_attr,
+       .dev_attr       = &capability_dsp_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
 
index 46fd80c29a02f94c1bcafcfebc219fb6e6a0b6e6..17ab2dbc89314ef40c095060ee36ed94a71a23c6 100644 (file)
@@ -3097,6 +3097,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+       .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+       .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3201,6 +3211,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer6 */
@@ -3223,6 +3234,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer7 */
@@ -3244,6 +3256,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+       .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer8 */
@@ -3265,7 +3278,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-       .dev_attr       = &capability_pwm_dev_attr,
+       .dev_attr       = &capability_dsp_pwm_dev_attr,
 };
 
 /* timer9 */
index 19e7fa577bd0ad04eadcc4276d0de4f40039dadd..85868e98c11cd4ce4466da49669ee4cafc41c29f 100644 (file)
@@ -60,6 +60,7 @@
 #define OMAP_TIMER_ALWON                               0x40000000
 #define OMAP_TIMER_HAS_PWM                             0x20000000
 #define OMAP_TIMER_NEEDS_RESET                         0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ                         0x08000000
 
 struct omap_timer_capability_dev_attr {
        u32 timer_capability;