serial: 8250: Disable UART_IER_RLSI and UART_IER_RDI for dma receive
authorHuibin Hong <huibin.hong@rock-chips.com>
Mon, 24 Oct 2016 11:34:59 +0000 (19:34 +0800)
committerHuibin Hong <huibin.hong@rock-chips.com>
Tue, 25 Oct 2016 01:14:01 +0000 (09:14 +0800)
For rockchip serial, received data available and character timeout
interrupts are both enabled by IER[0]. Then when there is data in
the FIFO, received data available interrupt will occurd frequently.
So we must disable it, but which may disable the character timeout
interrput. Then it is useful to add a timer to report the data received
in dma buffer every 10 microsecond.

Change-Id: I1cf9dee495453d3530ab66c95a4e4cfef46b7795
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
drivers/tty/serial/8250/8250_port.c

index 56ccbcefdd850d435b6fe9b8e71e48a2df71d6e5..4feb9ed92d7c493af1ab0f5df59d87d2b2db29a3 100644 (file)
@@ -1563,9 +1563,17 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
        DEBUG_INTR("status = %x...", status);
 
        if (status & (UART_LSR_DR | UART_LSR_BI)) {
-               if (up->dma)
-                       dma_err = up->dma->rx_dma(up, iir);
+               if (up->dma) {
+                       /*
+                        * The RDI must be masked, or interrupt
+                        * would occur all the time.
+                        */
+                       up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
+                       up->port.read_status_mask &= ~UART_LSR_DR;
+                       serial_port_out(port, UART_IER, up->ier);
 
+                       dma_err = up->dma->rx_dma(up, iir);
+               }
                if (!up->dma || dma_err)
                        status = serial8250_rx_chars(up, status);
        }
@@ -2355,6 +2363,9 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 
        serial8250_set_divisor(port, baud, quot, frac);
 
+       if (up->dma)
+               up->fcr = UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_11;
+
        /*
         * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
         * is written without DLAB set, this mode will be disabled.