Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.

This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 8e692f3fd400a32565398e845a5963bf944bdc6f..bbeec1cac4381d0793f84c09f099f62f0c77898f 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -161,11 +161,6 @@ public:
 };
 } // end anonymous namespace
 
-namespace llvm {
-  // FIXME: TableGen this?
-  extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
-}
-
 namespace {
 
 /// ARMOperand - Instances of this class represent a parsed ARM machine

diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 4c5e9945139a56fa9b18dc848064f326d1a402e4..defeb91ac0a1c49662c49800b4843044ce61555e 100644 (file)
--- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1152,11 +1152,6 @@ getMsbOpValue(const MCInst &MI, unsigned Op,
   return msb;
 }
 
-namespace llvm {
-  // FIXME: TableGen this?
-  extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
-}
-
 unsigned ARMMCCodeEmitter::
 getRegisterListOpValue(const MCInst &MI, unsigned Op,
                        SmallVectorImpl<MCFixup> &Fixups) const {

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index efa8a6e1547e7b63dafc7b99d60af5208cf5c47d..6630fd00b2e767b26ac5aaa14c96fe1424904769 100644 (file)
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -13,6 +13,7 @@
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
@@ -400,19 +401,25 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
   if (Tok.isNot(AsmToken::Identifier))
     return Error(Tok.getLoc(), "invalid register name");
 
-  // FIXME: Validate register for the current architecture; we have to do
-  // validation later, so maybe there is no need for this here.
   RegNo = MatchRegisterName(Tok.getString());
 
   // If the match failed, try the register name as lowercase.
   if (RegNo == 0)
     RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
 
-  // FIXME: This should be done using Requires<In32BitMode> and
-  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
-  // can be also checked.
-  if (RegNo == X86::RIZ && !is64BitMode())
-    return Error(Tok.getLoc(), "riz register in 64-bit mode only");
+  if (!is64BitMode()) {
+    // FIXME: This should be done using Requires<In32BitMode> and
+    // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
+    // checked.
+    // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
+    // REX prefix.
+    if (RegNo == X86::RIZ ||
+        X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
+        X86II::isX86_64NonExtLowByteReg(RegNo) ||
+        X86II::isX86_64ExtendedReg(RegNo))
+      return Error(Tok.getLoc(), "register %"
+                   + Tok.getString() + " is only available in 64-bit mode");
+  }
 
   // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
   if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
@@ -490,7 +497,7 @@ X86Operand *X86ATTAsmParser::ParseOperand() {
     SMLoc Start, End;
     if (ParseRegister(RegNo, Start, End)) return 0;
     if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
-      Error(Start, "eiz and riz can only be used as index registers");
+      Error(Start, "%eiz and %riz can only be used as index registers");
       return 0;
     }
 

diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index bd7ee0a549443839c505120163e441b1f76a110c..cf582b58446a69ca2ed817ff3c56f4f0a9383b7c 100644 (file)
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -155,11 +155,6 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
   return MCFixup::getKindForSize(Size, isPCRel);
 }
 
-namespace llvm {
-  // FIXME: TableGen this?
-  extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc.
-}
-
 /// Is32BitMemOperand - Return true if the specified instruction with a memory
 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
 /// memory operand.  Op specifies the operand # of the memoperand.

diff --git a/test/MC/X86/3DNow.s b/test/MC/X86/3DNow.s
index 4dc68aecf4fa4a059e1184c657eeb021518fe508..871857b155d00fa62d6026bb821335aab37c718f 100644 (file)
--- a/test/MC/X86/3DNow.s
+++ b/test/MC/X86/3DNow.s
@@ -1,18 +1,18 @@
-// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
 
 // PR8283
 
 // CHECK: pavgusb %mm2, %mm1  # encoding: [0x0f,0x0f,0xca,0xbf]
 pavgusb        %mm2, %mm1
 
-// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0xbf]
+// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf]
 pavgusb        9(%esi,%edx), %mm3
 
         
 // CHECK: pf2id %mm2, %mm1  # encoding: [0x0f,0x0f,0xca,0x1d]
 pf2id  %mm2, %mm1
 
-// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0x1d]
+// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d]
 pf2id  9(%esi,%edx), %mm3
 
 // CHECK: pfacc %mm2, %mm1  # encoding: [0x0f,0x0f,0xca,0xae]

diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s
index d2d42c209d5bd06611eb2d5afe7301427be2f4a5..0954ce2b02cd99d864cf2515183c5293dc843398 100644 (file)
--- a/test/MC/X86/x86-32-coverage.s
+++ b/test/MC/X86/x86-32-coverage.s
@@ -19571,8 +19571,8 @@
 // CHECK:      aeskeygenassist $125, (%edx,%eax,4), %xmm2
                 aeskeygenassist $125, (%edx,%eax,4), %xmm2
 
-// CHECK:   blendvps   (%rax), %xmm1   # encoding: [0x66,0x0f,0x38,0x14,0x08]
-            blendvps (%rax), %xmm1
+// CHECK:   blendvps   (%eax), %xmm1   # encoding: [0x66,0x0f,0x38,0x14,0x08]
+            blendvps (%eax), %xmm1
 // CHECK:   blendvps   %xmm2, %xmm1    # encoding: [0x66,0x0f,0x38,0x14,0xca]
             blendvps %xmm2, %xmm1
 

diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s
index 183306be2c116cfc6d8aea07d838023003c1de63..318e4788d6d43c2191a741b33e8a311eda55baa9 100644 (file)
--- a/test/MC/X86/x86_errors.s
+++ b/test/MC/X86/x86_errors.s
@@ -1,5 +1,12 @@
 // RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
-// RUN: FileCheck < %t.err %s
+// RUN: FileCheck --check-prefix=64 < %t.err %s
 
-// CHECK: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
+// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
+// RUN: FileCheck --check-prefix=32 < %t.err %s
+// rdar://8204588
+
+// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
 cmp $0, 0(%eax)
+
+// 32: error: register %rax is only available in 64-bit mode
+addl $0, 0(%rax)

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index f56dcd5b8c596e26ebd65f5ada22d30f38d5c3fa..9587245a259a2b0b46f153a598bce6553756cc67 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -40,6 +40,9 @@ RegisterInfoEmitter::runEnums(raw_ostream &OS,
 
   OS << "namespace llvm {\n\n";
 
+  OS << "class MCRegisterClass;\n"
+     << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n";
+
   if (!Namespace.empty())
     OS << "namespace " << Namespace << " {\n";
   OS << "enum {\n  NoRegister,\n";