ARM: mvebu: Add MBus to Armada 370/XP device tree
authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Fri, 26 Jul 2013 13:17:57 +0000 (10:17 -0300)
committerJason Cooper <jason@lakedaemon.net>
Tue, 6 Aug 2013 14:11:16 +0000 (14:11 +0000)
The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.

This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.

A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/boot/dts/armada-370-db.dts
arch/arm/boot/dts/armada-370-mirabox.dts
arch/arm/boot/dts/armada-370-rd.dts
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-370.dtsi
arch/arm/boot/dts/armada-xp-db.dts
arch/arm/boot/dts/armada-xp-gp.dts
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
arch/arm/boot/dts/armada-xp.dtsi

index 55b986cc43561d71e1b7296b0aedddeeac17435f..5920b4e4b74c523674e2545348aec2deaab4caa5 100644 (file)
@@ -30,6 +30,8 @@
        };
 
        soc {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <200000000>;
index 37530afd8af0b7d2c07fd5e4cc7110b0ba1e0632..a4202b6c16c214df494e7daee9323452355dc3a8 100644 (file)
@@ -25,6 +25,8 @@
        };
 
        soc {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <200000000>;
index 7aa2171fbc76e7fb0b14b3fc3f44e180c061bd53..dd0ba018b6285e5ae712c6573a2b4820c36d2e30 100644 (file)
@@ -28,6 +28,8 @@
        };
 
        soc {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <200000000>;
index 90b117624abb2230105855b70fbdf313fa73a05e..62639b4a61f97735773598233426102a3c13bcbd 100644 (file)
@@ -18,6 +18,8 @@
 
 /include/ "skeleton64.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
 / {
        model = "Marvell Armada 370 and XP SoC";
        compatible = "marvell,armada-370-xp";
        };
 
        soc {
-               #address-cells = <1>;
+               #address-cells = <2>;
                #size-cells = <1>;
-               compatible = "simple-bus";
+               controller = <&mbusc>;
                interrupt-parent = <&mpic>;
-               ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
-                         0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
 
                internal-regs {
                        compatible = "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       ranges;
+                       ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                       mbusc: mbus-controller@20000 {
+                               compatible = "marvell,mbus-controller";
+                               reg = <0x20000 0x100>, <0x20180 0x20>;
+                       };
 
                        mpic: interrupt-controller@20000 {
                                compatible = "marvell,mpic";
index 08ec6e3a9c7ad061f7131e924415c74bcb441cc0..4b54e511baef57014dbf0f04ce71b04d669a763e 100644 (file)
@@ -29,8 +29,8 @@
        };
 
        soc {
-               ranges = <0          0xd0000000 0x0100000 /* internal registers */
-                         0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+               compatible = "marvell,armada370-mbus", "simple-bus";
+
                internal-regs {
                        system-controller@18200 {
                                compatible = "marvell,armada-370-xp-system-controller";
index a9bd766c53243211db07c0dcc1824561154e2327..0d4ce54d0c2dd443e3668fc9e148c69d8ea280a5 100644 (file)
@@ -30,9 +30,7 @@
        };
 
        soc {
-               ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
-                         0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
-                         0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
 
                internal-regs {
                        serial@12000 {
index 54843e5a049f4e960b26fad02f634f61413601a4..2fa920987780fcdec06e3887f0fef6721cd48a45 100644 (file)
@@ -39,9 +39,7 @@
        };
 
        soc {
-               ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
-                         0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-                         0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
 
                internal-regs {
                        serial@12000 {
index d090264d81dd232e719c9dfa36eee2f6f777e8f5..a3e3a1290ff54872bfbef07d53fbffe04562d4fe 100644 (file)
@@ -27,9 +27,7 @@
        };
 
        soc {
-               ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
-                         0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
-                         0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
 
                internal-regs {
                        serial@12000 {
index 8c07bfe21ee85e7171c00fed2b10fbfba02d357a..803382497c352f4b6b81518e3a1f7be30d01951d 100644 (file)
@@ -27,6 +27,8 @@
        };
 
        soc {
+               compatible = "marvell,armadaxp-mbus", "simple-bus";
+
                internal-regs {
                        L2: l2-cache {
                                compatible = "marvell,aurora-system-cache";