rk29: L2 Data RAM latency set to 4 cycles, Tag RAM latency set to 3 cycles, suggested...

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f5e368dc0912dab82cc778552018813b7d075466..9b26be949ef2512a58b70ef4bddb776eff2eab6e 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -271,8 +271,8 @@ __v7_setup:
        bic     r5, r5, #1 << 29                @ L2 data RAM read multiplexer select: 0 = two cycles
        bic     r5, r5, #7 << 6
        bic     r5, r5, #15
-       orr     r5, r5, #3 << 6                 @ Tag RAM latency: b011 = 4 cycles
-       orr     r5, r5, #4                      @ Data RAM latency: b0100 = 5 cycles
+       orr     r5, r5, #2 << 6                 @ Tag RAM latency: b010 = 3 cycles
+       orr     r5, r5, #3                      @ Data RAM latency: b0011 = 4 cycles
        mcr     p15, 1, r5, c9, c0, 2
 #endif