drm/i915/chv: Add cursor pipe offsets

Unsurprisingly the cursor C regiters are also at a weird offset on CHV.
Add more pipe offsets to handle them.

This also gets rid of most of the differences between the i9xx vs. ivb
cursor code. We can unify the remaining code as well, but I'll leave
that for another patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6764ac86c341c455b2e8737f0065921d3f541b31..16bbdc7243df75474b9ca20c7d0e99faa2a9eea7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2304,10 +2304,8 @@ static bool cursor_active(struct drm_device *dev, int pipe)
 
        if (IS_845G(dev) || IS_I865G(dev))
                state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
-       else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
-               state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
        else
-               state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
+               state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
        return state;
 }
@@ -2317,10 +2315,7 @@ static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 pos;
 
-       if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
-               pos = I915_READ(CURPOS_IVB(pipe));
-       else
-               pos = I915_READ(CURPOS(pipe));
+       pos = I915_READ(CURPOS(pipe));
 
        *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
        if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4636799c7b67deeb0e9d658047ec725a5755686e..6920127d734aa8b9cdbd1194d9b917193b9bfe63 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -61,11 +61,18 @@ static struct drm_driver driver;
        .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
                             CHV_PALETTE_C_OFFSET }
 
+#define CURSOR_OFFSETS \
+       .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
+
+#define IVB_CURSOR_OFFSETS \
+       .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
+
 static const struct intel_device_info intel_i830_info = {
        .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
        .has_overlay = 1, .overlay_needs_physical = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_845g_info = {
@@ -73,6 +80,7 @@ static const struct intel_device_info intel_845g_info = {
        .has_overlay = 1, .overlay_needs_physical = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i85x_info = {
@@ -82,6 +90,7 @@ static const struct intel_device_info intel_i85x_info = {
        .has_fbc = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i865g_info = {
@@ -89,6 +98,7 @@ static const struct intel_device_info intel_i865g_info = {
        .has_overlay = 1, .overlay_needs_physical = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i915g_info = {
@@ -96,6 +106,7 @@ static const struct intel_device_info intel_i915g_info = {
        .has_overlay = 1, .overlay_needs_physical = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i915gm_info = {
        .gen = 3, .is_mobile = 1, .num_pipes = 2,
@@ -105,12 +116,14 @@ static const struct intel_device_info intel_i915gm_info = {
        .has_fbc = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945g_info = {
        .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
        .has_overlay = 1, .overlay_needs_physical = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945gm_info = {
        .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
@@ -120,6 +133,7 @@ static const struct intel_device_info intel_i945gm_info = {
        .has_fbc = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i965g_info = {
@@ -128,6 +142,7 @@ static const struct intel_device_info intel_i965g_info = {
        .has_overlay = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
@@ -137,6 +152,7 @@ static const struct intel_device_info intel_i965gm_info = {
        .supports_tv = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_g33_info = {
@@ -145,6 +161,7 @@ static const struct intel_device_info intel_g33_info = {
        .has_overlay = 1,
        .ring_mask = RENDER_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_g45_info = {
@@ -152,6 +169,7 @@ static const struct intel_device_info intel_g45_info = {
        .has_pipe_cxsr = 1, .has_hotplug = 1,
        .ring_mask = RENDER_RING | BSD_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_gm45_info = {
@@ -161,6 +179,7 @@ static const struct intel_device_info intel_gm45_info = {
        .supports_tv = 1,
        .ring_mask = RENDER_RING | BSD_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_pineview_info = {
@@ -168,6 +187,7 @@ static const struct intel_device_info intel_pineview_info = {
        .need_gfx_hws = 1, .has_hotplug = 1,
        .has_overlay = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ironlake_d_info = {
@@ -175,6 +195,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
        .need_gfx_hws = 1, .has_hotplug = 1,
        .ring_mask = RENDER_RING | BSD_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
@@ -183,6 +204,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
        .has_fbc = 1,
        .ring_mask = RENDER_RING | BSD_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_sandybridge_d_info = {
@@ -192,6 +214,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
        .has_llc = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
@@ -201,6 +224,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
        .has_llc = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 #define GEN7_FEATURES  \
@@ -214,6 +238,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
        GEN7_FEATURES,
        .is_ivybridge = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
@@ -221,6 +246,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
        .is_ivybridge = 1,
        .is_mobile = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
@@ -228,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
        .is_ivybridge = 1,
        .num_pipes = 0, /* legal, last one wins */
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_valleyview_m_info = {
@@ -239,6 +266,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
        .has_fbc = 0, /* legal, last one wins */
        .has_llc = 0, /* legal, last one wins */
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
@@ -249,6 +277,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
        .has_fbc = 0, /* legal, last one wins */
        .has_llc = 0, /* legal, last one wins */
        GEN_DEFAULT_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_haswell_d_info = {
@@ -258,6 +287,7 @@ static const struct intel_device_info intel_haswell_d_info = {
        .has_fpga_dbg = 1,
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_haswell_m_info = {
@@ -268,6 +298,7 @@ static const struct intel_device_info intel_haswell_m_info = {
        .has_fpga_dbg = 1,
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_broadwell_d_info = {
@@ -278,6 +309,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
        .has_ddi = 1,
        .has_fbc = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_broadwell_m_info = {
@@ -308,6 +340,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = {
        .has_ddi = 1,
        .has_fbc = 1,
        GEN_DEFAULT_PIPEOFFSETS,
+       IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_cherryview_info = {
@@ -318,6 +351,7 @@ static const struct intel_device_info intel_cherryview_info = {
        .is_valleyview = 1,
        .display_mmio_offset = VLV_DISPLAY_BASE,
        GEN_CHV_PIPEOFFSETS,
+       CURSOR_OFFSETS,
 };
 
 /*

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 53e6fa5c18698b71467e40ff255e4762244f5986..979f6e6f8e2eb1f87fc70cc180c705d7c40f458a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -566,6 +566,7 @@ struct intel_device_info {
        int dpll_offsets[I915_MAX_PIPES];
        int dpll_md_offsets[I915_MAX_PIPES];
        int palette_offsets[I915_MAX_PIPES];
+       int cursor_offsets[I915_MAX_PIPES];
 };
 
 #undef DEFINE_FLAG

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ada0cf326e7f9ac04144073d66981e23d387b687..9407edb7eb946c7f50fee30090fb8ce71fc206da 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3833,7 +3833,7 @@ enum punit_power_well {
 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
 
 /* Cursor A & B regs */
-#define _CURACNTR              (dev_priv->info.display_mmio_offset + 0x70080)
+#define _CURACNTR              0x70080
 /* Old style CUR*CNTR flags (desktop 8xx) */
 #define   CURSOR_ENABLE                0x80000000
 #define   CURSOR_GAMMA_ENABLE  0x40000000
@@ -3860,28 +3860,34 @@ enum punit_power_well {
 #define   MCURSOR_PIPE_B       (1 << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
 #define   CURSOR_TRICKLE_FEED_DISABLE  (1 << 14)
-#define _CURABASE              (dev_priv->info.display_mmio_offset + 0x70084)
-#define _CURAPOS               (dev_priv->info.display_mmio_offset + 0x70088)
+#define _CURABASE              0x70084
+#define _CURAPOS               0x70088
 #define   CURSOR_POS_MASK       0x007FF
 #define   CURSOR_POS_SIGN       0x8000
 #define   CURSOR_X_SHIFT        0
 #define   CURSOR_Y_SHIFT        16
 #define CURSIZE                        0x700a0
-#define _CURBCNTR              (dev_priv->info.display_mmio_offset + 0x700c0)
-#define _CURBBASE              (dev_priv->info.display_mmio_offset + 0x700c4)
-#define _CURBPOS               (dev_priv->info.display_mmio_offset + 0x700c8)
+#define _CURBCNTR              0x700c0
+#define _CURBBASE              0x700c4
+#define _CURBPOS               0x700c8
 
 #define _CURBCNTR_IVB          0x71080
 #define _CURBBASE_IVB          0x71084
 #define _CURBPOS_IVB           0x71088
 
-#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
-#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
-#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
+#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
+       dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
+       dev_priv->info.display_mmio_offset)
+
+#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
+#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
+#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
 
-#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
-#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
-#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
+#define CURSOR_A_OFFSET 0x70080
+#define CURSOR_B_OFFSET 0x700c0
+#define CHV_CURSOR_C_OFFSET 0x700e0
+#define IVB_CURSOR_B_OFFSET 0x71080
+#define IVB_CURSOR_C_OFFSET 0x72080
 
 /* Display A control */
 #define _DSPACNTR                              0x70180

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 00a214a9d18f9d2abfed4543d4d3b9e3e3a65820..a68dcce6ac3949c030d538c9a54a19b9ed417d33 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1190,10 +1190,8 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
 
        if (IS_845G(dev) || IS_I865G(dev))
                cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
-       else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
-               cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
        else
-               cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
+               cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
        WARN(cur_state != state,
             "cursor on pipe %c assertion failure (expected %s, current %s)\n",
@@ -7910,7 +7908,7 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
 
        if (intel_crtc->cursor_visible != visible) {
                int16_t width = intel_crtc->cursor_width;
-               uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
+               uint32_t cntl = I915_READ(CURCNTR(pipe));
                if (base) {
                        cntl &= ~CURSOR_MODE;
                        cntl |= MCURSOR_GAMMA_ENABLE;
@@ -7936,14 +7934,14 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
                        cntl |= CURSOR_PIPE_CSC_ENABLE;
                        cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
                }
-               I915_WRITE(CURCNTR_IVB(pipe), cntl);
+               I915_WRITE(CURCNTR(pipe), cntl);
 
                intel_crtc->cursor_visible = visible;
        }
        /* and commit changes on next vblank */
-       POSTING_READ(CURCNTR_IVB(pipe));
-       I915_WRITE(CURBASE_IVB(pipe), base);
-       POSTING_READ(CURBASE_IVB(pipe));
+       POSTING_READ(CURCNTR(pipe));
+       I915_WRITE(CURBASE(pipe), base);
+       POSTING_READ(CURBASE(pipe));
 }
 
 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
@@ -7990,16 +7988,14 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        if (!visible && !intel_crtc->cursor_visible)
                return;
 
-       if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-               I915_WRITE(CURPOS_IVB(pipe), pos);
+       I915_WRITE(CURPOS(pipe), pos);
+
+       if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
                ivb_update_cursor(crtc, base);
-       } else {
-               I915_WRITE(CURPOS(pipe), pos);
-               if (IS_845G(dev) || IS_I865G(dev))
-                       i845_update_cursor(crtc, base);
-               else
-                       i9xx_update_cursor(crtc, base);
-       }
+       else if (IS_845G(dev) || IS_I865G(dev))
+               i845_update_cursor(crtc, base);
+       else
+               i9xx_update_cursor(crtc, base);
 }
 
 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
@@ -12290,15 +12286,9 @@ intel_display_capture_error_state(struct drm_device *dev)
                if (!error->pipe[i].power_domain_on)
                        continue;
 
-               if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
-                       error->cursor[i].control = I915_READ(CURCNTR(i));
-                       error->cursor[i].position = I915_READ(CURPOS(i));
-                       error->cursor[i].base = I915_READ(CURBASE(i));
-               } else {
-                       error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
-                       error->cursor[i].position = I915_READ(CURPOS_IVB(i));
-                       error->cursor[i].base = I915_READ(CURBASE_IVB(i));
-               }
+               error->cursor[i].control = I915_READ(CURCNTR(i));
+               error->cursor[i].position = I915_READ(CURPOS(i));
+               error->cursor[i].base = I915_READ(CURBASE(i));
 
                error->plane[i].control = I915_READ(DSPCNTR(i));
                error->plane[i].stride = I915_READ(DSPSTRIDE(i));