{
struct vop *vop = to_vop(crtc);
const struct vop_data *vop_data = vop->data;
+ int request_clock = mode->clock;
int clock;
if (mode->hdisplay > vop_data->max_disably_output.width)
if (mode->vdisplay > vop_data->max_disably_output.height)
return MODE_BAD_VVALUE;
- clock = clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ request_clock *= 2;
+ clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
+
/*
* Hdmi or DisplayPort request a Accurate clock.
*/
if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
output_type == DRM_MODE_CONNECTOR_DisplayPort)
- if (clock != mode->clock)
+ if (clock != request_clock)
return MODE_CLOCK_RANGE;
return MODE_OK;
{
struct vop *vop = to_vop(crtc);
const struct vop_data *vop_data = vop->data;
+ int request_clock = mode->clock;
if (mode->hdisplay > vop_data->max_disably_output.width ||
mode->vdisplay > vop_data->max_disably_output.height)
return false;
- adjusted_mode->clock =
- clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ request_clock *= 2;
+ adjusted_mode->crtc_clock =
+ clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
return true;
}
VOP_CTRL_SET(vop, p2i_en, 0);
}
- clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
+ VOP_CTRL_SET(vop, core_dclk_div,
+ !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
+
+ clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
vop_cfg_done(vop);
/*
.post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
.global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
.overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
- .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
+ .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1),
.p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),