rk29: fix clock name and depends

diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c
index 52929d10e28a034687783e7d314ef0312d5bcedb..e1e11b1c1f783deeeda0a5d9d06248a9492b95d8 100755 (executable)
--- a/arch/arm/mach-rk29/clock.c
+++ b/arch/arm/mach-rk29/clock.c
@@ -762,7 +762,7 @@ static struct clk *aclk_periph_parents[4] = { &periph_pll_clk, &arm_pll_clk, &dd
 static struct clk aclk_periph = {
        .name           = "aclk_periph",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_PEIRPH_AXI,
+       .gate_idx       = CLK_GATE_ACLK_PEIRPH,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
        .clksel_con     = CRU_CLKSEL0_CON,
@@ -776,7 +776,7 @@ static struct clk aclk_periph = {
 static struct clk pclk_periph = {
        .name           = "pclk_periph",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_PEIRPH_APB,
+       .gate_idx       = CLK_GATE_PCLK_PEIRPH,
        .parent         = &aclk_periph,
        .recalc         = clksel_recalc_shift,
        .set_rate       = clksel_set_rate_shift,
@@ -789,7 +789,7 @@ static struct clk pclk_periph = {
 static struct clk hclk_periph = {
        .name           = "hclk_periph",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_PEIRPH_AHB,
+       .gate_idx       = CLK_GATE_HCLK_PEIRPH,
        .parent         = &aclk_periph,
        .recalc         = clksel_recalc_shift,
        .set_rate       = clksel_set_rate_shift,
@@ -862,7 +862,7 @@ static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 static struct clk clk_mac_ref = {
        .name           = "mac_ref",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_MAC_PHY,
+       .gate_idx       = CLK_GATE_MAC_REF,
        .clksel_con     = CRU_CLKSEL1_CON,
        .clksel_parent_mask     = 1,
        .clksel_parent_shift    = 28,
@@ -1127,35 +1127,35 @@ static struct clk clk_timer3 = {
 };
 
 
-static struct clk *clk_sdmmc_src_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
+static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 
-static struct clk clk_sdmmc_src = {
-       .name           = "sdmmc_src",
+static struct clk clk_mmc_src = {
+       .name           = "mmc_src",
        .clksel_con     = CRU_CLKSEL7_CON,
        .clksel_parent_mask     = 3,
        .clksel_parent_shift    = 0,
-       .parents        = clk_sdmmc_src_parents,
+       .parents        = clk_mmc_src_parents,
 };
 
-static struct clk clk_sdmmc0 = {
-       .name           = "sdmmc0",
-       .parent         = &clk_sdmmc_src,
+static struct clk clk_mmc0 = {
+       .name           = "mmc0",
+       .parent         = &clk_mmc_src,
        .mode           = gate_mode,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
-       .gate_idx       = CLK_GATE_SDMMC0,
+       .gate_idx       = CLK_GATE_MMC0,
        .clksel_con     = CRU_CLKSEL7_CON,
        .clksel_mask    = 0x3F,
        .clksel_shift   = 2,
 };
 
-static struct clk clk_sdmmc1 = {
-       .name           = "sdmmc1",
-       .parent         = &clk_sdmmc_src,
+static struct clk clk_mmc1 = {
+       .name           = "mmc1",
+       .parent         = &clk_mmc_src,
        .mode           = gate_mode,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
-       .gate_idx       = CLK_GATE_SDMMC1,
+       .gate_idx       = CLK_GATE_MMC1,
        .clksel_con     = CRU_CLKSEL7_CON,
        .clksel_mask    = 0x3F,
        .clksel_shift   = 10,
@@ -1163,7 +1163,7 @@ static struct clk clk_sdmmc1 = {
 
 static struct clk clk_emmc = {
        .name           = "emmc",
-       .parent         = &clk_sdmmc_src,
+       .parent         = &clk_mmc_src,
        .mode           = gate_mode,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
@@ -1523,7 +1523,7 @@ static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
 static struct clk dclk_lcdc = {
        .name           = "dclk_lcdc",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_LCDC,
+       .gate_idx       = CLK_GATE_DCLK_LCDC,
        .clksel_con     = CRU_CLKSEL16_CON,
        .clksel_parent_mask     = 1,
        .clksel_parent_shift    = 10,
@@ -1533,7 +1533,7 @@ static struct clk dclk_lcdc = {
 static struct clk dclk_ebook = {
        .name           = "dclk_ebook",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_EBOOK,
+       .gate_idx       = CLK_GATE_DCLK_EBOOK,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
        .clksel_con     = CRU_CLKSEL16_CON,
@@ -1549,7 +1549,7 @@ static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &perip
 static struct clk aclk_lcdc = {
        .name           = "aclk_lcdc",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_LCDC_AXI,
+       .gate_idx       = CLK_GATE_ACLK_LCDC,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
        .clksel_con     = CRU_CLKSEL16_CON,
@@ -1563,7 +1563,7 @@ static struct clk aclk_lcdc = {
 static struct clk hclk_lcdc = {
        .name           = "hclk_lcdc",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_LCDC_AHB,
+       .gate_idx       = CLK_GATE_HCLK_LCDC,
        .parent         = &aclk_lcdc,
        .clksel_con     = CRU_CLKSEL16_CON,
        .recalc         = clksel_recalc_shift,
@@ -1580,7 +1580,7 @@ static struct clk aclk_vepu = {
        .mode           = gate_mode,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
-       .gate_idx       = CLK_GAET_VEPU_AXI,
+       .gate_idx       = CLK_GAET_ACLK_VEPU,
        .clksel_con     = CRU_CLKSEL17_CON,
        .clksel_mask    = 0x1F,
        .clksel_shift   = 2,
@@ -1595,7 +1595,7 @@ static struct clk hclk_vepu = {
        .mode           = gate_mode,
        .recalc         = clksel_recalc_shift,
        .set_rate       = clksel_set_rate_shift,
-       .gate_idx       = CLK_GATE_VEPU_AHB,
+       .gate_idx       = CLK_GATE_HCLK_VEPU,
        .clksel_con     = CRU_CLKSEL17_CON,
        .clksel_mask    = 3,
        .clksel_shift   = 28,
@@ -1608,7 +1608,7 @@ static struct clk aclk_vdpu = {
        .mode           = gate_mode,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
-       .gate_idx       = CLK_GATE_VDPU_AXI,
+       .gate_idx       = CLK_GATE_ACLK_VDPU,
        .clksel_con     = CRU_CLKSEL17_CON,
        .clksel_mask    = 0x1F,
        .clksel_shift   = 9,
@@ -1623,7 +1623,7 @@ static struct clk hclk_vdpu = {
        .mode           = gate_mode,
        .recalc         = clksel_recalc_shift,
        .set_rate       = clksel_set_rate_shift,
-       .gate_idx       = CLK_GATE_VDPU_AHB,
+       .gate_idx       = CLK_GATE_HCLK_VDPU,
        .clksel_con     = CRU_CLKSEL17_CON,
        .clksel_mask    = 3,
        .clksel_shift   = 30,
@@ -1647,7 +1647,7 @@ static struct clk clk_gpu = {
 static struct clk aclk_gpu = {
        .name           = "aclk_gpu",
        .mode           = gate_mode,
-       .gate_idx       = CLK_GATE_GPU_AXI,
+       .gate_idx       = CLK_GATE_ACLK_GPU,
        .recalc         = clksel_recalc_div,
        .set_rate       = clksel_set_rate_div,
        .clksel_con     = CRU_CLKSEL17_CON,
@@ -1693,13 +1693,12 @@ GATE_CLK(gpio4, pclk_cpu, GPIO4);
 GATE_CLK(gpio5, pclk_periph, GPIO5);
 GATE_CLK(gpio6, pclk_cpu, GPIO6);
 
-GATE_CLK(dma0, aclk_cpu, DMA0);
-GATE_CLK(dma1, aclk_periph, DMA1);
+GATE_CLK(dma1, aclk_cpu, DMA1);
 GATE_CLK(dma2, aclk_periph, DMA2);
 
 GATE_CLK(gic, aclk_cpu, GIC);
-GATE_CLK(imem, aclk_cpu, IMEM);
-GATE_CLK(ebrom, hclk_cpu, EBROM);
+GATE_CLK(intmem, aclk_cpu, INTMEM);
+GATE_CLK(rom, hclk_cpu, ROM);
 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
@@ -1712,46 +1711,46 @@ GATE_CLK(pmu, pclk_cpu, PMU);
 GATE_CLK(grf, pclk_cpu, GRF);
 
 GATE_CLK(emem, hclk_periph, EMEM);
-GATE_CLK(usb, hclk_periph, USB);
-GATE_CLK(ddr_periph, aclk_periph, DDR_PERIPH);
-GATE_CLK(periph_cpu, aclk_cpu, PERIPH_CPU);
-GATE_CLK(smc_axi, aclk_periph, SMC_AXI);
+GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
+GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
+GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
+GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
 GATE_CLK(smc, pclk_periph, SMC);
-GATE_CLK(mac_ahb, hclk_periph, MAC_AHB);
-GATE_CLK(mac_tx, hclk_periph, MAC_TX);
-GATE_CLK(mac_rx, hclk_periph, MAC_RX);
+GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
+GATE_CLK(mii_tx, hclk_periph, MII_TX);
+GATE_CLK(mii_rx, hclk_periph, MII_RX);
 GATE_CLK(hif, hclk_periph, HIF);
 GATE_CLK(nandc, hclk_periph, NANDC);
-GATE_CLK(hsadc_ahb, hclk_periph, HSADC_AHB);
+GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
-GATE_CLK(uhost_ahb, hclk_periph, UHOST_AHB);
+GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
 
-GATE_CLK(vip_slave, hclk_cpu, VIP_SLAVE);
+GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
 GATE_CLK(wdt, pclk_periph, WDT);
 GATE_CLK(pwm, pclk_periph, PWM);
 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
-GATE_CLK(vip_matrix, hclk_cpu, VIP_MATRIX);
+GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
 GATE_CLK(vip_input, hclk_cpu, VIP_INPUT);
 GATE_CLK(jtag, aclk_cpu, JTAG);
 
-GATE_CLK(ddr_lcdc_axi, aclk_cpu, DDR_LCDC_AXI);
-GATE_CLK(ipp_axi, aclk_cpu, IPP_AXI);
-GATE_CLK(ipp_ahb, hclk_cpu, IPP_AHB);
-GATE_CLK(ebook_ahb, hclk_cpu, EBOOK_AHB);
-GATE_CLK(display_matrix_axi, aclk_cpu, DISPLAY_MATRIX_AXI);
-GATE_CLK(display_matrix_ahb, hclk_cpu, DISPLAY_MATRIX_AHB);
-GATE_CLK(ddr_vepu_axi, aclk_cpu, DDR_VEPU_AXI);
-GATE_CLK(ddr_vdpu_axi, aclk_cpu, DDR_VDPU_AXI);
-GATE_CLK(ddr_gpu_axi, aclk_cpu, DDR_GPU_AXI);
-GATE_CLK(gpu_ahb, hclk_cpu, GPU_AHB);
-GATE_CLK(cpu_vcodec_ahb, hclk_cpu, CPU_VCODEC_AHB);
-GATE_CLK(cpu_display_ahb, hclk_cpu, CPU_DISPLAY_AHB);
-
-GATE_CLK(sdmmc0_ahb, hclk_periph, SDMMC0_AHB);
-GATE_CLK(sdmmc1_ahb, hclk_periph, SDMMC1_AHB);
-GATE_CLK(emmc_ahb, hclk_periph, EMMC_AHB);
+GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
+GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
+GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
+GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
+GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
+GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
+GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
+GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
+GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
+GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
+GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
+GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
+
+GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
+GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
+GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
 
 #define CLK(dev, con, ck) \
        { \
@@ -1816,13 +1815,13 @@ static struct clk_lookup clks[] = {
        CLK1(timer2),
        CLK1(timer3),
 
-       CLK1(sdmmc_src),
-       CLK("rk29_sdmmc.0", "sdmmc", &clk_sdmmc0),
-       CLK("rk29_sdmmc.0", "sdmmc_ahb", &clk_sdmmc0_ahb),
-       CLK("rk29_sdmmc.1", "sdmmc", &clk_sdmmc1),
-       CLK("rk29_sdmmc.1", "sdmmc_ahb", &clk_sdmmc1_ahb),
+       CLK1(mmc_src),
+       CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
+       CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
+       CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
+       CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
        CLK1(emmc),
-       CLK1(emmc_ahb),
+       CLK1(hclk_emmc),
        CLK1(ddr),
 
        CLK1(uart01_src),
@@ -1875,13 +1874,12 @@ static struct clk_lookup clks[] = {
        CLK1(gpio5),
        CLK1(gpio6),
 
-       CLK1(dma0),
        CLK1(dma1),
        CLK1(dma2),
 
        CLK1(gic),
-       CLK1(imem),
-       CLK1(ebrom),
+       CLK1(intmem),
+       CLK1(rom),
        CLK1(ddr_phy),
        CLK1(ddr_reg),
        CLK1(ddr_cpu),
@@ -1894,20 +1892,20 @@ static struct clk_lookup clks[] = {
        CLK1(grf),
 
        CLK1(emem),
-       CLK1(usb),
-       CLK1(ddr_periph),
-       CLK1(periph_cpu),
-       CLK1(smc_axi),
+       CLK1(hclk_usb_peri),
+       CLK1(aclk_ddr_peri),
+       CLK1(aclk_cpu_peri),
+       CLK1(aclk_smc),
        CLK1(smc),
-       CLK1(mac_ahb),
-       CLK1(mac_tx),
-       CLK1(mac_rx),
+       CLK1(hclk_mac),
+       CLK1(mii_tx),
+       CLK1(mii_rx),
        CLK1(hif),
        CLK1(nandc),
-       CLK1(hsadc_ahb),
+       CLK1(hclk_hsadc),
        CLK1(usbotg0),
        CLK1(usbotg1),
-       CLK1(uhost_ahb),
+       CLK1(hclk_uhost),
        CLK1(pid_filter),
 
        CLK1(vip_slave),
@@ -1918,18 +1916,18 @@ static struct clk_lookup clks[] = {
        CLK1(vip_input),
        CLK1(jtag),
 
-       CLK1(ddr_lcdc_axi),
-       CLK1(ipp_axi),
-       CLK1(ipp_ahb),
-       CLK1(ebook_ahb),
-       CLK1(display_matrix_axi),
-       CLK1(display_matrix_ahb),
-       CLK1(ddr_vepu_axi),
-       CLK1(ddr_vdpu_axi),
-       CLK1(ddr_gpu_axi),
-       CLK1(gpu_ahb),
-       CLK1(cpu_vcodec_ahb),
-       CLK1(cpu_display_ahb),
+       CLK1(aclk_ddr_lcdc),
+       CLK1(aclk_ipp),
+       CLK1(hclk_ipp),
+       CLK1(hclk_ebook),
+       CLK1(aclk_disp_matrix),
+       CLK1(hclk_disp_matrix),
+       CLK1(aclk_ddr_vepu),
+       CLK1(aclk_ddr_vdpu),
+       CLK1(aclk_ddr_gpu),
+       CLK1(hclk_gpu),
+       CLK1(hclk_cpu_vcodec),
+       CLK1(hclk_cpu_display),
 };
 
 static LIST_HEAD(clocks);
@@ -2265,7 +2263,7 @@ static void rk29_clock_common_init(void)
        clk_set_parent_nolock(&clk_i2s1_div, &periph_pll_clk);
        clk_set_parent_nolock(&clk_spdif_div, &periph_pll_clk);
        clk_set_parent_nolock(&clk_spi_src, &periph_pll_clk);
-       clk_set_parent_nolock(&clk_sdmmc_src, &periph_pll_clk);
+       clk_set_parent_nolock(&clk_mmc_src, &periph_pll_clk);
        clk_set_parent_nolock(&clk_uart01_src, &periph_pll_clk);
        clk_set_parent_nolock(&clk_uart23_src, &periph_pll_clk);
        clk_set_parent_nolock(&dclk_lcdc_div, &periph_pll_clk);
@@ -2283,14 +2281,14 @@ static void rk29_clock_common_init(void)
 
 static void clk_enable_init_clocks(void)
 {
-       clk_enable_nolock(&clk_cpu_display_ahb);
-       clk_enable_nolock(&clk_ddr_gpu_axi);
-       clk_enable_nolock(&clk_display_matrix_ahb);
-       clk_enable_nolock(&clk_display_matrix_axi);
-       clk_enable_nolock(&clk_ddr_lcdc_axi);
+       clk_enable_nolock(&clk_hclk_cpu_display);
+       clk_enable_nolock(&clk_aclk_ddr_gpu);
+       clk_enable_nolock(&clk_hclk_disp_matrix);
+       clk_enable_nolock(&clk_aclk_disp_matrix);
+       clk_enable_nolock(&clk_aclk_ddr_lcdc);
        clk_enable_nolock(&clk_nandc);
-       clk_enable_nolock(&clk_periph_cpu);
-       clk_enable_nolock(&clk_ddr_periph);
+       clk_enable_nolock(&clk_aclk_cpu_peri);
+       clk_enable_nolock(&clk_aclk_ddr_peri);
        clk_enable_nolock(&clk_grf);
        clk_enable_nolock(&clk_pmu);
        clk_enable_nolock(&clk_ddr_cpu);
@@ -2299,18 +2297,17 @@ static void clk_enable_init_clocks(void)
        clk_enable_nolock(&clk_gic);
        clk_enable_nolock(&clk_dma2);
        clk_enable_nolock(&clk_dma1);
-       clk_enable_nolock(&clk_dma0);
 #ifdef CONFIG_DEBUG_LL
        clk_enable_nolock(&clk_uart1);
 #endif
        /* vpu */
        clk_enable_nolock(&aclk_vdpu);
        clk_enable_nolock(&hclk_vdpu);
-       clk_enable_nolock(&clk_ddr_vdpu_axi);
+       clk_enable_nolock(&clk_aclk_ddr_vdpu);
        clk_enable_nolock(&aclk_vepu);
        clk_enable_nolock(&hclk_vepu);
-       clk_enable_nolock(&clk_ddr_vepu_axi);
-       clk_enable_nolock(&clk_cpu_vcodec_ahb);
+       clk_enable_nolock(&clk_aclk_ddr_vepu);
+       clk_enable_nolock(&clk_hclk_cpu_vcodec);
 }
 
 static int __init clk_disable_unused(void)

diff --git a/arch/arm/mach-rk29/include/mach/cru.h b/arch/arm/mach-rk29/include/mach/cru.h
index 3ece2b9794434c81bc35c65c22a4cb1398bf28f7..2f86edc444d5db9e6b142ec5efad414c7eabb1f4 100644 (file)
--- a/arch/arm/mach-rk29/include/mach/cru.h
+++ b/arch/arm/mach-rk29/include/mach/cru.h
@@ -19,19 +19,18 @@ enum cru_clk_gate
 {
        /* SCU CLK GATE 0 CON */
        CLK_GATE_CORE = 0,
-       CLK_GATE_CORE_APB,
-       CLK_GATE_CORE_ATB,
-       CLK_GATE_CPU_AXI,
-       CLK_GATE_CPU_AXI2,
-       CLK_GATE_CPU_AHB,
-       CLK_GATE_CPU_MATRIX1_AHB,
-       CLK_GATE_CPU_APB,
-       CLK_GATE_CPU_ATB,
-       CLK_GATE_DMA0,
-       CLK_GATE_DMA1,
+       CLK_GATE_PCLK_CORE,
+       CLK_GATE_ATCLK_CORE,
+       CLK_GATE_ACLK_CPU,
+       CLK_GATE_ACLK_CPU2,
+       CLK_GATE_HCLK_CPU,
+       CLK_GATE_HCLK_CPU_MATRIX1,
+       CLK_GATE_PCLK_CPU,
+       CLK_GATE_ATCLK_CPU,
+       CLK_GATE_DMA1 = 10,
        CLK_GATE_GIC,
-       CLK_GATE_IMEM,
-       CLK_GATE_EBROM = 14,
+       CLK_GATE_INTMEM,
+       CLK_GATE_ROM = 14,
        CLK_GATE_I2S0,
        CLK_GATE_I2S1,
        CLK_GATE_SPDIF,
@@ -51,35 +50,35 @@ enum cru_clk_gate
        CLK_GATE_GRF,
 
        /* SCU CLK GATE 1 CON */
-       CLK_GATE_PEIRPH_AXI = 32,
-       CLK_GATE_PEIRPH_AHB,
-       CLK_GATE_PEIRPH_APB,
+       CLK_GATE_ACLK_PEIRPH = 32,
+       CLK_GATE_HCLK_PEIRPH,
+       CLK_GATE_PCLK_PEIRPH,
        CLK_GATE_EMEM,
-       CLK_GATE_USB,
+       CLK_GATE_HCLK_USB_PERI,
        CLK_GATE_DMA2,
-       CLK_GATE_DDR_PERIPH,
-       CLK_GATE_PERIPH_CPU,
-       CLK_GATE_SMC_AXI,
+       CLK_GATE_ACLK_DDR_PERI,
+       CLK_GATE_ACLK_CPU_PERI,
+       CLK_GATE_ACLK_SMC,
        CLK_GATE_SMC,
-       CLK_GATE_MAC_AHB = 43,
-       CLK_GATE_MAC_PHY,
-       CLK_GATE_MAC_TX,
-       CLK_GATE_MAC_RX,
+       CLK_GATE_HCLK_MAC = 43,
+       CLK_GATE_MAC_REF,
+       CLK_GATE_MII_TX,
+       CLK_GATE_MII_RX,
        CLK_GATE_HIF,
        CLK_GATE_NANDC,
-       CLK_GATE_HSADC_AHB,
+       CLK_GATE_HCLK_HSADC,
        CLK_GATE_HSADC,
-       CLK_GATE_SDMMC0_AHB,
-       CLK_GATE_SDMMC0,
-       CLK_GATE_SDMMC1_AHB,
-       CLK_GATE_SDMMC1,
-       CLK_GATE_EMMC_AHB,
+       CLK_GATE_HCLK_MMC0,
+       CLK_GATE_MMC0,
+       CLK_GATE_HCLK_MMC1,
+       CLK_GATE_MMC1,
+       CLK_GATE_HCLK_EMMC,
        CLK_GATE_EMMC,
        CLK_GATE_USBOTG0,
        CLK_GATE_USBPHY0,
        CLK_GATE_USBOTG1,
        CLK_GATE_USBPHY1,
-       CLK_GATE_UHOST_AHB,
+       CLK_GATE_HCLK_UHOST,
        CLK_GATE_UHOST,
        CLK_GATE_PID_FILTER,
 
@@ -112,28 +111,28 @@ enum cru_clk_gate
        CLK_GATE_JTAG,
 
        /* CRU CLK GATE 3 CON */
-       CLK_GATE_LCDC_AXI = 96,
-       CLK_GATE_DDR_LCDC_AXI,
-       CLK_GATE_LCDC_AHB,
-       CLK_GATE_LCDC,
-       CLK_GATE_IPP_AXI,
-       CLK_GATE_IPP_AHB,
-       CLK_GATE_EBOOK_AHB,
-       CLK_GATE_EBOOK,
-       CLK_GATE_DISPLAY_MATRIX_AXI,
-       CLK_GATE_DISPLAY_MATRIX_AHB,
-       CLK_GAET_VEPU_AXI,
-       CLK_GATE_DDR_VEPU_AXI,
-       CLK_GATE_VDPU_AXI,
-       CLK_GATE_DDR_VDPU_AXI,
+       CLK_GATE_ACLK_LCDC = 96,
+       CLK_GATE_ACLK_DDR_LCDC,
+       CLK_GATE_HCLK_LCDC,
+       CLK_GATE_DCLK_LCDC,
+       CLK_GATE_ACLK_IPP,
+       CLK_GATE_HCLK_IPP,
+       CLK_GATE_HCLK_EBOOK,
+       CLK_GATE_DCLK_EBOOK,
+       CLK_GATE_ACLK_DISP_MATRIX,
+       CLK_GATE_HCLK_DISP_MATRIX,
+       CLK_GAET_ACLK_VEPU,
+       CLK_GATE_ACLK_DDR_VEPU,
+       CLK_GATE_ACLK_VDPU,
+       CLK_GATE_ACLK_DDR_VDPU,
        CLK_GATE_GPU,
-       CLK_GATE_GPU_AXI,
-       CLK_GATE_DDR_GPU_AXI,
-       CLK_GATE_GPU_AHB,
-       CLK_GATE_VEPU_AHB,
-       CLK_GATE_VDPU_AHB,
-       CLK_GATE_CPU_VCODEC_AHB,
-       CLK_GATE_CPU_DISPLAY_AHB,
+       CLK_GATE_ACLK_GPU,
+       CLK_GATE_ACLK_DDR_GPU,
+       CLK_GATE_HCLK_GPU,
+       CLK_GATE_HCLK_VEPU,
+       CLK_GATE_HCLK_VDPU,
+       CLK_GATE_HCLK_CPU_VCODEC,
+       CLK_GATE_HCLK_CPU_DISPLAY,
 
        CLK_GATE_MAX,
 };

diff --git a/drivers/mmc/host/rk29_sdmmc.c b/drivers/mmc/host/rk29_sdmmc.c
index 48909a70dcd11f833ff1a12f2477ddb0e43e0641..33c64b1aa41f9db6a1d667345fd3ae578efc969f 100755 (executable)
--- a/drivers/mmc/host/rk29_sdmmc.c
+++ b/drivers/mmc/host/rk29_sdmmc.c
@@ -1379,10 +1379,10 @@ static int rk29_sdmmc_probe(struct platform_device *pdev)
                rk29_dma_set_buffdone_fn(host->dma_chn, rk29_sdmmc_dma_complete);       
                host->dma_addr = regs->start + SDMMC_DATA;
        }               
-       host->clk = clk_get(&pdev->dev, "sdmmc");
+       host->clk = clk_get(&pdev->dev, "mmc");
        clk_set_rate(host->clk,52000000);
        clk_enable(host->clk);
-       clk_enable(clk_get(&pdev->dev, "sdmmc_ahb"));
+       clk_enable(clk_get(&pdev->dev, "hclk_mmc"));
        host->bus_hz = clk_get_rate(host->clk);  ///40000000;  ////cgu_get_clk_freq(CGU_SB_SD_MMC_CCLK_IN_ID); 
 
        /* reset all blocks */

diff --git a/drivers/staging/rk29/ipp/rk29-ipp.c b/drivers/staging/rk29/ipp/rk29-ipp.c
index bdf1f6c1ac70ee57cba6d8e87a5d9ae7ca0f9b79..42187319f83d6170a37e48cfb52928ab31df8080 100644 (file)
--- a/drivers/staging/rk29/ipp/rk29-ipp.c
+++ b/drivers/staging/rk29/ipp/rk29-ipp.c
@@ -812,16 +812,16 @@ static int __init ipp_drv_probe(struct platform_device *pdev)
        }\r
 \r
        /* get the clock */\r
-       data->axi_clk = clk_get(&pdev->dev, "ipp_axi");\r
-       if(NULL == data->axi_clk)\r
+       data->axi_clk = clk_get(&pdev->dev, "aclk_ipp");\r
+       if (IS_ERR(data->axi_clk))\r
        {\r
                ERR("failed to find ipp axi clock source\n");\r
                ret = -ENOENT;\r
                goto err_clock;\r
        }\r
 \r
-       data->ahb_clk = clk_get(&pdev->dev, "ipp_ahb");\r
-       if(NULL == data->ahb_clk)\r
+       data->ahb_clk = clk_get(&pdev->dev, "hclk_ipp");\r
+       if (IS_ERR(data->ahb_clk))\r
        {\r
                ERR("failed to find ipp ahb clock source\n");\r
                ret = -ENOENT;\r

diff --git a/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_driver.c b/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_driver.c
index b95716a44e3f2d9eef79dd8f717afa2fcefd5374..c09b616eeedb0f00b9e47156b9319728562b719b 100644 (file)
--- a/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_driver.c
+++ b/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_driver.c
@@ -463,7 +463,7 @@ static int drv_init(void)
 #if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
     struct clk * clk_gpu = NULL;
     struct clk * clk_aclk_gpu = NULL;
-    struct clk * clk_gpu_ahb = NULL;
+    struct clk * clk_hclk_gpu = NULL;
 #endif
 
     gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_DRIVER,
@@ -471,8 +471,8 @@ static int drv_init(void)
 
 #if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
     // clk_gpu_ahb
-    clk_gpu_ahb = clk_get(NULL, "gpu_ahb");
-    if(!IS_ERR(clk_gpu_ahb))    clk_enable(clk_gpu_ahb);
+    clk_hclk_gpu = clk_get(NULL, "hclk_gpu");
+    if(!IS_ERR(clk_hclk_gpu))    clk_enable(clk_hclk_gpu);
 
     // clk_aclk_gpu
     clk_aclk_gpu = clk_get(NULL, "aclk_gpu");
@@ -626,7 +626,7 @@ static void drv_exit(void)
 #if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
     struct clk * clk_gpu = NULL;
     struct clk * clk_aclk_gpu = NULL;
-    struct clk * clk_gpu_ahb = NULL;
+    struct clk * clk_hclk_gpu = NULL;
 #endif
     gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_DRIVER,
                  "[galcore] Entering drv_exit\n");
@@ -651,8 +651,8 @@ static void drv_exit(void)
     clk_aclk_gpu = clk_get(NULL, "aclk_gpu");
     if(!IS_ERR(clk_aclk_gpu))    clk_disable(clk_aclk_gpu);   
 
-    clk_gpu_ahb = clk_get(NULL, "gpu_ahb");
-    if(!IS_ERR(clk_gpu_ahb))    clk_disable(clk_gpu_ahb);
+    clk_hclk_gpu = clk_get(NULL, "hclk_gpu");
+    if(!IS_ERR(clk_hclk_gpu))    clk_disable(clk_hclk_gpu);
 #endif
 }
 

diff --git a/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_os.c b/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_os.c
index 0c9a55cf67ec351e90696035b308a1808879911f..a56afb5d304e1685c51a0633691fa68f9e51464a 100644 (file)
--- a/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_os.c
+++ b/drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_os.c
@@ -5890,16 +5890,16 @@ gckOS_SetGPUPower(
 
     struct clk * clk_gpu = clk_get(NULL, "gpu");
     struct clk * clk_aclk_gpu = clk_get(NULL, "aclk_gpu");
-    struct clk * clk_gpu_ahb = clk_get(NULL, "gpu_ahb");
+    struct clk * clk_hclk_gpu = clk_get(NULL, "hclk_gpu");
 
     if(Clock) {
-        if(!IS_ERR(clk_gpu_ahb))    clk_enable(clk_gpu_ahb);
+        if(!IS_ERR(clk_hclk_gpu))   clk_enable(clk_hclk_gpu);
         if(!IS_ERR(clk_aclk_gpu))   clk_enable(clk_aclk_gpu);
         if(!IS_ERR(clk_gpu))        clk_enable(clk_gpu);
     } else {
         if(!IS_ERR(clk_gpu))        clk_disable(clk_gpu);
         if(!IS_ERR(clk_aclk_gpu))   clk_disable(clk_aclk_gpu);
-        if(!IS_ERR(clk_gpu_ahb))    clk_disable(clk_gpu_ahb);
+        if(!IS_ERR(clk_hclk_gpu))   clk_disable(clk_hclk_gpu);
     }
 
     if(Power) {

diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c
index f26074426bbefa4f1d827e168a764e9b76f4177f..ebbb9da51bd561d15a40bc82a3371cb6d01c4f43 100755 (executable)
--- a/drivers/usb/dwc_otg/dwc_otg_driver.c
+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
@@ -904,7 +904,7 @@ static __devinit int dwc_otg_driver_probe(struct platform_device *pdev)
        memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
        dwc_otg_device->reg_offset = 0xFFFFFFFF;
        
-    busclk = clk_get(NULL, "usb");
+    busclk = clk_get(NULL, "hclk_usb_peri");
     if (IS_ERR(busclk)) {
             retval = PTR_ERR(busclk);
             DWC_ERROR("can't get USB PERIPH AHB bus clock\n");
@@ -1295,7 +1295,7 @@ static __devinit int host11_driver_probe(struct platform_device *pdev)
     }
     clk_enable(phyclk);
     
-    ahbclk = clk_get(NULL, "uhost_ahb");
+    ahbclk = clk_get(NULL, "hclk_uhost");
     if (IS_ERR(ahbclk)) {
             retval = PTR_ERR(ahbclk);
             DWC_ERROR("can't get UHOST ahb bus clock\n");