[IntrNoMem]>;
}
+//===----------------------------------------------------------------------===//
+// SSE4A
+
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse4a_movnt_ss : GCCBuiltin<"__builtin_ia32_movntss">,
+ Intrinsic<[], [llvm_ptr_ty, llvm_v4f32_ty], []>;
+ def int_x86_sse4a_movnt_sd : GCCBuiltin<"__builtin_ia32_movntsd">,
+ Intrinsic<[], [llvm_ptr_ty, llvm_v2f64_ty], []>;
+}
+
//===----------------------------------------------------------------------===//
// AVX
defm : pclmul_alias<"lqhq", 0x10>;
defm : pclmul_alias<"lqlq", 0x00>;
+//===----------------------------------------------------------------------===//
+// SSE4A Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasSSE4A] in {
+def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
+ "movntss\t{$src, $dst|$dst, $src}",
+ [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
+
+def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
+ "movntsd\t{$src, $dst|$dst, $src}",
+ [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
+}
+
//===----------------------------------------------------------------------===//
// AVX Instructions
//===----------------------------------------------------------------------===//
--- /dev/null
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
+
+define void @test1(float* %p, <4 x float> %a) nounwind optsize ssp {
+; CHECK: movntss
+entry:
+ tail call void @llvm.x86.sse4a.movnt.ss(float* %p, <4 x float> %a) nounwind
+ ret void
+}
+
+declare void @llvm.x86.sse4a.movnt.ss(float*, <4 x float>)
+
+define void @test2(double* %p, <2 x double> %a) nounwind optsize ssp {
+; CHECK: movntsd
+entry:
+ tail call void @llvm.x86.sse4a.movnt.sd(double* %p, <2 x double> %a) nounwind
+ ret void
+}
+
+declare void @llvm.x86.sse4a.movnt.sd(double*, <2 x double>)