rk3128-box:update dts according to pm.c
authorLuowei <lw@rock-chips.com>
Wed, 10 Dec 2014 06:19:53 +0000 (14:19 +0800)
committerLuowei <lw@rock-chips.com>
Wed, 10 Dec 2014 06:20:28 +0000 (14:20 +0800)
arch/arm/boot/dts/rk3128-box-rk88.dts
arch/arm/boot/dts/rk3128-box.dts

index 498c747c2e759ab0669b8b428285605c31bb0eb8..a7af9bea2d3f5f6a3b70daad10eddecd20b0bc75 100755 (executable)
                         |RKPM_CTR_PWR_DMNS
                         |RKPM_CTR_GTCLKS
                         |RKPM_CTR_PLLS
+                        //|RKPM_CTR_ARMOFF_LPMD
+                        |RKPM_CTR_DDR
                         |RKPM_CTR_IDLESRAM_MD
                         |RKPM_CTR_DDR
-                        |RKPM_CTR_VOLTS
-                        |RKPM_CTR_VOL_PWM1
-                        |RKPM_CTR_VOL_PWM2
+                        //|RKPM_CTR_BUS_IDLE
+                       //|RKPM_CTR_VOLTS
+                       //|RKPM_CTR_VOL_PWM1
+                       //|RKPM_CTR_VOL_PWM2
                         )
                 >;
+               rockchip,pmic-suspend_gpios = <
+                       0
+                        >;
         };
 
 };
index f4c564d62af5b73e87d7ea9a8840f3ce38659013..97d581e1db9cf752d1a1830139af73764f95823a 100755 (executable)
                         |RKPM_CTR_PWR_DMNS
                         |RKPM_CTR_GTCLKS
                         |RKPM_CTR_PLLS
+                        //|RKPM_CTR_ARMOFF_LPMD
+                        |RKPM_CTR_DDR
                         |RKPM_CTR_IDLESRAM_MD
                         |RKPM_CTR_DDR
-                        |RKPM_CTR_VOLTS
-                        |RKPM_CTR_VOL_PWM1
-                        |RKPM_CTR_VOL_PWM2
+                        //|RKPM_CTR_BUS_IDLE
+                       //|RKPM_CTR_VOLTS
+                       //|RKPM_CTR_VOL_PWM1
+                       //|RKPM_CTR_VOL_PWM2
                         )
                 >;
+               rockchip,pmic-suspend_gpios = <
+                       0
+                        >;
         };
 };