uint32_t dst0_YrgbMst=0,dst0_CbrMst=0;\r
uint32_t ret = 0;\r
uint32_t deinterlace_config = 0;\r
-\r
+ \r
//printk("ipp_blit\n");\r
if (drvdata == NULL) { /* ddl@rock-chips.com : check driver is normal or not */\r
printk("%s drvdata is NULL, IPP driver probe is fail!!\n", __FUNCTION__);\r
{\r
deinterlace_config = (req->deinterlace_enable<<24) | (req->deinterlace_para0<<19) | (req->deinterlace_para1<<14) | (req->deinterlace_para2<<9);\r
DBG("para0 %d, para1 %d, para2 %d,deinterlace_config %x\n",req->deinterlace_para0,req->deinterlace_para1,req->deinterlace_para2,deinterlace_config);\r
- ipp_write((ipp_read(IPP_CONFIG)&0xFE0001FF)|deinterlace_config, IPP_CONFIG);\r
- //printk("IPP_CONFIG2 = 0x%x\n",ipp_read(IPP_CONFIG));\r
+ #ifdef CONFIG_DEINTERLACE\r
+ ipp_write((ipp_read(IPP_CONFIG)&0xFE0001FF)|deinterlace_config, IPP_CONFIG);\r
+ #else\r
+ printk("does not support deinterlacing!\n");\r
+ ipp_write(ipp_read(IPP_CONFIG)&(~DEINTERLACE_ENABLE), IPP_CONFIG); //disable deinterlace\r
+ #endif\r
}\r
else\r
{\r
ipp_write(ipp_read(IPP_CONFIG)&(~STORE_CLIP_MODE), IPP_CONFIG);\r
}\r
\r
+\r
/* Start the operation */\r
ipp_write(8, IPP_INT);// \r
dsb();\r
\r
//printk("ipp_blit_sync -------------------\n");\r
\r
-\r
////If IPP is busy now,wait until it becomes idle\r
mutex_lock(&drvdata->mutex);\r
{\r
goto err_noput;\r
}\r
\r
- \r
+ if(req.deinterlace_enable==2)\r
+ {\r
+ #ifdef CONFIG_DEINTERLACE\r
+ printk("ipp support deinterlacing\n");\r
+ return 0;\r
+ #else\r
+ printk("ipp dose not support deinterlacing\n");\r
+ return -EPERM;\r
+ #endif\r
+ }\r
+\r
if(cmd == IPP_BLIT_SYNC)\r
{\r
ret = ipp_blit_sync(&req);\r