addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 9ea6157ebb362762b77d11271a8135015e7420b2..a7c994f2a3f34fe4350a144cd9881ad6e0845c2f 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -50,7 +50,6 @@ def ThumbFrm    : Format<25>;
 def VFPFrm      : Format<26>;
 
 
-
 //===----------------------------------------------------------------------===//
 
 // ARM Instruction templates.
@@ -59,6 +58,8 @@ def VFPFrm      : Format<26>;
 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
               Format f, string cstr>
   : Instruction {
+  field bits<32> Inst;
+
   let Namespace = "ARM";
 
   bits<4> Opcode = opcod;
@@ -122,11 +123,17 @@ class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
+      asm, "", pattern> {
+  let Inst{5-6}  = 0;
+  let Inst{7-10} = opcod;
+}
 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
            string asm, list<dag> pattern>
   : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-       asm, "", pattern>;
+       asm, "", pattern> {
+  let Inst{5-6}  = 0;
+  let Inst{7-10} = opcod;
+}
 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,