Put VMOVS widening under a command line option, off by default.

It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0e2915fedd2aa23fc264dea78523fcdda85baf19..f8096b98c5924ee87f10398ccd868972f9d77190 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -46,6 +46,10 @@ static cl::opt<bool>
 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
                cl::desc("Enable ARM 2-addr to 3-addr conv"));
 
+static cl::opt<bool>
+WidenVMOVS("widen-vmovs", cl::Hidden,
+           cl::desc("Widen ARM vmovs to vmovd when possible"));
+
 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
 struct ARM_MLxEntry {
   unsigned MLxOpc;     // MLA / MLS opcode
@@ -637,7 +641,8 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     // a VMOVD since that can be converted to a NEON-domain move by
     // NEONMoveFix.cpp.  Check that MI is the original COPY instruction, and
     // that it really defines the whole D-register.
-    if ((DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 &&
+    if (WidenVMOVS &&
+        (DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 &&
         I != MBB.end() && I->isCopy() &&
         I->getOperand(0).getReg() == DestReg &&
         I->getOperand(1).getReg() == SrcReg) {