andd subcc instructions which is used to create the 'cmp' pseudo instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12744 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 8764d4e88703c88885ca304f0c3b1dfa15118c2b..ee397c830c1418a29a6533ba099d91efb31b40e5 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -94,7 +94,8 @@ def SRAri : F3_2<2, 0b100111, "sra">;
 def ADDrr : F3_1<2, 0b000000, "add">;
 
 // Section B.15 - Subtract Instructions, p. 110
-def SUBrr : F3_1<2, 0b000100, "sub">;
+def SUBrr   : F3_1<2, 0b000100, "sub">;
+def SUBCCrr : F3_1<2, 0b010100, "subcc">;
 
 // Section B.18 - Multiply Instructions, p. 113
 def UMULrr : F3_1<2, 0b001010, "umul">;
@@ -133,3 +134,4 @@ def JMPLri : F3_2<2, 0b111000, "jmpl">;              // jmpl [rs1+imm], rd
 // Section B.29 - Write State Register Instructions
 def WRrr : F3_1<2, 0b110000, "wr">;                    // wr rs1, rs2, rd
 def WRri : F3_2<2, 0b110000, "wr">;                    // wr rs1, imm, rd
+

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 8764d4e88703c88885ca304f0c3b1dfa15118c2b..ee397c830c1418a29a6533ba099d91efb31b40e5 100644 (file)
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -94,7 +94,8 @@ def SRAri : F3_2<2, 0b100111, "sra">;
 def ADDrr : F3_1<2, 0b000000, "add">;
 
 // Section B.15 - Subtract Instructions, p. 110
-def SUBrr : F3_1<2, 0b000100, "sub">;
+def SUBrr   : F3_1<2, 0b000100, "sub">;
+def SUBCCrr : F3_1<2, 0b010100, "subcc">;
 
 // Section B.18 - Multiply Instructions, p. 113
 def UMULrr : F3_1<2, 0b001010, "umul">;
@@ -133,3 +134,4 @@ def JMPLri : F3_2<2, 0b111000, "jmpl">;              // jmpl [rs1+imm], rd
 // Section B.29 - Write State Register Instructions
 def WRrr : F3_1<2, 0b110000, "wr">;                    // wr rs1, rs2, rd
 def WRri : F3_2<2, 0b110000, "wr">;                    // wr rs1, imm, rd
+