+++ /dev/null
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible: should contain "rockchip,dwc3"
-- clocks: A list of phandle + clock-specifier pairs for the
- clocks listed in clock-names
-- clock-names: Should contain the following:
- "clk_usb3otg0_ref" Controller reference clk
- "clk_usb3otg0_suspend"Controller suspend clk, can use 24 MHz or 32 KHz
- "aclk_usb3" Master/Core clock, have to be >= 62.5 MHz for SS operation
-
-
-Optional clocks:
- "aclk_usb3otg0" Aclk for specific usb controller clock.
- "aclk_usb3_rksoc_axi_perf" USB AXI perf clock. Not present on all platforms.
- "aclk_usb3_noc" USB noc clock. Not present on all platforms.
- "aclk_usb3_grf" USB grf clock. Not present on all platforms.
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-
-Example device nodes:
-
- usbdrd3_0: usb@fe800000 {
- compatible = "rockchip,dwc3";
- clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
- <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
- <&cru ACLK_USB3_GRF>;
- clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
- "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "aclk_usb3_noc",
- "aclk_usb3_grf";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
- usbdrd_dwc3_0: dwc3 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe800000 0x0 0x100000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "otg";
- tx-fifo-resize;
- status = "disabled";
- };
- };
-