APInt usub_ov(const APInt &RHS, bool &Overflow) const;
APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;
APInt smul_ov(const APInt &RHS, bool &Overflow) const;
+ APInt umul_ov(const APInt &RHS, bool &Overflow) const;
APInt sshl_ov(unsigned Amt, bool &Overflow) const;
/// @returns the bit value at bitPosition
case Intrinsic::ctpop:
case Intrinsic::ctlz:
case Intrinsic::cttz:
- case Intrinsic::uadd_with_overflow:
- case Intrinsic::usub_with_overflow:
case Intrinsic::sadd_with_overflow:
+ case Intrinsic::uadd_with_overflow:
case Intrinsic::ssub_with_overflow:
+ case Intrinsic::usub_with_overflow:
case Intrinsic::smul_with_overflow:
+ case Intrinsic::umul_with_overflow:
case Intrinsic::convert_from_fp16:
case Intrinsic::convert_to_fp16:
case Intrinsic::x86_sse_cvtss2si:
case Intrinsic::uadd_with_overflow:
case Intrinsic::ssub_with_overflow:
case Intrinsic::usub_with_overflow:
- case Intrinsic::smul_with_overflow: {
+ case Intrinsic::smul_with_overflow:
+ case Intrinsic::umul_with_overflow: {
APInt Res;
bool Overflow;
switch (F->getIntrinsicID()) {
case Intrinsic::smul_with_overflow:
Res = Op1->getValue().smul_ov(Op2->getValue(), Overflow);
break;
+ case Intrinsic::umul_with_overflow:
+ Res = Op1->getValue().umul_ov(Op2->getValue(), Overflow);
+ break;
}
Constant *Ops[] = {
ConstantInt::get(F->getContext(), Res),
%i8i1 = type {i8, i1}
+declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8)
+declare {i8, i1} @llvm.usub.with.overflow.i8(i8, i8)
+declare {i8, i1} @llvm.umul.with.overflow.i8(i8, i8)
+
+declare {i8, i1} @llvm.sadd.with.overflow.i8(i8, i8)
+declare {i8, i1} @llvm.ssub.with.overflow.i8(i8, i8)
+declare {i8, i1} @llvm.smul.with.overflow.i8(i8, i8)
+
;;-----------------------------
;; uadd
;;-----------------------------
; CHECK: ret %i8i1 { i8 -2, i1 true }
}
+;;-----------------------------
+;; umul
+;;-----------------------------
+
+define {i8, i1} @umul_1() nounwind {
+entry:
+ %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 100, i8 3)
+ ret {i8, i1} %t
+
+; CHECK: @umul_1
+; CHECK: ret %i8i1 { i8 44, i1 true }
+}
+
+define {i8, i1} @umul_2() nounwind {
+entry:
+ %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 100, i8 2)
+ ret {i8, i1} %t
+
+; CHECK: @umul_2
+; CHECK: ret %i8i1 { i8 -56, i1 false }
+}
+
;;-----------------------------
;; sadd
;;-----------------------------
; CHECK: ret %i8i1 { i8 -10, i1 false }
}
-
-
-declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8)
-declare {i8, i1} @llvm.usub.with.overflow.i8(i8, i8)
-
-declare {i8, i1} @llvm.sadd.with.overflow.i8(i8, i8)
-declare {i8, i1} @llvm.ssub.with.overflow.i8(i8, i8)
-declare {i8, i1} @llvm.smul.with.overflow.i8(i8, i8)
+;;-----------------------------
+;; smul
+;;-----------------------------
; rdar://8501501
define {i8, i1} @smul_1() nounwind {