This opt is now handled in DAG combine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29243 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 2ae607c182c06d513a2467bcbe9e4d5285a7d5ac..4ebe4caad098a203e07541c3d3cb4e002ea8f2e1 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2393,8 +2393,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
   bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
 
   if (isSplatMask(PermMask.Val)) {
-    if (ISD::isBuildVectorAllZeros(V1.Val) || ISD::isBuildVectorAllOnes(V1.Val))
-      return V1;
     if (NumElems <= 4) return Op;
     // Promote it to a v4i32 splat.
     return PromoteSplat(Op, DAG);