MIPS: Avoid pipeline stalls on some MIPS32R2 cores.

The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 03eb0ef9158047b023ee87d8d5d0e45c67c1583f..22ba108d708dee71a072b49401a3056df398c687 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -449,8 +449,20 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
        }
 
        if (cpu_has_mips_r2) {
-               if (cpu_has_mips_r2_exec_hazard)
+               /*
+                * The architecture spec says an ehb is required here,
+                * but a number of cores do not have the hazard and
+                * using an ehb causes an expensive pipeline stall.
+                */
+               switch (current_cpu_type()) {
+               case CPU_M14KC:
+               case CPU_74K:
+                       break;
+
+               default:
                        uasm_i_ehb(p);
+                       break;
+               }
                tlbw(p);
                return;
        }