pdma: pdma@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
+ clocks = <&clk_gates5 1>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
/*aclk_peri_pre*/
<&clk_gates4 3>,/*aclk_peri_axi_matrix*/
- <&clk_gates5 1>,/*aclk_dmac2*/
+ //<&clk_gates5 1>,/*aclk_dmac2*/
<&clk_gates9 15>,/*aclk_peri_niu*/
<&clk_gates4 2>,/*aclk_cpu_peri*/
pdma: pdma@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
+ clocks = <&clk_gates5 1>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
/*aclk_peri_pre*/
//<&clk_gates10 10>,/*aclk_gmac*/
<&clk_gates4 3>,/*aclk_peri_axi_matrix*/
- <&clk_gates5 1>,/*aclk_dmac2*/
+ //<&clk_gates5 1>,/*aclk_dmac2*/
<&clk_gates9 15>,/*aclk_peri_niu*/
<&clk_gates9 2>,/*g_pclk_pmu*/
<&clk_gates9 3>,/*g_pclk_pmu_noc*/
pdma0: pdma@ffb20000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffb20000 0x4000>;
+ clocks = <&clk_gates10 12>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
pdma1: pdma@ff250000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff250000 0x4000>;
+ clocks = <&clk_gates6 3>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
<&clk_gates10 5>,/*aclk_intmem0*/
<&clk_gates10 6>,/*aclk_intmem1*/
<&clk_gates10 7>,/*aclk_intmem2*/
- <&clk_gates10 12>,/*aclk_dma1*/
+ /*<&clk_gates10 12>,*//*aclk_dma1*/
<&clk_gates10 13>,/*aclk_strc_sys*/
<&clk_gates10 4>,/*aclk_intmem*/
/*aclk_peri*/
<&clk_gates6 2>,/*aclk_peri_axi_matrix*/
- <&clk_gates6 3>,/*aclk_dmac2*/
+ /*<&clk_gates6 3>,*//*aclk_dmac2*/
<&clk_gates7 11>,/*aclk_peri_niu*/
<&clk_gates8 12>,/*aclk_peri_mmu*/