dts: rk3036/rk312x/rk3288: add dma clk to fit
authordkl <dkl@rock-chips.com>
Mon, 9 Mar 2015 07:32:28 +0000 (15:32 +0800)
committerdkl <dkl@rock-chips.com>
Mon, 9 Mar 2015 07:34:13 +0000 (15:34 +0800)
commit 75ce2b93307105d10a21e995ab27ec30cc50aaf3

Signed-off-by: dkl <dkl@rock-chips.com>
arch/arm/boot/dts/rk3036.dtsi
arch/arm/boot/dts/rk312x.dtsi
arch/arm/boot/dts/rk3288.dtsi

index daba534a2c04ce70a6a14b4addea26220d012c2d..ce3f200ef14e475be874564ef785e9c9cff87ccf 100755 (executable)
                pdma: pdma@20078000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x20078000 0x4000>;
+                       clocks = <&clk_gates5 1>;
+                       clock-names = "apb_pclk";
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
 
                                /*aclk_peri_pre*/
                                <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
-                               <&clk_gates5 1>,/*aclk_dmac2*/
+                               //<&clk_gates5 1>,/*aclk_dmac2*/
                                <&clk_gates9 15>,/*aclk_peri_niu*/
                                <&clk_gates4 2>,/*aclk_cpu_peri*/
 
index ea52b54ff41f95b7dcc131db3201e6499d9586c4..3d9eb790e0b88f32b1fa3dc4ad71a0cb71343685 100755 (executable)
                pdma: pdma@20078000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x20078000 0x4000>;
+                       clocks = <&clk_gates5 1>;
+                       clock-names = "apb_pclk";
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
                                /*aclk_peri_pre*/
                                //<&clk_gates10 10>,/*aclk_gmac*/
                                <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
-                               <&clk_gates5 1>,/*aclk_dmac2*/
+                               //<&clk_gates5 1>,/*aclk_dmac2*/
                                <&clk_gates9 15>,/*aclk_peri_niu*/
                                <&clk_gates9 2>,/*g_pclk_pmu*/
                                <&clk_gates9 3>,/*g_pclk_pmu_noc*/
index ae24dc4ddc1da8941ebfc5dd286077662a23c831..dfd65ef7959d1cdf3e8985c1592ac6d929f9a6e7 100644 (file)
                pdma0: pdma@ffb20000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0xffb20000 0x4000>;
+                       clocks = <&clk_gates10 12>;
+                       clock-names = "apb_pclk";
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
                pdma1: pdma@ff250000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0xff250000 0x4000>;
+                       clocks = <&clk_gates6 3>;
+                       clock-names = "apb_pclk";
                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
                                <&clk_gates10 5>,/*aclk_intmem0*/
                                <&clk_gates10 6>,/*aclk_intmem1*/
                                <&clk_gates10 7>,/*aclk_intmem2*/
-                               <&clk_gates10 12>,/*aclk_dma1*/
+                               /*<&clk_gates10 12>,*//*aclk_dma1*/
                                <&clk_gates10 13>,/*aclk_strc_sys*/
                                <&clk_gates10 4>,/*aclk_intmem*/
 
 
                                /*aclk_peri*/
                                <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
-                               <&clk_gates6 3>,/*aclk_dmac2*/
+                               /*<&clk_gates6 3>,*//*aclk_dmac2*/
                                <&clk_gates7 11>,/*aclk_peri_niu*/
                                <&clk_gates8 12>,/*aclk_peri_mmu*/