rockchip,prop = <0>;
reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates5 15>, <&clk_gates16 4>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
+ clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
status = "disabled";
};
rockchip,prop = <1>;
reg = <0xff964000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates5 15>, <&clk_gates16 5>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
+ clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
status = "disabled";
};
//enable ref clock
clk_prepare_enable(dsi->phy.refclk);
clk_prepare_enable(dsi->dsi_pclk);
+ clk_prepare_enable(dsi->dsi_pd);
udelay(10);
switch(dsi->host.lane) {
rk32_dsi_set_bits(dsi, 0, phy_shutdownz);
clk_disable_unprepare(dsi->phy.refclk);
clk_disable_unprepare(dsi->dsi_pclk);
+ clk_disable_unprepare(dsi->dsi_pd);
return 0;
}
dsi->phy.refclk = devm_clk_get(&pdev->dev, "clk_mipi_24m");
if (unlikely(IS_ERR(dsi->phy.refclk))) {
- dev_err(&pdev->dev, "get mipi_ref clock fail\n");
+ dev_err(&pdev->dev, "get clk_mipi_24m clock fail\n");
ret = PTR_ERR(dsi->phy.refclk);
//goto probe_err6;
}
//goto probe_err7;
}
+ dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
+ if (unlikely(IS_ERR(dsi->dsi_pd))) {
+ dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
+ ret = PTR_ERR(dsi->dsi_pd);
+ //goto probe_err7;
+ }
+
+
dsi->host.irq = platform_get_irq(pdev, 0);
if (dsi->host.irq < 0) {
dev_err(&pdev->dev, "no irq resource?\n");