.gate_idx = CLK_GATE_ACLK_VEPU_SRC,
.recalc = clksel_recalc_div,
.clksel_con = CRU_CLKSELS_CON(32),
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
+ .set_rate = clkset_rate_freediv_autosel_parents,
+ .round_rate = clk_freediv_round_autosel_parents_rate,
CRU_DIV_SET(0x1f, 0, 32),
CRU_SRC_SET(0x1, 7),
CRU_PARENTS_SET(clk_aclk_vepu_parents),
.mode = gate_mode,
.gate_idx = CLK_GATE_ACLK_VDPU_SRC,
.recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
+ .set_rate = clkset_rate_freediv_autosel_parents,
+ .round_rate = clk_freediv_round_autosel_parents_rate,
.clksel_con = CRU_CLKSELS_CON(32),
CRU_DIV_SET(0x1f, 8, 32),
CRU_SRC_SET(0x1, 15),