Remove simple coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10695 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 4d0916046a0f4d45989d2913e19f8bd2856601b7..1bd8deb37b24cac2d42039718e276429bf21ec82 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -131,21 +131,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
                 assert(r2iit != r2iMap_.end());
                 intervals_[r2iit->second].weight += pow(10.0F, loopDepth);
             }
-
-            // add hints for coalescing
-            unsigned src, dst;
-            if (tii.isMoveInstr(*instr, src, dst)) {
-                if (src >= MRegisterInfo::FirstVirtualRegister) {
-                    Reg2IntervalMap::iterator r2iit = r2iMap_.find(src);
-                    assert(r2iit != r2iMap_.end());
-                    intervals_[r2iit->second].hint = dst;
-                }
-                if (dst >= MRegisterInfo::FirstVirtualRegister) {
-                    Reg2IntervalMap::iterator r2iit = r2iMap_.find(dst);
-                    assert(r2iit != r2iMap_.end());
-                    intervals_[r2iit->second].hint = src;
-                }
-            }
         }
     }
 

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index e677ce8824bba58a4650137d5bd817c4b84b9fb4..b58f63014020b02d0f1b8d8b13d6f50e702ac84d 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -617,17 +617,6 @@ unsigned RA::getFreePhysReg(Intervals::const_iterator cur)
     DEBUG(std::cerr << "\t\tgetting free physical register: ");
     const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
 
-    if (unsigned reg = cur->hint) {
-        if (reg >= MRegisterInfo::FirstVirtualRegister &&
-            v2pMap_.find(reg) != v2pMap_.end())
-            reg = v2pMap_[reg];
-        if (reg && reg < MRegisterInfo::FirstVirtualRegister &&
-            mri_->getRegClass(reg) == rc && !regUse_[reg]) {
-            DEBUG(std::cerr << mri_->getName(reg) << '\n');
-            return reg;
-        }
-    }
-            
     for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
          i != rc->allocation_order_end(*mf_); ++i) {
         unsigned reg = *i;