misched: cleanup reaching def computation

Ignore undef uses completely.
Use a more explicit SlotIndex API.
Add more explicit comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151233 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 29e4df670c33f1a3e1e96d74baf39d18c47e0bb7..2858904fde3cbddc86147c31db999b363857d466 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -408,10 +408,12 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
 
   // Lookup this operand's reaching definition.
   assert(LIS && "vreg dependencies requires LiveIntervals");
-  SlotIndex UseIdx = LIS->getSlotIndexes()->getInstructionIndex(MI);
+  SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
   LiveInterval *LI = &LIS->getInterval(Reg);
-  VNInfo *VNI = LI->getVNInfoAt(UseIdx);
+  VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
+  // VNI will be valid because MachineOperand::readsReg() is checked by caller.
   MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
+  // Phis and other noninstructions (after coalescing) have a NULL Def.
   if (Def) {
     SUnit *DefSU = getSUnit(Def);
     if (DefSU) {
@@ -540,7 +542,7 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
         assert(!IsPostRA && "Virtual register encountered!");
         if (MO.isDef())
           addVRegDefDeps(SU, j);
-        else
+        else if (MO.readsReg()) // ignore undef operands
           addVRegUseDeps(SU, j);
       }
     }