rk3066b: set gpll=297M, cpll=1200M, support GPU 400M

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index b9462c5d875351417ee8c99471d02374fe3bf392..c65d283c23ac0f8340eb95cce6b5fb20050814d4 100644 (file)
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -1013,6 +1013,7 @@ static const struct pll_clk_set gpll_clks[] = {
        _PLL_SET_CLKS(300000,   1,      50,     4),
        _PLL_SET_CLKS(594000,   2,      198,    4),
        _PLL_SET_CLKS(1188000,  2,      99,     1),
+       _PLL_SET_CLKS(1200000,  1,      50,     1),
        _PLL_SET_CLKS(0,        0,       0,     0),
 };
 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
@@ -1517,7 +1518,7 @@ static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
 static struct clk dclk_lcdc0 = {
        .name           = "dclk_lcdc0",
        .mode           = gate_mode,
-       .set_rate       = clksel_set_rate_freediv,
+       .set_rate       = clkset_rate_freediv_autosel_parents,
        .recalc         = clksel_recalc_div,
        .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
        .clksel_con     = CRU_CLKSELS_CON(27),
@@ -1530,7 +1531,7 @@ static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
 static struct clk dclk_lcdc1 = {
        .name           = "dclk_lcdc1",
        .mode           = gate_mode,
-       .set_rate       = clksel_set_rate_freediv,
+       .set_rate       = clkset_rate_freediv_autosel_parents,
        .recalc         = clksel_recalc_div,
        .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
        .clksel_con     = CRU_CLKSELS_CON(28),
@@ -3137,8 +3138,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long
        clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
        clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
        //gpu auto sel
-       clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
-       clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
+       clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
+       clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
        clk_set_rate_nolock(&clk_gpu, 200 * MHZ);
        clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
 }

diff --git a/arch/arm/mach-rk30/include/mach/board.h b/arch/arm/mach-rk30/include/mach/board.h
index 34e3508ac2fd2e8ba4c907a69c0253171aa3219c..cbf02d079490f59db7c8784a1279e469881a3c9a 100755 (executable)
--- a/arch/arm/mach-rk30/include/mach/board.h
+++ b/arch/arm/mach-rk30/include/mach/board.h
@@ -126,6 +126,7 @@ enum _codec_pll {
        codec_pll_768mhz = 768000000,
        codec_pll_798mhz = 798000000,
        codec_pll_1188mhz = 1188000000,
+       codec_pll_1200mhz = 1200000000,
 };
 
 //has extern 27mhz
@@ -154,9 +155,9 @@ enum _codec_pll {
 #if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M)
 #define codec_pll_default codec_pll_768mhz
 #else
-#define codec_pll_default codec_pll_798mhz
+#define codec_pll_default codec_pll_1200mhz
 #endif
-#define periph_pll_default periph_pll_594mhz
+#define periph_pll_default periph_pll_297mhz
 
 #endif