This target does not yet support ISD::BRCONDTWOWAY

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21163 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 773299c38690b2d0082cfcc168d8d29051787449..0d706f80f8fd73e51d8a5e0d36002d016c310c42 100644 (file)
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -47,6 +47,7 @@ namespace {
       addRegisterClass(MVT::f64, PPC64::FPRCRegisterClass);
       
       // PowerPC has no intrinsics for these particular operations
+      setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
       setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
       setOperationAction(ISD::MEMSET, MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY, MVT::Other, Expand);

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index aea11e4b12db29267ced17c9cc4aba3ba0ebe6b1..7ad633a39d825fe66fe62cb81979022d21465c02 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -49,6 +49,7 @@ namespace {
       addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
       
       // PowerPC has no intrinsics for these particular operations
+      setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
       setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
       setOperationAction(ISD::MEMSET, MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY, MVT::Other, Expand);