ARM: dts: imx: add IMX50 SoC device tree
authorGreg Ungerer <gerg@uclinux.org>
Tue, 29 Oct 2013 05:15:56 +0000 (15:15 +1000)
committerShawn Guo <shawn.guo@linaro.org>
Sun, 9 Feb 2014 13:32:20 +0000 (21:32 +0800)
Create device tree source for the Freescale IMX50 SoC. This was based on
the IMX53 source with changes made as necessary.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/boot/dts/imx50.dtsi [new file with mode: 0644]

diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
new file mode 100644 (file)
index 0000000..22a4a8a
--- /dev/null
@@ -0,0 +1,452 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx50-pinfunc.h"
+
+/ {
+       aliases {
+               gpio0 = &gpio1;
+               gpio1 = &gpio2;
+               gpio2 = &gpio3;
+               gpio3 = &gpio4;
+               gpio4 = &gpio5;
+               gpio5 = &gpio6;
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a8";
+                       reg = <0x0>;
+               };
+       };
+
+       tzic: tz-interrupt-controller@0fffc000 {
+               compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               reg = <0x0fffc000 0x4000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ckil {
+                       compatible = "fsl,imx-ckil", "fixed-clock";
+                       clock-frequency = <32768>;
+               };
+
+               ckih1 {
+                       compatible = "fsl,imx-ckih1", "fixed-clock";
+                       clock-frequency = <22579200>;
+               };
+
+               ckih2 {
+                       compatible = "fsl,imx-ckih2", "fixed-clock";
+                       clock-frequency = <0>;
+               };
+
+               osc {
+                       compatible = "fsl,imx-osc", "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&tzic>;
+               ranges;
+
+               aips@50000000 { /* AIPS1 */
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x50000000 0x10000000>;
+                       ranges;
+
+                       spba@50000000 {
+                               compatible = "fsl,spba-bus", "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x50000000 0x40000>;
+                               ranges;
+
+                               esdhc1: esdhc@50004000 {
+                                       compatible = "fsl,imx50-esdhc";
+                                       reg = <0x50004000 0x4000>;
+                                       interrupts = <1>;
+                                       clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                       clock-names = "ipg", "ahb", "per";
+                                       bus-width = <4>;
+                                       status = "disabled";
+                               };
+
+                               esdhc2: esdhc@50008000 {
+                                       compatible = "fsl,imx50-esdhc";
+                                       reg = <0x50008000 0x4000>;
+                                       interrupts = <2>;
+                                       clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                       clock-names = "ipg", "ahb", "per";
+                                       bus-width = <4>;
+                                       status = "disabled";
+                               };
+
+                               uart3: serial@5000c000 {
+                                       compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                                       reg = <0x5000c000 0x4000>;
+                                       interrupts = <33>;
+                                       clocks = <&clks 32>, <&clks 33>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
+
+                               ecspi1: ecspi@50010000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
+                                       reg = <0x50010000 0x4000>;
+                                       interrupts = <36>;
+                                       clocks = <&clks 51>, <&clks 52>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
+
+                               ssi2: ssi@50014000 {
+                                       compatible = "fsl,imx50-ssi", "fsl,imx21-ssi";
+                                       reg = <0x50014000 0x4000>;
+                                       interrupts = <30>;
+                                       clocks = <&clks 49>;
+                                       fsl,fifo-depth = <15>;
+                                       fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
+                                       status = "disabled";
+                               };
+
+                               esdhc3: esdhc@50020000 {
+                                       compatible = "fsl,imx50-esdhc";
+                                       reg = <0x50020000 0x4000>;
+                                       interrupts = <3>;
+                                       clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                       clock-names = "ipg", "ahb", "per";
+                                       bus-width = <4>;
+                                       status = "disabled";
+                               };
+
+                               esdhc4: esdhc@50024000 {
+                                       compatible = "fsl,imx50-esdhc";
+                                       reg = <0x50024000 0x4000>;
+                                       interrupts = <4>;
+                                       clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                       clock-names = "ipg", "ahb", "per";
+                                       bus-width = <4>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       usbotg: usb@53f80000 {
+                               compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                               reg = <0x53f80000 0x0200>;
+                               interrupts = <18>;
+                               clocks = <&clks 124>;
+                               status = "disabled";
+                       };
+
+                       usbh1: usb@53f80200 {
+                               compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                               reg = <0x53f80200 0x0200>;
+                               interrupts = <14>;
+                               clocks = <&clks 125>;
+                               status = "disabled";
+                       };
+
+                       usbh2: usb@53f80400 {
+                               compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                               reg = <0x53f80400 0x0200>;
+                               interrupts = <16>;
+                               clocks = <&clks 108>;
+                               status = "disabled";
+                       };
+
+                       usbh3: usb@53f80600 {
+                               compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                               reg = <0x53f80600 0x0200>;
+                               interrupts = <17>;
+                               clocks = <&clks 108>;
+                               status = "disabled";
+                       };
+
+                       gpio1: gpio@53f84000 {
+                               compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                               reg = <0x53f84000 0x4000>;
+                               interrupts = <50 51>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio2: gpio@53f88000 {
+                               compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                               reg = <0x53f88000 0x4000>;
+                               interrupts = <52 53>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio3: gpio@53f8c000 {
+                               compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                               reg = <0x53f8c000 0x4000>;
+                               interrupts = <54 55>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio4: gpio@53f90000 {
+                               compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                               reg = <0x53f90000 0x4000>;
+                               interrupts = <56 57>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       wdog1: wdog@53f98000 {
+                               compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
+                               reg = <0x53f98000 0x4000>;
+                               interrupts = <58>;
+                               clocks = <&clks 0>;
+                       };
+
+                       gpt: timer@53fa0000 {
+                               compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
+                               reg = <0x53fa0000 0x4000>;
+                               interrupts = <39>;
+                               clocks = <&clks 36>, <&clks 41>;
+                               clock-names = "ipg", "per";
+                       };
+
+                       iomuxc: iomuxc@53fa8000 {
+                               compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
+                               reg = <0x53fa8000 0x4000>;
+                       };
+
+                       gpr: iomuxc-gpr@53fa8000 {
+                               compatible = "fsl,imx50-iomuxc-gpr", "syscon";
+                               reg = <0x53fa8000 0xc>;
+                       };
+
+                       pwm1: pwm@53fb4000 {
+                               #pwm-cells = <2>;
+                               compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
+                               reg = <0x53fb4000 0x4000>;
+                               clocks = <&clks 37>, <&clks 38>;
+                               clock-names = "ipg", "per";
+                               interrupts = <61>;
+                       };
+
+                       pwm2: pwm@53fb8000 {
+                               #pwm-cells = <2>;
+                               compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
+                               reg = <0x53fb8000 0x4000>;
+                               clocks = <&clks 39>, <&clks 40>;
+                               clock-names = "ipg", "per";
+                               interrupts = <94>;
+                       };
+
+                       uart1: serial@53fbc000 {
+                               compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                               reg = <0x53fbc000 0x4000>;
+                               interrupts = <31>;
+                               clocks = <&clks 28>, <&clks 29>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       uart2: serial@53fc0000 {
+                               compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                               reg = <0x53fc0000 0x4000>;
+                               interrupts = <32>;
+                               clocks = <&clks 30>, <&clks 31>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       src: src@53fd0000 {
+                               compatible = "fsl,imx50-src", "fsl,imx51-src";
+                               reg = <0x53fd0000 0x4000>;
+                               #reset-cells = <1>;
+                       };
+
+                       clks: ccm@53fd4000{
+                               compatible = "fsl,imx50-ccm";
+                               reg = <0x53fd4000 0x4000>;
+                               interrupts = <0 71 0x04 0 72 0x04>;
+                               #clock-cells = <1>;
+                       };
+
+                       gpio5: gpio@53fdc000 {
+                               compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                               reg = <0x53fdc000 0x4000>;
+                               interrupts = <103 104>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio6: gpio@53fe0000 {
+                               compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                               reg = <0x53fe0000 0x4000>;
+                               interrupts = <105 106>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       i2c3: i2c@53fec000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+                               reg = <0x53fec000 0x4000>;
+                               interrupts = <64>;
+                               clocks = <&clks 88>;
+                               status = "disabled";
+                       };
+
+                       uart4: serial@53ff0000 {
+                               compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                               reg = <0x53ff0000 0x4000>;
+                               interrupts = <13>;
+                               clocks = <&clks 65>, <&clks 66>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+               };
+
+               aips@60000000 { /* AIPS2 */
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x60000000 0x10000000>;
+                       ranges;
+
+                       uart5: serial@63f90000 {
+                               compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                               reg = <0x63f90000 0x4000>;
+                               interrupts = <86>;
+                               clocks = <&clks 67>, <&clks 68>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       owire: owire@63fa4000 {
+                               compatible = "fsl,imx50-owire", "fsl,imx21-owire";
+                               reg = <0x63fa4000 0x4000>;
+                               clocks = <&clks 159>;
+                               status = "disabled";
+                       };
+
+                       ecspi2: ecspi@63fac000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
+                               reg = <0x63fac000 0x4000>;
+                               interrupts = <37>;
+                               clocks = <&clks 53>, <&clks 54>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       sdma: sdma@63fb0000 {
+                               compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
+                               reg = <0x63fb0000 0x4000>;
+                               interrupts = <6>;
+                               clocks = <&clks 56>, <&clks 56>;
+                               clock-names = "ipg", "ahb";
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
+                       };
+
+                       cspi: cspi@63fc0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
+                               reg = <0x63fc0000 0x4000>;
+                               interrupts = <38>;
+                               clocks = <&clks 55>, <&clks 55>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       i2c2: i2c@63fc4000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+                               reg = <0x63fc4000 0x4000>;
+                               interrupts = <63>;
+                               clocks = <&clks 35>;
+                               status = "disabled";
+                       };
+
+                       i2c1: i2c@63fc8000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+                               reg = <0x63fc8000 0x4000>;
+                               interrupts = <62>;
+                               clocks = <&clks 34>;
+                               status = "disabled";
+                       };
+
+                       ssi1: ssi@63fcc000 {
+                               compatible = "fsl,imx50-ssi", "fsl,imx21-ssi";
+                               reg = <0x63fcc000 0x4000>;
+                               interrupts = <29>;
+                               clocks = <&clks 48>;
+                               fsl,fifo-depth = <15>;
+                               fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
+                               status = "disabled";
+                       };
+
+                       audmux: audmux@63fd0000 {
+                               compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
+                               reg = <0x63fd0000 0x4000>;
+                               status = "disabled";
+                       };
+
+                       fec: ethernet@63fec000 {
+                               compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+                               reg = <0x63fec000 0x4000>;
+                               interrupts = <87>;
+                               clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                               clock-names = "ipg", "ahb", "ptp";
+                               status = "disabled";
+                       };
+               };
+       };
+};