drm/gma500: Add support for SGX interrupts

Add 2D blit status and MMU fault interrupts to the IRQ handler.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>

diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c
index f883f9e4c5240ee923cbaabb3c57b88472983431..624eb36511c5dc226e4cb0817eb1322fc3011326 100644 (file)
--- a/drivers/gpu/drm/gma500/psb_irq.c
+++ b/drivers/gpu/drm/gma500/psb_irq.c
@@ -200,11 +200,64 @@ static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
                mid_pipe_event_handler(dev, 1);
 }
 
+/*
+ * SGX interrupt handler
+ */
+static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
+{
+       struct drm_psb_private *dev_priv = dev->dev_private;
+       u32 val, addr;
+       int error = false;
+
+       if (stat_1 & _PSB_CE_TWOD_COMPLETE)
+               val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
+
+       if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
+               val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
+               addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
+               if (val) {
+                       if (val & _PSB_CBI_STAT_PF_N_RW)
+                               DRM_ERROR("SGX MMU page fault:");
+                       else
+                               DRM_ERROR("SGX MMU read / write protection fault:");
+
+                       if (val & _PSB_CBI_STAT_FAULT_CACHE)
+                               DRM_ERROR("\tCache requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_TA)
+                               DRM_ERROR("\tTA requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_VDM)
+                               DRM_ERROR("\tVDM requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_2D)
+                               DRM_ERROR("\t2D requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_PBE)
+                               DRM_ERROR("\tPBE requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_TSP)
+                               DRM_ERROR("\tTSP requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_ISP)
+                               DRM_ERROR("\tISP requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
+                               DRM_ERROR("\tUSSEPDS requestor");
+                       if (val & _PSB_CBI_STAT_FAULT_HOST)
+                               DRM_ERROR("\tHost requestor");
+
+                       DRM_ERROR("\tMMU failing address is 0x%08x.\n",
+                                 (unsigned int)addr);
+                       error = true;
+               }
+       }
+
+       /* Clear bits */
+       PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
+       PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
+       PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
+}
+
 irqreturn_t psb_irq_handler(int irq, void *arg)
 {
        struct drm_device *dev = arg;
        struct drm_psb_private *dev_priv = dev->dev_private;
        uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
+       u32 sgx_stat_1, sgx_stat_2;
        int handled = 0;
 
        spin_lock(&dev_priv->irqmask_lock);
@@ -233,14 +286,9 @@ irqreturn_t psb_irq_handler(int irq, void *arg)
        }
 
        if (sgx_int) {
-               /* Not expected - we have it masked, shut it up */
-               u32 s, s2;
-               s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
-               s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
-               PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
-               PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
-               /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
-                  we may as well poll even if we add that ! */
+               sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
+               sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
+               psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
                handled = 1;
        }
 
@@ -269,8 +317,13 @@ void psb_irq_preinstall(struct drm_device *dev)
 
        spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 
-       if (gma_power_is_on(dev))
+       if (gma_power_is_on(dev)) {
                PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
+               PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
+               PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
+               PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
+               PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
+       }
        if (dev->vblank[0].enabled)
                dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
        if (dev->vblank[1].enabled)
@@ -286,7 +339,7 @@ void psb_irq_preinstall(struct drm_device *dev)
        /* Revisit this area - want per device masks ? */
        if (dev_priv->ops->hotplug)
                dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
-       dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE;
+       dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
 
        /* This register is safe even if display island is off */
        PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
@@ -295,12 +348,16 @@ void psb_irq_preinstall(struct drm_device *dev)
 
 int psb_irq_postinstall(struct drm_device *dev)
 {
-       struct drm_psb_private *dev_priv =
-           (struct drm_psb_private *) dev->dev_private;
+       struct drm_psb_private *dev_priv = dev->dev_private;
        unsigned long irqflags;
 
        spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 
+       /* Enable 2D and MMU fault interrupts */
+       PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
+       PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
+       PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
+
        /* This register is safe even if display island is off */
        PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
        PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);