arm64: dts: rockchip: change dr_mode for rk3399 dwc3

The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations. For rk3399, it has
two DWC3 controllers, we set DRD for DWC3_0 and Host only for DWC3_1
by default.

Change-Id: Ia0063e04e48770d8d0ec7ec86cb621c5e9979fb9
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
index a5911c8ed015497346a1e69c99aeb4026b0547f4..9dec42dad55ed3b447fd18617bc7a75afd1594d3 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
@@ -460,10 +460,6 @@
        };
 };
 
-&usbdrd_dwc3_0 {
-       dr_mode = "peripheral";
-};
-
 &pinctrl {
        isp {
                cif_clkout: cif-clkout {

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 634ca036e25a333feb69579f3150dccac0375566..020996bb185eee39f4d858e9f4511b12c8bb6502 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -480,7 +480,7 @@
                        compatible = "snps,dwc3";
                        reg = <0x0 0xfe900000 0x0 0x100000>;
                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
-                       dr_mode = "otg";
+                       dr_mode = "host";
                        phys = <&u2phy1_otg>, <&tcphy1 1>;
                        phy-names = "usb2-phy", "usb3-phy";
                        phy_type = "utmi_wide";