}
static struct device_attribute cec_attrs[] = {
- __ATTR(logic, 0666, cec_logic_show, cec_logic_store),
- __ATTR(phy, 0666, cec_phy_show, cec_phy_store),
- __ATTR(enable, 0666, cec_enable_show, cec_enable_store),
+ __ATTR(logic, S_IRUGO | S_IWUSR, cec_logic_show, cec_logic_store),
+ __ATTR(phy, S_IRUGO | S_IWUSR, cec_phy_show, cec_phy_store),
+ __ATTR(enable, S_IRUGO | S_IWUSR, cec_enable_show, cec_enable_store),
__ATTR(stat, S_IRUGO, cec_state_show, NULL),
};
audio_cfg.rate = rate;
- if (params->flags == HW_PARAMS_FLAG_NLPCM)
- audio_cfg.type = HDMI_AUDIO_NLPCM;
- else
- audio_cfg.type = HDMI_AUDIO_LPCM;
+ /*
+ *if (params->flags == HW_PARAMS_FLAG_NLPCM)
+ * audio_cfg.type = HDMI_AUDIO_NLPCM;
+ *else
+ */
+ audio_cfg.type = HDMI_AUDIO_LPCM;
audio_cfg.channel = params_channels(params);
audio_cfg.word_length = HDMI_AUDIO_WORD_LENGTH_16bit;
#include "rockchip-hdmi.h"
-#include "../../edid.h"
+#include "../../fbdev/edid.h"
#ifdef EDIDDEBUG
#define EDBG DBG
{
unsigned int ddc_offset, native_dtd_num, cur_offset = 4;
unsigned int tag, IEEEOUI = 0, count, i;
+ struct fb_videomode *vmode;
if (!buf)
return E_HDMI_EDID_PARAM;
}
/* Parse DTD */
- struct fb_videomode *vmode =
- kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
+ vmode = kmalloc(sizeof(*vmode), GFP_KERNEL);
if (!vmode)
return E_HDMI_EDID_SUCCESS;
}
kfree(vmode);
-#endif
return E_HDMI_EDID_SUCCESS;
}
ret = devm_request_irq(hdmi_dev->hdmi->dev,
hdmi_dev->irq,
rockchip_hdmiv1_irq_func,
- IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+ IRQF_TRIGGER_HIGH,
dev_name(hdmi_dev->hdmi->dev),
hdmi_dev->hdmi);
if (ret) {
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/of_gpio.h>
hdmi_dev->clk_on |= HDMI_EXT_PHY_CLK_ON;
}
} else if ((hdmi_dev->clk_on & HDMI_PD_ON) == 0) {
- if (!hdmi_dev->pd) {
- hdmi_dev->pd = devm_clk_get(hdmi_dev->dev, "pd_hdmi");
- if (IS_ERR(hdmi_dev->pd)) {
- dev_err(hdmi_dev->dev,
- "Unable to get hdmi pd\n");
- return -1;
- }
- }
- clk_prepare_enable(hdmi_dev->pd);
+ pm_runtime_get_sync(hdmi_dev->dev);
hdmi_dev->clk_on |= HDMI_PD_ON;
}
if (hdmi_dev->clk_on == 0)
return 0;
- if ((hdmi_dev->clk_on & HDMI_PD_ON) && (hdmi_dev->pd)) {
- clk_disable_unprepare(hdmi_dev->pd);
+ if ((hdmi_dev->clk_on & HDMI_PD_ON)) {
+ pm_runtime_put(hdmi_dev->dev);
hdmi_dev->clk_on &= ~HDMI_PD_ON;
}
dev_err(&pdev->dev, "failed to get hdmi reset: %d\n", ret);
goto failed;
}
-
+ pm_runtime_enable(hdmi_dev->dev);
/*enable pd and pclk and hdcp_clk*/
if (rockchip_hdmiv2_clk_enable(hdmi_dev) < 0) {
ret = -ENXIO;
SUPPORT_YCBCR_INPUT |
SUPPORT_1080I |
SUPPORT_480I_576I;
- if (rockchip_get_cpu_version())
- rk_hdmi_property.feature |=
- SUPPORT_YUV420 |
- SUPPORT_DEEP_10BIT;
+ /*
+ *if (rockchip_get_cpu_version())
+ * rk_hdmi_property.feature |=
+ * SUPPORT_YUV420 |
+ * SUPPORT_DEEP_10BIT;
+ */
} else {
ret = -ENXIO;
goto failed1;
if ((stat & EXT_PHY_PPLL_LOCK_STATUS_MASK) == 0) {
stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
dev_err(hdmi_dev->hdmi->dev,
- "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
+ "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
(stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
return -1;
}
if ((stat & m_PHY_LOCK) == 0) {
stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
dev_err(hdmi_dev->hdmi->dev,
- "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
+ "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
(stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
return -1;
}
#define RK322X_PLL_PDATA_DEN BIT(11 + 16)
#define RK322X_PLL_PDATA_EN (BIT(11) | BIT(11 + 16))
+#ifndef RK322X_GRF_SOC_CON2
+#define RK322X_GRF_SOC_CON2 RK3228_GRF_SOC_CON2
+#endif
+#ifndef RK322X_GRF_SOC_CON6
+#define RK322X_GRF_SOC_CON6 RK3228_GRF_SOC_CON6
+#endif
+
struct ext_pll_config_tab {
u32 pix_clock;
u32 tmdsclock;