Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...

Pull ARM SoC non-urgent fixes from Olof Johansson:
 "A handful of fixes that came in and didn't seem warranted to go in
  through the 4.3-rc cycle.

   - MAINTAINERS updates for one of the Broadcom platforms and lpc18xx
   - A couple of non-critical Davinci bugfixes
   - A fix to reset irq affinity for TI platforms (silences a warning at
     reboot)"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  MAINTAINERS: update lpc18xx entry with more drivers
  soc: ti: reset irq affinity before freeing irq
  ARM: cns3xxx: pci: avoid potential stack overflow
  ARM: davinci: clock: Correct return values for API functions
  ARM: davinci: re-use %*ph specifier
  MAINTAINERS: add entry for the Broadcom Northstar Plus SoCs

diff --git a/MAINTAINERS b/MAINTAINERS
index 8f10834124a94fa4134aeef157702e681a9a3e9d..bc93927db022124006827237a96759d12ab9f1f5 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1233,6 +1233,13 @@ ARM/LPC18XX ARCHITECTURE
 M:     Joachim Eastwood <manabian@gmail.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
+F:     arch/arm/boot/dts/lpc43*
+F:     drivers/clk/nxp/clk-lpc18xx*
+F:     drivers/clocksource/time-lpc32xx.c
+F:     drivers/i2c/busses/i2c-lpc2k.c
+F:     drivers/memory/pl172.c
+F:     drivers/mtd/spi-nor/nxp-spifi.c
+F:     drivers/rtc/rtc-lpc24xx.c
 N:     lpc18xx
 
 ARM/MAGICIAN MACHINE SUPPORT
@@ -2388,19 +2395,27 @@ L:      linux-scsi@vger.kernel.org
 S:     Supported
 F:     drivers/scsi/bnx2i/
 
-BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+BROADCOM IPROC ARM ARCHITECTURE
 M:     Ray Jui <rjui@broadcom.com>
 M:     Scott Branden <sbranden@broadcom.com>
+M:     Jon Mason <jonmason@broadcom.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:     bcm-kernel-feedback-list@broadcom.com
 T:     git git://github.com/broadcom/cygnus-linux.git
 S:     Maintained
 N:     iproc
 N:     cygnus
+N:     nsp
 N:     bcm9113*
 N:     bcm9583*
-N:     bcm583*
+N:     bcm9585*
+N:     bcm9586*
+N:     bcm988312
 N:     bcm113*
+N:     bcm583*
+N:     bcm585*
+N:     bcm586*
+N:     bcm88312
 
 BROADCOM BRCMSTB GPIO DRIVER
 M:     Gregory Fong <gregory.0xf0@gmail.com>

diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index c622c306c390719f95cfac1eb8b3eff46f38c340..47905a50e0757e94c1300ec98a3924d9a51b7a5b 100644 (file)
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -65,8 +65,9 @@ static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
 
        /*
         * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
-        * we still want to access it. For this to work, we must place
-        * the first device on the same bus as the CNS PCI bridge.
+        * we still want to access it.
+        * We place the host bridge on bus 0, and the directly connected
+        * device on bus 1, slot 0.
         */
        if (busno == 0) { /* internal PCIe bus, host bridge device */
                if (devfn == 0) /* device# and function# are ignored by hw */
@@ -211,58 +212,46 @@ static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
        }
 }
 
+static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
+                                        int where, int size, u32 val)
+{
+       void __iomem *base = cnspci->host_regs + (where & 0xffc);
+       u32 v;
+       u32 mask = (0x1ull << (size * 8)) - 1;
+       int shift = (where % 4) * 8;
+
+       v = readl_relaxed(base + (where & 0xffc));
+
+       v &= ~(mask << shift);
+       v |= (val & mask) << shift;
+
+       writel_relaxed(v, base + (where & 0xffc));
+       readl_relaxed(base + (where & 0xffc));
+}
+
 static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
 {
-       int port = cnspci->port;
-       struct pci_sys_data sd = {
-               .private_data = cnspci,
-       };
-       struct pci_bus bus = {
-               .number = 0,
-               .ops = &cns3xxx_pcie_ops,
-               .sysdata = &sd,
-       };
        u16 mem_base  = cnspci->res_mem.start >> 16;
        u16 mem_limit = cnspci->res_mem.end   >> 16;
        u16 io_base   = cnspci->res_io.start  >> 16;
        u16 io_limit  = cnspci->res_io.end    >> 16;
-       u32 devfn = 0;
-       u8 tmp8;
-       u16 pos;
-       u16 dc;
-
-       pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
-       pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
-       pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
 
-       pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
-       pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
-       pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
-
-       pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
-       pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit);
-       pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
-       pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit);
+       cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
+       cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
+       cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
+       cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
+       cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
+       cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
+       cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
 
        if (!cnspci->linked)
                return;
 
        /* Set Device Max_Read_Request_Size to 128 byte */
-       bus.number = 1; /* directly connected PCIe device */
-       devfn = PCI_DEVFN(0, 0);
-       pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
-       pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
-       if (dc & PCI_EXP_DEVCTL_READRQ) {
-               dc &= ~PCI_EXP_DEVCTL_READRQ;
-               pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
-               pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
-               if (dc & PCI_EXP_DEVCTL_READRQ)
-                       pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
-               else
-                       pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
-       }
+       pcie_bus_config = PCIE_BUS_PEER2PEER;
+
        /* Disable PCIe0 Interrupt Mask INTA to INTD */
-       __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+       __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
 }
 
 static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 1a0898c1c17ec40f4c66f2d3fa0f4c7d9da9f357..bbdd2d614b4978022f0b9f51a7abc898dc0b5e0f 100644 (file)
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -546,9 +546,7 @@ static int dm6444evm_msp430_get_pins(void)
        if (status < 0)
                return status;
 
-       dev_dbg(&dm6446evm_msp->dev,
-               "PINS: %02x %02x %02x %02x\n",
-               buf[0], buf[1], buf[2], buf[3]);
+       dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
 
        return (buf[3] << 8) | buf[2];
 }

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index c70bb0a4dfb44cb288e671f727199c07a1d0af5f..3caff9637a82e759db99ee78c7677340f1f3e560 100644 (file)
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -97,7 +97,9 @@ int clk_enable(struct clk *clk)
 {
        unsigned long flags;
 
-       if (clk == NULL || IS_ERR(clk))
+       if (!clk)
+               return 0;
+       else if (IS_ERR(clk))
                return -EINVAL;
 
        spin_lock_irqsave(&clockfw_lock, flags);
@@ -124,7 +126,7 @@ EXPORT_SYMBOL(clk_disable);
 unsigned long clk_get_rate(struct clk *clk)
 {
        if (clk == NULL || IS_ERR(clk))
-               return -EINVAL;
+               return 0;
 
        return clk->rate;
 }
@@ -159,8 +161,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
        unsigned long flags;
        int ret = -EINVAL;
 
-       if (clk == NULL || IS_ERR(clk))
-               return ret;
+       if (!clk)
+               return 0;
+       else if (IS_ERR(clk))
+               return -EINVAL;
 
        if (clk->set_rate)
                ret = clk->set_rate(clk, rate);
@@ -181,7 +185,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 {
        unsigned long flags;
 
-       if (clk == NULL || IS_ERR(clk))
+       if (!clk)
+               return 0;
+       else if (IS_ERR(clk))
                return -EINVAL;
 
        /* Cannot change parent on enabled clock */

diff --git a/drivers/soc/ti/knav_qmss_acc.c b/drivers/soc/ti/knav_qmss_acc.c
index ef6f69db0bd04c06caa6c1b955e3dbbebc91677a..b98fe56598ddf184aeeb15efa4820dea529de383 100644 (file)
--- a/drivers/soc/ti/knav_qmss_acc.c
+++ b/drivers/soc/ti/knav_qmss_acc.c
@@ -261,6 +261,10 @@ static int knav_range_setup_acc_irq(struct knav_range_info *range,
        if (old && !new) {
                dev_dbg(kdev->dev, "setup-acc-irq: freeing %s for channel %s\n",
                        acc->name, acc->name);
+               ret = irq_set_affinity_hint(irq, NULL);
+               if (ret)
+                       dev_warn(range->kdev->dev,
+                                "Failed to set IRQ affinity\n");
                free_irq(irq, range);
        }