SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
+ RegInfo = TM.getRegisterInfo();
+
// Set up the register classes.
addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
SDValue Callee = TheCall->getCallee();
bool isVarArg = TheCall->isVarArg();
DebugLoc dl = Op.getDebugLoc();
+ MachineFunction &MF = DAG.getMachineFunction();
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, dl, SystemZ::R15D, getPointerTy());
-
- SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
- StackPtr,
- DAG.getIntPtrConstant(VA.getLocMemOffset()));
-
+ StackPtr =
+ DAG.getCopyFromReg(Chain, dl,
+ (RegInfo->hasFP(MF) ?
+ SystemZ::R11D : SystemZ::R15D),
+ getPointerTy());
+
+ SDValue PtrOff =
+ DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ StackPtr,
+ DAG.getIntPtrConstant(160+VA.getLocMemOffset()));
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
PseudoSourceValue::getStack(),
#define LLVM_TARGET_SystemZ_ISELLOWERING_H
#include "SystemZ.h"
+#include "SystemZRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetLowering.h"
private:
const SystemZSubtarget &Subtarget;
const SystemZTargetMachine &TM;
+ const SystemZRegisterInfo *RegInfo;
};
} // namespace llvm
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,