clk: rockchip: rk3399: add SCLK_PCIEPHY_REF100M for PCIe

Change-Id: Iead548d47a627745267acbcc73d401f73c68a702
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index bb32739083e385768e6f695f425b76df20da7258..73da861158d6576f9fb7512026c0791ed223ec1e 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -878,7 +878,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(6), 2, GFLAGS),
 
-       COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", 0,
+       COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
                        RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
                        RK3399_CLKGATE_CON(12), 6, GFLAGS),
        MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index fce4e0bf79ff590eed0f55b3132d71b5dc388b5b..13f23767d404b7f895c997e870bed5ce6ed1da2f 100644 (file)
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -130,6 +130,7 @@
 #define SCLK_DPHY_TX1RX1_CFG           164
 #define SCLK_DPHY_RX0_CFG              165
 #define SCLK_RMII_SRC                  166
+#define SCLK_PCIEPHY_REF100M           167
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181