#
menu "HDMI"
config HDMI
- tristate "HDMI support"
- depends on FB_RK29
-
-if HDMI
-
-config HDMI_OLD
- default y
- bool "old hdmi support"
- help
- nothing
-if HDMI_OLD
-source "drivers/video/hdmi/hdmi-old/Kconfig"
-endif
+ bool "HDMI support"
-config HDMI_NEW
- bool "new hdmi support"
- help
- nothing
-if HDMI_NEW
-source "drivers/video/hdmi/hdmi-new/Kconfig"
-endif
-
-config HDMI_DEBUG
- bool "hdmi debug"
+if HDMI
+source "drivers/video/hdmi/chips/Kconfig"
+#config HDMI_DUAL_DISP
+# bool "hdmi support dual display"
+# help
+# nothing
+#config HDMI_DEBUG
+# bool "hdmi debug"
endif
endmenu
-obj-$(CONFIG_HDMI_OLD) += hdmi-old/
-obj-$(CONFIG_HDMI_NEW) += hdmi-new/
+obj-y += hdmi-core.o hdmi-sysfs.o hdmi-fb.o hdmi-codec.o hdmi-backlight.o
+obj-y += chips/
--- /dev/null
+choice
+ prompt "HDMI chips select"
+config ANX7150
+ bool "anx7150"
+config ANX9030
+ bool "anx9030"
+endchoice
--- /dev/null
+obj-$(CONFIG_ANX7150) += anx7150_hw.o anx7150.o
+
--- /dev/null
+#include <linux/kernel.h>\r
+#include <linux/delay.h>\r
+#include <linux/module.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/hdmi.h>\r
+#include <linux/i2c.h>\r
+#include <linux/interrupt.h>\r
+#include <mach/gpio.h>\r
+#include <mach/iomux.h>\r
+\r
+\r
+\r
+#include "anx7150.h"\r
+#include "anx7150_hw.h"\r
+int anx7150_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)\r
+{\r
+ client->addr = ANX7150_I2C_ADDR0;\r
+ return i2c_master_reg8_recv(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
+}\r
+int anx7150_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)\r
+{\r
+ client->addr = ANX7150_I2C_ADDR0;\r
+ return i2c_master_reg8_send(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
+}\r
+int anx7150_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)\r
+{\r
+ client->addr = ANX7150_I2C_ADDR1;\r
+ return i2c_master_reg8_recv(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
+}\r
+int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)\r
+{\r
+ client->addr = ANX7150_I2C_ADDR1;\r
+ return i2c_master_reg8_send(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
+}\r
+\r
+static int anx7150_precent(struct hdmi *hdmi)\r
+{\r
+ struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
+\r
+ return gpio_get_value(anx->client->irq)?0:1;\r
+}\r
+static int anx7150_param_chg(struct anx7150_pdata *anx)\r
+{\r
+ int resolution_real;\r
+\r
+ hdmi_switch_fb(anx->hdmi, HDMI_ENABLE);\r
+ resolution_real = ANX7150_Get_Optimal_resolution(anx->hdmi->resolution);\r
+ HDMI_Set_Video_Format(resolution_real);\r
+ HDMI_Set_Audio_Fs(anx->hdmi->audio_fs);\r
+ ANX7150_API_HDCP_ONorOFF(anx->hdmi->hdcp_on);\r
+ ANX7150_API_System_Config();\r
+ ANX7150_Config_Video(anx->client);\r
+\r
+ ANX7150_Config_Audio(anx->client);\r
+ ANX7150_Config_Packet(anx->client);\r
+ ANX7150_HDCP_Process(anx->client, anx->hdmi->display_on);\r
+ ANX7150_PLAYBACK_Process();\r
+\r
+ return 0;\r
+}\r
+\r
+static int anx7150_insert(struct hdmi *hdmi)\r
+{\r
+ int tmo = 10;\r
+ struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
+\r
+ if(anx->init == 1)\r
+ return -1;\r
+\r
+ anx7150_plug(anx->client);\r
+ hdmi_dbg(&anx->client->dev, "parse edid\n");\r
+ if(ANX7150_Parse_EDID(anx->client,&anx->dev) < 0)\r
+ {\r
+ dev_info(hdmi->dev, "parse EDID error\n");\r
+ anx7150_unplug(anx->client);\r
+ return -1;\r
+ }\r
+ \r
+ while(--tmo && ANX7150_GET_SENSE_STATE(anx->client) != 1)\r
+ mdelay(10);\r
+ if(tmo <= 0)\r
+ {\r
+ anx7150_unplug(anx->client);\r
+ dev_dbg(hdmi->dev, "get sense_state error\n");\r
+ return -1;\r
+ }\r
+ hdmi_set_spk(HDMI_DISABLE);\r
+ hdmi_set_backlight(HDMI_DISABLE);\r
+ hdmi->scale = hdmi->scale_set;\r
+ anx7150_param_chg(anx);\r
+ return 0;\r
+}\r
+static int anx7150_remove(struct hdmi *hdmi)\r
+{\r
+ struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
+\r
+ if(anx->init == 1)\r
+ return -1;\r
+\r
+ anx7150_unplug(anx->client);\r
+ hdmi->scale = 100;\r
+ hdmi_set_spk(HDMI_ENABLE);\r
+ hdmi_switch_fb(hdmi, HDMI_DISABLE);\r
+ hdmi_set_backlight(HDMI_ENABLE);\r
+\r
+ return 0;\r
+}\r
+\r
+static int anx7150_set_param(struct hdmi *hdmi)\r
+{\r
+ struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
+ if(anx->init == 1)\r
+ return 0;\r
+\r
+ anx7150_param_chg(anx);\r
+ return 0;\r
+}\r
+static int anx7150_init(struct hdmi *hdmi)\r
+{\r
+ struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
+\r
+ anx->init = 0;\r
+ hdmi_changed(hdmi, 1);\r
+\r
+ return 0;\r
+}\r
+static struct hdmi_ops anx7150_ops = {\r
+ .set_param = anx7150_set_param,\r
+ .hdmi_precent = anx7150_precent,\r
+ .insert = anx7150_insert,\r
+ .remove = anx7150_remove,\r
+ .init = anx7150_init,\r
+};\r
+#ifdef CONFIG_HAS_EARLYSUSPEND\r
+static void anx7150_early_suspend(struct early_suspend *h)\r
+{\r
+ struct anx7150_pdata *anx = container_of(h,\r
+ struct anx7150_pdata,\r
+ early_suspend);\r
+ dev_info(&anx->client->dev, "anx7150 enter early suspend\n");\r
+ hdmi_suspend(anx->hdmi);\r
+ return;\r
+}\r
+\r
+static void anx7150_early_resume(struct early_suspend *h)\r
+{\r
+ struct anx7150_pdata *anx = container_of(h,\r
+ struct anx7150_pdata,\r
+ early_suspend);\r
+ dev_info(&anx->client->dev, "anx7150 exit early suspend\n");\r
+ hdmi_resume(anx->hdmi);\r
+ return;\r
+}\r
+#endif\r
+\r
+static int anx7150_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)\r
+{\r
+ int ret = 0;\r
+ struct hdmi *hdmi = NULL;\r
+ struct anx7150_pdata *anx = NULL;\r
+\r
+ hdmi = hdmi_register(sizeof(struct anx7150_pdata), &client->dev);\r
+ if (!hdmi)\r
+ {\r
+ dev_err(&client->dev, "fail to register hdmi\n");\r
+ return -ENOMEM;\r
+ }\r
+ hdmi->ops = &anx7150_ops;\r
+ hdmi->display_on = HDMI_DISABLE;\r
+ hdmi->hdcp_on = HDMI_DISABLE;\r
+ hdmi->audio_fs = HDMI_I2S_DEFAULT_Fs;\r
+ hdmi->resolution = HDMI_DEFAULT_RESOLUTION;\r
+ hdmi->dual_disp = DUAL_DISP_CAP;\r
+ hdmi->mode = DISP_ON_LCD;\r
+ hdmi->scale = 100;\r
+ hdmi->scale_set = 100;\r
+ \r
+ anx = hdmi_priv(hdmi);\r
+ anx->init = 1;\r
+ anx->hdmi = hdmi;\r
+ i2c_set_clientdata(client, anx);\r
+ anx->client = client;\r
+\r
+ if((ret = gpio_request(client->irq, "hdmi gpio")) < 0)\r
+ {\r
+ dev_err(&client->dev, "fail to request gpio %d\n", client->irq);\r
+ goto err_hdmi_unregister;\r
+ }\r
+ //gpio_pull_updown(client->irq,0);\r
+ gpio_direction_input(client->irq);\r
+\r
+ if(anx7150_detect_device(anx) < 0)\r
+ {\r
+ dev_err(&client->dev, "anx7150 is not exist\n");\r
+ ret = -EIO;\r
+ goto err_gpio_free;\r
+ }\r
+\r
+#ifdef CONFIG_HAS_EARLYSUSPEND\r
+ anx->early_suspend.suspend = anx7150_early_suspend;\r
+ anx->early_suspend.resume = anx7150_early_resume;\r
+ anx->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 1;\r
+ register_early_suspend(&anx->early_suspend);\r
+#endif\r
+ anx7150_unplug(anx->client);\r
+ dev_info(&client->dev, "anx7150 i2c probe ok\n");\r
+ return 0;\r
+err_gpio_free:\r
+ gpio_free(client->irq);\r
+err_hdmi_unregister:\r
+ hdmi_unregister(hdmi);\r
+ anx = NULL;\r
+ return ret;\r
+}\r
+\r
+static int __devexit anx7150_i2c_remove(struct i2c_client *client)\r
+{\r
+ struct anx7150_pdata *anx = (struct anx7150_pdata *)i2c_get_clientdata(client);\r
+ struct hdmi *hdmi = anx->hdmi;\r
+\r
+ gpio_free(client->irq);\r
+ hdmi_unregister(hdmi);\r
+ anx = NULL;\r
+ return 0;\r
+}\r
+static const struct i2c_device_id anx7150_id[] = {\r
+ { "anx7150", 0 },\r
+ { }\r
+};\r
+\r
+static struct i2c_driver anx7150_i2c_driver = {\r
+ .driver = {\r
+ .name = "anx7150",\r
+ .owner = THIS_MODULE,\r
+ },\r
+ .probe = &anx7150_i2c_probe,\r
+ .remove = &anx7150_i2c_remove,\r
+ .id_table = anx7150_id,\r
+};\r
+\r
+\r
+static int __init anx7150_module_init(void)\r
+{\r
+ return i2c_add_driver(&anx7150_i2c_driver);\r
+}\r
+\r
+static void __exit anx7150_module_exit(void)\r
+{\r
+ i2c_del_driver(&anx7150_i2c_driver);\r
+}\r
+\r
+module_init(anx7150_module_init);\r
+//fs_initcall(anx7150_module_init);\r
+module_exit(anx7150_module_exit);\r
+\r
+\r
--- /dev/null
+#ifndef _ANX7150_H\r
+#define _ANX7150_H\r
+\r
+#include <linux/hdmi.h>\r
+#include <linux/earlysuspend.h>\r
+\r
+\r
+#define ANX7150_I2C_ADDR0 0X39\r
+#define ANX7150_I2C_ADDR1 0X3d\r
+\r
+#define ANX7150_SCL_RATE 100 * 1000\r
+\r
+\r
+\r
+/* HDMI auto switch */\r
+#define HDMI_AUTO_SWITCH HDMI_ENABLE\r
+\r
+/* HDMI reciver status */\r
+#define HDMI_RECIVER_INACTIVE 0\r
+#define HDMI_RECIVER_ACTIVE 1\r
+\r
+/* ANX7150 reciver HPD Status */\r
+#define HDMI_RECIVER_UNPLUG 0\r
+#define HDMI_RECIVER_PLUG 1\r
+\r
+#define LCD 0\r
+#define HDMI 1\r
+\r
+#define RK29_OUTPUT_STATUS_LCD LCD\r
+#define RK29_OUTPUT_STATUS_HDMI HDMI\r
+\r
+/* HDMI HDCP ENABLE */\r
+#define ANX7150_HDCP_EN HDMI_DISABLE\r
+\r
+/* ANX7150 state machine */\r
+enum{\r
+ HDMI_INITIAL = 1,\r
+ WAIT_HOTPLUG,\r
+ READ_PARSE_EDID,\r
+ WAIT_RX_SENSE,\r
+ WAIT_HDMI_ENABLE,\r
+ SYSTEM_CONFIG,\r
+ CONFIG_VIDEO,\r
+ CONFIG_AUDIO,\r
+ CONFIG_PACKETS,\r
+ HDCP_AUTHENTICATION,\r
+ PLAY_BACK,\r
+ RESET_LINK,\r
+ UNKNOWN,\r
+};\r
+\r
+\r
+struct anx7150_dev_s{\r
+ struct i2c_driver *i2c_driver;\r
+ struct fasync_struct *async_queue;\r
+ struct workqueue_struct *workqueue;\r
+ struct delayed_work delay_work;\r
+ struct miscdevice *mdev;\r
+ void (*notifier_callback)(struct anx7150_dev_s *);\r
+ int anx7150_detect;\r
+ int resolution_set;\r
+ int resolution_real;\r
+ int i2s_Fs;\r
+ int hdmi_enable;\r
+ int hdmi_auto_switch;\r
+ int reciver_status;\r
+ int HPD_change_cnt;\r
+ int HPD_status;\r
+ int rk29_output_status;\r
+ int hdcp_enable;\r
+ int parameter_config;\r
+ int rate;\r
+ int fb_switch_state;\r
+\r
+ struct hdmi *hdmi;\r
+};\r
+\r
+struct anx7150_pdata {\r
+ int irq;\r
+ int gpio;\r
+ int init;\r
+ int is_early_suspend;\r
+ int is_changed;\r
+ struct delayed_work work;\r
+ struct hdmi *hdmi;\r
+ struct i2c_client *client;\r
+ struct anx7150_dev_s dev;\r
+#ifdef CONFIG_HAS_EARLYSUSPEND\r
+ struct early_suspend early_suspend;
+#endif\r
+};\r
+\r
+\r
+\r
+int anx7150_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val);\r
+int anx7150_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val);\r
+int anx7150_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val);\r
+int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val);\r
+\r
+#endif\r
--- /dev/null
+#include <linux/delay.h>\r
+#include <linux/i2c.h>\r
+#include <linux/hdmi.h>\r
+\r
+\r
+#include "anx7150.h"\r
+#include "anx7150_hw.h"\r
+//#ifdef ITU656\r
+struct ANX7150_video_timingtype ANX7150_video_timingtype_table =\r
+{\r
+ //640x480p-60hz\r
+ {0x20/*H_RES_LOW*/, 0x03/*H_RES_HIGH*/,0x80 /*ACT_PIX_LOW*/,0x02 /*ACT_PIX_HIGH*/,\r
+ 0x60/*HSYNC_WIDTH_LOW*/,0x00 /*HSYNC_WIDTH_HIGH*/,0x30 /*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
+ 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/,0x02 /*VSYNC_WIDTH*/, 0x21/*V_BP_LINE*/,\r
+ 0x0a/*V_FP_LINE*/,0x10 /*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
+ //720x480p-60hz\r
+ {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
+ 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x3c/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x06/*VSYNC_WIDTH*/, 0x1e/*V_BP_LINE*/,\r
+ 0x09/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
+ //720p-60hz\r
+ {0x72/*H_RES_LOW*/, 0x06/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
+ 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
+ 0x05/*V_FP_LINE*/, 0x6e/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+ //1080i-60hz\r
+ {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+ 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
+ 0x02/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+ //720x480i-60hz\r
+ {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
+ 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x39/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
+ 0x04/*V_FP_LINE*/, 0x13/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol}, //update\r
+ //1080p-60hz\r
+ {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+ 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
+ 0x04/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+ //576p-50hz\r
+ {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
+ 0x40/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x44/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
+ 0x40/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x27/*V_BP_LINE*/,\r
+ 0x05/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
+ //720p-50hz\r
+ {0xbc/*H_RES_LOW*/, 0x07/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
+ 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
+ 0x05/*V_FP_LINE*/, 0xb8/*H_FP_LOW*/, 0x01/*H_FP_HIGH*/,\r
+ ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+ //1080i-50hz\r
+ {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+ 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
+ 0x02/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+ //576i-50hz\r
+ {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
+ 0x3f/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x45/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
+ 0x40/*ACT_LINE_LOW*/,0x02 /*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x13/*V_BP_LINE*/,\r
+ 0x02/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
+ \r
+ //1080p-50hz\r
+ {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+ 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
+ 0x04/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+};\r
+//#endif\r
+int anx7150_mass_read_need_delay = 0;\r
+\r
+u8 g_video_format = 0x00;\r
+u8 g_audio_format = 0x00;\r
+\r
+\r
+u8 timer_slot = 0;\r
+u8 *ANX7150_EDID_Buf = NULL;\r
+u8 ANX7150_avi_data[19];//, ANX7150_avi_checksum;\r
+u8 ANX7150_system_state = HDMI_INITIAL;\r
+u8 spdif_error_cnt = 0x00;\r
+u8 misc_reset_needed;\r
+u8 ANX7150_stdaddr,ANX7150_stdreg,ANX7150_ext_block_num;\r
+u8 ANX7150_svd_length,ANX7150_sau_length;\r
+u8 ANX7150_edid_dtd[18];\r
+u32 ANX7150_edid_length;\r
+ANX7150_edid_result_4_system ANX7150_edid_result;\r
+\r
+u8 ANX7150_ddc_fifo_full;\r
+u8 ANX7150_ddc_progress;\r
+u8 ANX7150_hdcp_auth_en;\r
+//u8 ANX7150_bksv_ready; //replace by srm_checked xy 01.09\r
+u8 ANX7150_HDCP_enable;\r
+u8 ANX7150_ksv_srm_pass;\r
+u8 ANX7150_hdcp_bcaps;\r
+u8 ANX7150_hdcp_bstatus[2];\r
+u8 ANX7150_srm_checked;\r
+u8 ANX7150_hdcp_auth_pass;\r
+u8 ANX7150_avmute_enable;\r
+u8 ANX7150_send_blue_screen;\r
+u8 ANX7150_hdcp_encryption;\r
+u8 ANX7150_hdcp_init_done;\r
+u8 ANX7150_hdcp_wait_100ms_needed;\r
+u8 ANX7150_auth_fully_pass;\r
+u8 ANX7150_parse_edid_done;//060714 XY\r
+//u8 testen;\r
+//u8 ANX7150_avi_data[19], ANX7150_avi_checksum;\r
+u8 ANX7150_hdcp_auth_fail_counter ;\r
+\r
+u8 ANX7150_video_format_config;\r
+u8 ANX7150_emb_sync_mode,ANX7150_de_gen_en,ANX7150_demux_yc_en,ANX7150_ddr_bus_mode;\r
+u8 ANX7150_ddr_edge,ANX7150_ycmux_u8_sel;\r
+u8 ANX7150_system_config_done;\r
+u8 ANX7150_RGBorYCbCr; //modified by zy 060814\r
+u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
+u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
+u8 ANX7150_video_timing_id;\r
+u8 ANX7150_pix_rpt_set_by_sys;\r
+u8 ANX7150_video_timing_parameter[18];\r
+u8 switch_value_sw_backup,switch_value_pc_backup;\r
+u8 switch_value,bist_switch_value_pc;\r
+u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
+u8 ANX7150_INT_Done;\r
+\r
+audio_config_struct s_ANX7150_audio_config;\r
+config_packets s_ANX7150_packet_config;\r
+\r
+u8 FREQ_MCLK; //0X72:0X50 u82:0\r
+//000b:Fm = 128*Fs\r
+//001b:Fm = 256*Fs\r
+//010b:Fm = 384*Fs\r
+//011b:Fm = 512*Fs\r
+u8 ANX7150_audio_clock_edge;\r
+int ANX7150_DDC_Mass_Read(struct i2c_client *client, u8 *buf, u16 len);\r
+\r
+int anx7150_detect_device(struct anx7150_pdata *anx)\r
+{\r
+ int i, rc = 0; \r
+ char d1, d2;\r
+ \r
+ for (i=0; i<10; i++) \r
+ { \r
+ if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDL_REG, &d1)) < 0) \r
+ continue;\r
+ if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDH_REG, &d2)) < 0) \r
+ continue;\r
+ if (d1 == 0x50 && d2 == 0x71)\r
+ { \r
+ hdmi_dbg(&anx->client->dev, "anx7150 detected!\n");\r
+ return 0;\r
+ } \r
+ } \r
+ \r
+ hdmi_dbg(&anx->client->dev, "anx7150 not detected");\r
+ return -1;\r
+}\r
+u8 ANX7150_Get_System_State(void)\r
+{\r
+ return ANX7150_system_state;\r
+}\r
+void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state)\r
+{\r
+ ANX7150_system_state = new_state;\r
+ switch (ANX7150_system_state)\r
+ {\r
+ case HDMI_INITIAL:\r
+ hdmi_dbg(&client->dev, "INITIAL\n");\r
+ break;\r
+ case WAIT_HOTPLUG:\r
+ hdmi_dbg(&client->dev, "WAIT_HOTPLUG\n");\r
+ break;\r
+ case READ_PARSE_EDID:\r
+ hdmi_dbg(&client->dev, "READ_PARSE_EDID\n");\r
+ break;\r
+ case WAIT_RX_SENSE:\r
+ hdmi_dbg(&client->dev, "WAIT_RX_SENSE\n");\r
+ break;\r
+ case WAIT_HDMI_ENABLE:\r
+ hdmi_dbg(&client->dev, "WAIT_HDMI_ENABLE\n");\r
+ break;\r
+ case SYSTEM_CONFIG:\r
+ hdmi_dbg(&client->dev, "SYSTEM_CONFIG\n");\r
+ break;\r
+ case CONFIG_VIDEO:\r
+ dev_info(&client->dev, "CONFIG_VIDEO\n");\r
+ break;\r
+ case CONFIG_AUDIO:\r
+ hdmi_dbg(&client->dev, "CONFIG_AUDIO\n");\r
+ break;\r
+ case CONFIG_PACKETS:\r
+ hdmi_dbg(&client->dev, "CONFIG_PACKETS\n");\r
+ break;\r
+ case HDCP_AUTHENTICATION:\r
+ hdmi_dbg(&client->dev, "HDCP_AUTHENTICATION\n");\r
+ break;\r
+ ////////////////////////////////////////////////\r
+ // System ANX7150_RESET_LINK is kept for RX clock recovery error case, not used in normal case.\r
+ case RESET_LINK:\r
+ hdmi_dbg(&client->dev, "RESET_LINK\n");\r
+ break;\r
+ ////////////////////////////////////////////////\r
+ case PLAY_BACK:\r
+ dev_info(&client->dev, "PLAY_BACK\n");\r
+ break;\r
+ default:\r
+ hdmi_dbg(&client->dev, "unknown state\n");\r
+ break;\r
+ }\r
+}\r
+\r
+int anx7150_get_hpd(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char sys_ctl3, intr_state, sys_state, hpd_state;\r
+ \r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &sys_ctl3)) < 0)\r
+ return rc;\r
+ if(sys_ctl3 & ANX7150_SYS_CTRL3_PWON_ALL)\r
+ {\r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &sys_state)) < 0)\r
+ return rc;\r
+ hpd_state = (sys_state & ANX7150_SYS_STATE_HP)? 1:0;\r
+ }\r
+ else\r
+ {\r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR_STATE_REG, &intr_state)) < 0)\r
+ return rc;\r
+ hpd_state = (intr_state)? 1:0;\r
+ }\r
+ return hpd_state;\r
+}\r
+static int anx7150_get_interrupt_status(struct i2c_client *client, struct anx7150_interrupt_s *interrupt_staus)\r
+{\r
+ int rc = 0;\r
+ u8 int_s1;\r
+ u8 int_s2;\r
+ u8 int_s3;\r
+ \r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//jack wen, for spdif input from SD0.\r
+ rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//power down all, 090630\r
+ rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//jack wen, for spdif input from SD0.\r
+ rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//power down all, 090630\r
+ rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//jack wen, for spdif input from SD0.\r
+ rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//power down all, 090630\r
+\r
+ interrupt_staus->hotplug_change = (int_s1 & ANX7150_INTR1_STATUS_HP_CHG) ? 1 : 0;\r
+ interrupt_staus->video_format_change = (int_s3 & ANX7150_INTR3_STATUS_VIDF_CHG) ? 1 : 0;\r
+ interrupt_staus->auth_done = (int_s2 & ANX7150_INTR2_STATUS_AUTH_DONE) ? 1 : 0;\r
+ interrupt_staus->auth_state_change = (int_s2 & ANX7150_INTR2_STATUS_AUTH_CHG) ? 1 : 0;\r
+ interrupt_staus->pll_lock_change = (int_s2 & ANX7150_INTR2_STATUS_PLLLOCK_CHG) ? 1 : 0;\r
+ interrupt_staus->rx_sense_change = (int_s3 & ANX7150_INTR3_STATUS_RXSEN_CHG) ? 1 : 0;\r
+ interrupt_staus->HDCP_link_change = (int_s2 & ANX7150_INTR2_STATUS_HDCPLINK_CHK) ? 1 : 0;\r
+ interrupt_staus->audio_clk_change = (int_s3 & ANX7150_INTR3_STATUS_AUDCLK_CHG) ? 1 : 0;\r
+ interrupt_staus->audio_FIFO_overrun = (int_s1 & ANX7150_INTR1_STATUS_AFIFO_OVER) ? 1 : 0;\r
+ interrupt_staus->SPDIF_error = (int_s1 & ANX7150_INTR1_STATUS_SPDIF_ERR) ? 1 : 0;\r
+ interrupt_staus->SPDIF_bi_phase_error = ((int_s3 & ANX7150_INTR3_STATUS_SPDIFBI_ERR) ? 1 : 0) \r
+ || ((int_s3 & ANX7150_INTR3_STATUS_SPDIF_UNSTBL) ? 1 : 0);\r
+ return 0;\r
+}\r
+static void ANX7150_Variable_Initial(void)\r
+{\r
+ u8 i;\r
+\r
+ ANX7150_hdcp_auth_en = 0;\r
+ ANX7150_ksv_srm_pass =0;\r
+ ANX7150_srm_checked = 0;\r
+ ANX7150_hdcp_auth_pass = 0;\r
+ ANX7150_avmute_enable = 1;\r
+ ANX7150_hdcp_auth_fail_counter =0;\r
+ ANX7150_hdcp_encryption = 0;\r
+ ANX7150_send_blue_screen = 0;\r
+ ANX7150_hdcp_init_done = 0;\r
+ ANX7150_hdcp_wait_100ms_needed = 1;\r
+ ANX7150_auth_fully_pass = 0;\r
+ timer_slot = 0;\r
+ //********************for video config**************\r
+ ANX7150_video_timing_id = 0;\r
+ ANX7150_in_pix_rpt = 0;\r
+ ANX7150_tx_pix_rpt = 0;\r
+ ANX7150_new_csc = 0;\r
+ ANX7150_new_vid_id = 0;\r
+ ANX7150_new_HW_interface = 0;\r
+ //********************end of video config*********\r
+\r
+ //********************for edid parse***********\r
+ ANX7150_edid_result.is_HDMI = 1;\r
+ ANX7150_edid_result.ycbcr422_supported = 0;\r
+ ANX7150_edid_result.ycbcr444_supported = 0;\r
+ ANX7150_edid_result.supported_720p_60Hz = 0;\r
+ ANX7150_edid_result.supported_720p_50Hz = 0;\r
+ ANX7150_edid_result.supported_576p_50Hz = 0;\r
+ ANX7150_edid_result.supported_576i_50Hz = 0;\r
+ ANX7150_edid_result.supported_1080i_60Hz = 0;\r
+ ANX7150_edid_result.supported_1080i_50Hz = 0;\r
+ ANX7150_edid_result.supported_640x480p_60Hz = 0;\r
+ ANX7150_edid_result.supported_720x480p_60Hz = 0;\r
+ ANX7150_edid_result.supported_720x480i_60Hz = 0;\r
+ ANX7150_edid_result.edid_errcode = 0;\r
+ ANX7150_edid_result.SpeakerFormat = 0;\r
+ for (i = 0; i < 8; i ++)\r
+ {\r
+ ANX7150_edid_result.AudioChannel[i] = 0;\r
+ ANX7150_edid_result.AudioFormat[i] = 0;\r
+ ANX7150_edid_result.AudioFs[i] = 0;\r
+ ANX7150_edid_result.AudioLength[i] = 0;\r
+ }\r
+ //********************end of edid**************\r
+\r
+ s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe\r
+ s_ANX7150_packet_config.avi_info.type = 0x82;\r
+ s_ANX7150_packet_config.avi_info.version = 0x02;\r
+ s_ANX7150_packet_config.avi_info.length = 0x0d;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[1] = 0x21;//YCbCr422\r
+ s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x08;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[3] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[4] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[5] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[6] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[7] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[8] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[9] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[10] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[11] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[12] = 0x00;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[13] = 0x00;\r
+\r
+ // audio infoframe\r
+ s_ANX7150_packet_config.audio_info.type = 0x84;\r
+ s_ANX7150_packet_config.audio_info.version = 0x01;\r
+ s_ANX7150_packet_config.audio_info.length = 0x0a;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[1] = 0x00; //zy 061123 for ATC\r
+ s_ANX7150_packet_config.audio_info.pb_u8[2] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[3] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[4] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[5] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[6] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[7] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[8] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[9] = 0x00;\r
+ s_ANX7150_packet_config.audio_info.pb_u8[10] = 0x00;\r
+\r
+ ANX7150_INT_Done = 0;\r
+}\r
+static void ANX7150_HW_Interface_Variable_Initial(void)\r
+{\r
+ u8 c;\r
+\r
+ ANX7150_video_format_config = 0x00;\r
+ ANX7150_RGBorYCbCr = 0x00;\r
+ ANX7150_ddr_edge = ANX7150_IDCK_EDGE_DDR;\r
+\r
+ c = 0;\r
+ c = (ANX7150_I2S_CH0_ENABLE << 2) | (ANX7150_I2S_CH1_ENABLE << 3) |\r
+ (ANX7150_I2S_CH2_ENABLE << 4) | (ANX7150_I2S_CH3_ENABLE << 5);\r
+ s_ANX7150_audio_config.audio_type = ANX7150_AUD_HW_INTERFACE; // input I2S\r
+ s_ANX7150_audio_config.down_sample = 0x00;\r
+ s_ANX7150_audio_config.i2s_config.audio_channel = c;//0x04;\r
+ s_ANX7150_audio_config.i2s_config.Channel_status1 =0x00;\r
+ s_ANX7150_audio_config.i2s_config.Channel_status1 = 0x00;\r
+ s_ANX7150_audio_config.i2s_config.Channel_status2 = 0x00;\r
+ s_ANX7150_audio_config.i2s_config.Channel_status3 = 0x00;\r
+ s_ANX7150_audio_config.i2s_config.Channel_status4 = 0x00;//0x02;//48k\r
+ s_ANX7150_audio_config.i2s_config.Channel_status5 = ANX7150_I2S_WORD_LENGTH;//0x0b;\r
+ s_ANX7150_audio_config.audio_layout = 0x00;\r
+\r
+ c = (ANX7150_I2S_SHIFT_CTRL << 3) | (ANX7150_I2S_DIR_CTRL << 2) |\r
+ (ANX7150_I2S_WS_POL << 1) | ANX7150_I2S_JUST_CTRL;\r
+ s_ANX7150_audio_config.i2s_config.i2s_format = c;//0x00;\r
+\r
+ FREQ_MCLK = ANX7150_MCLK_Fs_RELATION;//set the relation of MCLK and WS\r
+ ANX7150_audio_clock_edge = ANX7150_AUD_CLK_EDGE;\r
+\r
+\r
+}\r
+static int anx7150_hardware_initial(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c = 0;\r
+ \r
+ //clear HDCP_HPD_RST\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+ c |= (0x01);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+\r
+ mdelay(10);\r
+\r
+ c &= (~0x01);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+ \r
+ //Power on I2C\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
+ c |= (ANX7150_SYS_CTRL3_I2C_PWON);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+ c= 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
+\r
+ //clear HDCP_HPD_RST\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c &= (0xbf);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+\r
+ //Power on Audio capture and Video capture module clock\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
+ c |= (0x06);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
+\r
+ //Enable auto set clock range for video PLL\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
+ c &= (0x00);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
+\r
+ //Set registers value of Blue Screen when HDCP authentication failed--RGB mode,green field\r
+ c = 0x10;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
+ c = 0xeb;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
+ c = 0x10;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
+\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, (c | 0x80));\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
+ c |= (0x08);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_TX_AMP, &c);//jack wen\r
+ c |= (0x01);\r
+\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_TX_AMP, &c); //TMDS swing\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL1_REG, &c); //Added for PLL unlock issue in high temperature - Feiw\r
+ //if (ANX7150_AUD_HW_INTERFACE == 0x02) //jack wen, spdif\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);//jack wen, for spdif input from SD0.\r
+ c &= (0xef);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
+\r
+ c = 0xc7;\r
+ rc = anx7150_i2c_write_p0_reg(client, 0xE1, &c);\r
+\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);//power down HDCP, 090630\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//jack wen, for spdif input from SD0.\r
+ c &= (0xfe);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power down all, 090630\r
+\r
+ return rc;\r
+}\r
+\r
+int anx7150_rst_ddcchannel(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ //Reset the DDC channel\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+\r
+ c |= (ANX7150_SYS_CTRL2_DDC_RST);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+\r
+ c &= (~ANX7150_SYS_CTRL2_DDC_RST);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//abort current operation\r
+\r
+ c = 0x06;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
+\r
+ //Clear FIFO\r
+ c = 0x05;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
+\r
+ return rc;\r
+}\r
+\r
+int anx7150_initial(struct i2c_client *client)
+{
+ ANX7150_Variable_Initial(); //simon\r
+ ANX7150_HW_Interface_Variable_Initial(); //simon\r
+ \r
+ anx7150_hardware_initial(client); //simon\r
+ return 0;
+}
+int anx7150_unplug(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ dev_info(&client->dev, "anx7150 unplug\n");\r
+ \r
+ //wen HDCP CTS\r
+ ANX7150_Variable_Initial(); //simon\r
+ ANX7150_HW_Interface_Variable_Initial(); //simon\r
+ \r
+ rc = anx7150_hardware_initial(client); //simon\r
+ if(rc < 0)\r
+ dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //simon\r
+ if(rc < 0)\r
+ dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
+ //wen HDCP CTS\r
+ ANX7150_hdcp_wait_100ms_needed = 1;\r
+ ANX7150_auth_fully_pass = 0;\r
+\r
+ // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
+ ANX7150_parse_edid_done = 0;\r
+// ANX7150_system_config_done = 0;\r
+ ANX7150_srm_checked = 0;\r
+\r
+ return rc;\r
+}\r
+int anx7150_plug(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ dev_info(&client->dev, "anx7150 plug\n");\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
+ c |= (0x01);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power up all, 090630\r
+\r
+ //disable audio & video & hdcp & TMDS and init begin\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c &= (~ANX7150_VID_CTRL_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+ c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+\r
+ ANX7150_Variable_Initial();\r
+ //disable video & audio & hdcp & TMDS and init end\r
+\r
+ \r
+ //Power on chip and select DVI mode\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c |= (0x05);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);// cwz change 0x01 -> 0x05\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c &= (0xfd);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+\r
+ //D("ANX7150 is set to DVI mode\n");\r
+ rc = anx7150_rst_ddcchannel(client);\r
+ //Initial Interrupt\r
+ // disable video/audio CLK,Format change and before config video. 060713 xy\r
+\r
+ c = 0x04;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
+\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR_CTRL_REG, &c);\r
+\r
+ // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
+ ANX7150_parse_edid_done = 0;\r
+// ANX7150_system_config_done = 0;\r
+ ANX7150_srm_checked = 0;\r
+\r
+ return rc;\r
+}\r
+\r
+int anx7150_set_avmute(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ c = 0x01;\r
+ if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
+ return rc;\r
+ \r
+ if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ c |= (0x0c);\r
+ if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ ANX7150_avmute_enable = 1;\r
+\r
+ return rc;\r
+}\r
+int anx7150_clear_avmute(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ c = 0x02;\r
+ if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
+ return rc;\r
+ \r
+ if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ c |= (0x0c);\r
+ if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ ANX7150_avmute_enable = 0;\r
+// D("@@@@@@@@@@@@@@@@@@@@ANX7150_Clear_AVMute\n");\r
+ return rc;\r
+\r
+}\r
+\r
+static int anx7150_video_format_change(struct i2c_client *client)\r
+{\r
+ int rc;\r
+ char c;\r
+ \r
+ hdmi_dbg(&client->dev, "after video format change int \n");\r
+ \r
+ rc = anx7150_set_avmute(client);//wen\r
+ //stop HDCP and reset DDC\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ \r
+ rc = anx7150_rst_ddcchannel(client);\r
+ \r
+ //when format change, clear this reg to avoid error in package config\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ //xy 11.06 when format change, need system config again\r
+ // ANX7150_system_config_done = 0;\r
+ return rc;\r
+}\r
+static int anx7150_blue_screen_disable(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ c &= (0xfb);\r
+ if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
+ return rc;\r
+\r
+ ANX7150_send_blue_screen = 0;\r
+ \r
+ return rc;\r
+}\r
+static int anx7150_blue_screen_enable(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ \r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ c |= (ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN);\r
+ if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
+ return rc;\r
+ ANX7150_send_blue_screen = 1;\r
+\r
+ return rc;\r
+}\r
+static int anx7150_hdcp_encryption_enable(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ u8 c;\r
+ \r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
+ return rc;\r
+ c |= (ANX7150_HDCP_CTRL0_ENC_EN);\r
+ if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
+ return rc;\r
+ ANX7150_hdcp_encryption = 1;\r
+\r
+ return rc;\r
+}\r
+\r
+static int anx7150_hdcp_encryption_disable(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ u8 c;\r
+ \r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
+ return rc;\r
+ c &= (0xfb);\r
+ if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
+ return rc;\r
+\r
+ ANX7150_hdcp_encryption = 0;\r
+\r
+ return rc;\r
+}\r
+\r
+static int anx7150_auth_done(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ hdmi_dbg(&client->dev, "anx7150 auth done\n");\r
+ \r
+ if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c)) < 0)\r
+ return rc;\r
+ \r
+ if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Done\n");\r
+ anx7150_blue_screen_disable(client);\r
+ ANX7150_hdcp_auth_pass = 1;\r
+ ANX7150_hdcp_auth_fail_counter = 0;\r
+ }\r
+ else\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_Authentication failed\n");\r
+ ANX7150_hdcp_wait_100ms_needed = 1;\r
+ ANX7150_auth_fully_pass = 0;\r
+ ANX7150_hdcp_auth_pass = 0;\r
+ ANX7150_hdcp_auth_fail_counter ++;\r
+ if (ANX7150_hdcp_auth_fail_counter >= ANX7150_HDCP_FAIL_THRESHOLD)\r
+ {\r
+ ANX7150_hdcp_auth_fail_counter = 0;\r
+ //ANX7150_bksv_ready = 0;\r
+ // TODO: Reset link;\r
+ rc = anx7150_blue_screen_enable(client);\r
+ rc = anx7150_hdcp_encryption_disable(client);\r
+ //disable audio\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ }\r
+ }\r
+ return rc;\r
+}\r
+\r
+static int anx7150_clean_hdcp(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ //mute TMDS link\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);//jack wen\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, c & (~ANX7150_TMDS_CLKCH_MUTE));\r
+\r
+ //Disable hardware HDCP\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ \r
+ //Reset HDCP logic\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
+ c |= (ANX7150_SRST_HDCP_RST);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
+ c &= (~ANX7150_SRST_HDCP_RST);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
+\r
+ //Set ReAuth\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c |= (ANX7150_HDCP_CTRL0_RE_AUTH);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= (~ANX7150_HDCP_CTRL0_RE_AUTH);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ ANX7150_hdcp_auth_en = 0;\r
+ //ANX7150_bksv_ready = 0;\r
+ ANX7150_hdcp_auth_pass = 0;\r
+ ANX7150_hdcp_auth_fail_counter =0 ;\r
+ ANX7150_hdcp_encryption = 0;\r
+ ANX7150_send_blue_screen = 0;\r
+ ANX7150_hdcp_init_done = 0;\r
+ ANX7150_hdcp_wait_100ms_needed = 1;\r
+ ANX7150_auth_fully_pass = 0;\r
+ ANX7150_srm_checked = 0;\r
+ rc = anx7150_rst_ddcchannel(client);\r
+\r
+ return rc;\r
+}\r
+static int anx7150_auth_change(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ \r
+ int state = ANX7150_Get_System_State();\r
+ \r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
+ if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
+ {\r
+ ANX7150_hdcp_auth_pass = 1;\r
+ hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Change\n");\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_set_avmute(client); //wen\r
+ hdmi_dbg(&client->dev, "ANX7150_Authentication failed_by_Auth_change\n");\r
+ ANX7150_hdcp_auth_pass = 0;\r
+ ANX7150_hdcp_wait_100ms_needed = 1;\r
+ ANX7150_auth_fully_pass = 0;\r
+ ANX7150_hdcp_init_done=0; //wen HDCP CTS\r
+ ANX7150_hdcp_auth_en=0; //wen HDCP CTS\r
+ rc = anx7150_hdcp_encryption_disable(client);\r
+ if (state == PLAY_BACK)\r
+ {\r
+ ANX7150_auth_fully_pass = 0;\r
+ //disable audio\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ rc = anx7150_clean_hdcp(client); //wen updated for Changhong TV\r
+ }\r
+ }\r
+ return rc;\r
+}\r
+int ANX7150_GET_RECIVER_TYPE(void)\r
+{
+ return ANX7150_edid_result.is_HDMI;
+}\r
+static int anx7150_audio_clk_change(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ hdmi_dbg(&client->dev, "ANX7150: audio clock changed interrupt,disable audio.\n");\r
+ // disable audio\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ //xy 11.06 when format change, need system config again\r
+// ANX7150_system_config_done = 0;\r
+ return rc;\r
+}\r
+\r
+static int anx7150_afifo_overrun(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ hdmi_dbg(&client->dev, "ANX7150: AFIFO overrun interrupt,disable audio.\n");\r
+ // disable audio\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ return rc;\r
+}\r
+static int anx7150_spdif_error(struct i2c_client *client, int cur_state, int SPDIF_bi_phase_err, int SPDIF_error)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ int state = cur_state;\r
+\r
+ if(SPDIF_bi_phase_err || SPDIF_error)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ if( c & ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN) \r
+ {\r
+ \r
+ if ((state == CONFIG_AUDIO \r
+ || state == CONFIG_PACKETS \r
+ || state == HDCP_AUTHENTICATION \r
+ || state == PLAY_BACK ))\r
+ {\r
+ if(SPDIF_bi_phase_err){\r
+ hdmi_dbg(&client->dev, "SPDIF BI Phase or Unstable error.\n");\r
+ spdif_error_cnt += 0x03;\r
+ }\r
+\r
+ if(SPDIF_error){\r
+ hdmi_dbg(&client->dev, "SPDIF Parity error.\n");\r
+ spdif_error_cnt += 0x01;\r
+ }\r
+\r
+ }\r
+\r
+ // adjust spdif phase\r
+ if (spdif_error_cnt >= spdif_error_th)\r
+ {\r
+ char freq_mclk,c1,c2;\r
+ spdif_error_cnt = 0x00;\r
+ hdmi_dbg(&client->dev, "adjust mclk phase!\n");\r
+ \r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
+\r
+ freq_mclk = c2 & 0x07;\r
+ switch (freq_mclk)\r
+ {\r
+ case ANX7150_mclk_128_Fs: //invert 0x50[3]\r
+ hdmi_dbg(&client->dev, "adjust mclk phase when 128*Fs!\n");\r
+ if ( c2 & 0x08 ) c2 &= 0xf7;\r
+ else c2 |= 0x08;\r
+\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
+ break;\r
+\r
+ case ANX7150_mclk_256_Fs:\r
+ case ANX7150_mclk_384_Fs:\r
+ hdmi_dbg(&client->dev, "adjust mclk phase when 256*Fs or 384*Fs!\n");\r
+ if ( c1 & 0x60 ) c1 &= 0x9f;\r
+ else c1 |= 0x20;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
+ break;\r
+\r
+ case ANX7150_mclk_512_Fs:\r
+ hdmi_dbg(&client->dev, "adjust mclk phase when 512*Fs!\n");\r
+ if ( c1 & 0x60 ) c1 &= 0x9f;\r
+ else c1 |= 0x40;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
+ break;\r
+ default:\r
+ break;\r
+\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else{\r
+ if(spdif_error_cnt > 0 && state == PLAY_BACK) spdif_error_cnt --;\r
+ if(spdif_error_cnt > 0 && state < CONFIG_AUDIO) spdif_error_cnt = 0x00;\r
+\r
+ }\r
+\r
+ return rc;\r
+}\r
+static int anx7150_plllock(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ \r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_STATUS_REG, &c);\r
+ if((c&0x01) == 0)\r
+ {\r
+ rc = anx7150_set_avmute(client);//wen\r
+ hdmi_dbg(&client->dev, "ANX7150: PLL unlock interrupt,disable audio.\n");\r
+ // disable audio & video\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c &= (~ANX7150_VID_CTRL_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+\r
+ //when pll change, clear this reg to avoid error in package config\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);//wen\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+\r
+// ANX7150_system_config_done = 0;//jack wen\r
+ }\r
+ return rc;\r
+}\r
+static int anx7150_rx_sense_change(struct i2c_client *client, int cur_state)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ int state = cur_state;\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
+ hdmi_dbg(&client->dev, "ANX7150_Rx_Sense_Interrupt, ANX7150_SYS_STATE_REG = %.2x\n", (unsigned int)c); //wen\r
+\r
+ if ( c & ANX7150_SYS_STATE_RSV_DET)\r
+ {\r
+ //xy 11.06 Power on chip\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c |= (0x01);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+\r
+ s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe wen\r
+ }\r
+ else\r
+ {\r
+ // Rx is not active\r
+ if (state > WAIT_HOTPLUG)\r
+ {\r
+ //stop HDCP and reset DDC when lost Rx sense\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= (~ANX7150_HDCP_CTRL0_REG);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ \r
+ rc = anx7150_rst_ddcchannel(client);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c &= (0xfd);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ \r
+ // mute TMDS link\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+ c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+ }\r
+ //Power down chip\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c &= (0xfe);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ }\r
+ //xy 11.06 when format change, need system config again\r
+// ANX7150_system_config_done = 0;//wen HDCP CTS\r
+\r
+ return rc;\r
+}\r
+int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state)\r
+{\r
+ struct anx7150_interrupt_s interrupt_staus;\r
+\r
+ int state;\r
+ int hot_plug;\r
+ int rc;\r
+\r
+ state = cur_state;\r
+\r
+ hot_plug = anx7150_get_hpd(anx->client);\r
+\r
+ rc = anx7150_get_interrupt_status(anx->client, &interrupt_staus);\r
+ if(rc < 0){\r
+ goto out;\r
+ } \r
+\r
+ if(anx->dev.HPD_status != hot_plug){\r
+ anx->dev.HPD_change_cnt++;\r
+ }\r
+ else{\r
+ anx->dev.HPD_change_cnt = 0;\r
+ }\r
+\r
+ if(anx->dev.HPD_change_cnt > 1){\r
+ hdmi_dbg(&anx->client->dev, "hotplug_change\n");\r
+\r
+ if(hot_plug == HDMI_RECIVER_UNPLUG){\r
+ anx7150_unplug(anx->client);\r
+ state = HDMI_INITIAL;\r
+ anx->dev.reciver_status = HDMI_RECIVER_INACTIVE;\r
+ }\r
+\r
+ anx->dev.HPD_change_cnt = 0;\r
+ anx->dev.HPD_status = hot_plug;\r
+ }\r
+ return state;\r
+ if(state != HDMI_INITIAL && state != WAIT_HOTPLUG){\r
+ if(interrupt_staus.video_format_change){\r
+ if(state > SYSTEM_CONFIG){\r
+ rc = anx7150_video_format_change(anx->client);\r
+ state = CONFIG_VIDEO;\r
+ }\r
+ }\r
+\r
+ if(interrupt_staus.auth_done){\r
+ rc = anx7150_auth_done(anx->client);\r
+ state = CONFIG_AUDIO;\r
+ }\r
+\r
+ if(interrupt_staus.auth_state_change){\r
+ rc = anx7150_auth_change(anx->client);\r
+ if(state == PLAY_BACK){\r
+ state = HDCP_AUTHENTICATION;\r
+ }\r
+ }\r
+\r
+ if(ANX7150_GET_RECIVER_TYPE() == 1){\r
+ /*\r
+ if(interrupt_staus.audio_clk_change){\r
+ if(state > CONFIG_VIDEO){\r
+ rc = anx7150_audio_clk_change(anx->client);\r
+ state = SYSTEM_CONFIG;\r
+ }\r
+ }\r
+ \r
+ if(interrupt_staus.audio_FIFO_overrun){\r
+ if(state > CONFIG_VIDEO){\r
+ rc = anx7150_afifo_overrun(anx->client);\r
+ state = CONFIG_AUDIO;\r
+ }\r
+ }\r
+\r
+*/\r
+ rc = anx7150_spdif_error(anx->client, state, interrupt_staus.SPDIF_bi_phase_error, interrupt_staus.SPDIF_error);\r
+ }\r
+\r
+ if(interrupt_staus.pll_lock_change){\r
+ if(state > SYSTEM_CONFIG){\r
+ rc = anx7150_plllock(anx->client);\r
+ state = SYSTEM_CONFIG;\r
+ }\r
+ }\r
+\r
+ if(interrupt_staus.rx_sense_change){\r
+ anx7150_rx_sense_change(anx->client, state);\r
+ if(state > WAIT_RX_SENSE) \r
+ state = WAIT_RX_SENSE;\r
+ }\r
+ }\r
+\r
+out:\r
+ return state;\r
+}\r
+\r
+int ANX7150_API_Initial(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ hdmi_dbg(&client->dev, "%s\n", __func__);\r
+\r
+ ANX7150_Variable_Initial();\r
+ ANX7150_HW_Interface_Variable_Initial();\r
+ rc = anx7150_hardware_initial(client);\r
+\r
+ return rc;\r
+}\r
+\r
+void ANX7150_Shutdown(struct i2c_client *client)\r
+{\r
+ hdmi_dbg(&client->dev, "%s\n", __func__);\r
+ ANX7150_API_Initial(client);\r
+ ANX7150_Set_System_State(client, HDMI_INITIAL);\r
+}\r
+\r
+static int anx7150_initddc_read(struct i2c_client *client, \r
+ u8 devaddr, u8 segmentpointer,\r
+ u8 offset, u8 access_num_Low,u8 access_num_high)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ //Write slave device address\r
+ c = devaddr;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_ADDR_REG, &c);\r
+ // Write segment address\r
+ c = segmentpointer;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_SEGADDR_REG, &c);\r
+ //Write offset\r
+ c = offset;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_OFFADDR_REG, &c);\r
+ //Write number for access\r
+ c = access_num_Low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM0_REG, &c);\r
+ c = access_num_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM1_REG, &c);\r
+ //Clear FIFO\r
+ c = 0x05;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
+ //EDDC sequential Read\r
+ c = 0x04;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
+\r
+ return rc;\r
+}\r
+static int ANX7150_GetEDIDLength(struct i2c_client *client)\r
+{\r
+ u8 edid_data_length;\r
+ int rc = 0;\r
+\r
+ anx7150_rst_ddcchannel(client);\r
+\r
+ rc = anx7150_initddc_read(client, 0xa0, 0x00, 0x7e, 0x01, 0x00);\r
+\r
+ mdelay(10);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &edid_data_length);\r
+\r
+ ANX7150_edid_length = edid_data_length * 128 + 128;\r
+\r
+ return rc;\r
+\r
+}\r
+/*** DDC fetch and block validation ***/\r
+\r
+static const u8 edid_header[] = {\r
+ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00\r
+};\r
+\r
+\r
+/*\r
+ * Sanity check the EDID block (base or extension). Return 0 if the block\r
+ * doesn't check out, or 1 if it's valid.\r
+ */\r
+ \r
+int anx7150_edid_block_valid(struct i2c_client *client, u8 *raw_edid)\r
+{\r
+ int i;\r
+ u8 csum = 0;\r
+ struct edid *edid = (struct edid *)raw_edid;\r
+\r
+ if (raw_edid[0] == 0x00) {\r
+ int score = 0;\r
+\r
+ for (i = 0; i < sizeof(edid_header); i++)\r
+ if (raw_edid[i] == edid_header[i])\r
+ score++;\r
+\r
+ if (score == 8) ;\r
+ else if (score >= 6) {\r
+ hdmi_dbg(&client->dev, "Fixing EDID header, your hardware may be failing\n");\r
+ memcpy(raw_edid, edid_header, sizeof(edid_header));\r
+ } else {\r
+ goto bad;\r
+ }\r
+ }\r
+\r
+#if 0\r
+ for (i = 0; i < EDID_LENGTH; i++)\r
+ csum += raw_edid[i];\r
+ if (csum) {\r
+ hdmi_dbg(&client->dev, "EDID checksum is invalid, remainder is %d\n", csum);\r
+\r
+ /* allow CEA to slide through, switches mangle this */\r
+ if (raw_edid[0] != 0x02)\r
+ goto bad;\r
+ }\r
+#endif\r
+\r
+ /* per-block-type checks */\r
+ switch (raw_edid[0]) {\r
+ case 0: /* base */\r
+ if (edid->version != 1) {\r
+ dev_err(&client->dev, "EDID has major version %d, instead of 1\n", edid->version);\r
+ goto bad;\r
+ }\r
+\r
+ if (edid->revision > 4)\r
+ dev_err(&client->dev,"EDID minor > 4, assuming backward compatibility\n");\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return 1;\r
+\r
+bad:\r
+ if (raw_edid) {\r
+ dev_err(&client->dev, "Raw EDID:\n");\r
+ print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);\r
+ printk("\n");\r
+ }\r
+ return 0;\r
+}\r
+int ANX7150_DDC_EDID(struct i2c_client *client, u8 *buf, u8 block, u16 len)\r
+{\r
+ u8 offset;\r
+ u8 segment;\r
+ u8 len_low;\r
+ u8 len_high;\r
+ \r
+ offset = EDID_LENGTH * (block & 0x01);\r
+ segment = block >> 1;\r
+ len_low = len & 0xFF;\r
+ len_high = (len >> 8) & 0xFF;\r
+\r
+ anx7150_initddc_read(client, 0xa0, segment, offset, len_low, len_high);\r
+ if(ANX7150_DDC_Mass_Read(client, buf, len) == len)\r
+ return 0;\r
+ else\r
+ return -1;\r
+}\r
+u8 *ANX7150_Read_EDID(struct i2c_client *client)\r
+{\r
+ u8 *block = NULL;\r
+ u8 *raw_edid = NULL;\r
+ u8 extend_block_num;\r
+ int i = 0;\r
+ int j = 0;\r
+\r
+ anx7150_rst_ddcchannel(client);\r
+\r
+ if ((block = (u8 *)kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)\r
+ return NULL;\r
+\r
+ /* base block fetch */\r
+ hdmi_dbg(&client->dev, "Read base block\n");\r
+ for (i = 0; i < 4; i++) {\r
+ if(ANX7150_DDC_EDID(client, block, 0, EDID_LENGTH))\r
+ goto out;\r
+ if(anx7150_edid_block_valid(client, block))\r
+ break;\r
+ else\r
+ dev_err(&client->dev, "Read base block err, retry...\n");\r
+ \r
+ mdelay(10);\r
+ }\r
+\r
+ if(i == 4){\r
+ dev_err(&client->dev, "Read base block failed\n");\r
+ goto out;\r
+ }\r
+\r
+ /* if there's no extensions, we're done */\r
+ extend_block_num = block[0x7e];\r
+ if(extend_block_num == 0)\r
+ goto out;\r
+ \r
+ dev_err(&client->dev, "extend_block_num = %d\n", extend_block_num);\r
+\r
+ raw_edid = krealloc(block, (extend_block_num + 1) * EDID_LENGTH, GFP_KERNEL);\r
+ if(!raw_edid)\r
+ goto out;\r
+\r
+ block = raw_edid;\r
+\r
+ hdmi_dbg(&client->dev, "Read extend block\n");\r
+ for(j=1; j<=extend_block_num; j++){\r
+ for(i=0; i<4; i++){\r
+ if(ANX7150_DDC_EDID(client, raw_edid + j * EDID_LENGTH, j, EDID_LENGTH))\r
+ goto out;\r
+ if(anx7150_edid_block_valid(client, raw_edid + j * EDID_LENGTH))\r
+ break;\r
+ else\r
+ dev_err(&client->dev, "Read extend block %d err, retry...\n", j);\r
+\r
+ mdelay(10);\r
+ }\r
+\r
+ if(i == 4){\r
+ dev_err(&client->dev, "Read extend block %d failed\n", j);\r
+ goto out;\r
+ }\r
+ }\r
+\r
+ dev_err(&client->dev, "\n\nRaw EDID(extend_block_num = %d, total_len = %d):\n\n", extend_block_num, EDID_LENGTH*(extend_block_num+1));\r
+ print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH*(extend_block_num+1));\r
+ printk("\n\n");\r
+\r
+ return raw_edid;\r
+\r
+out:\r
+ kfree(block);\r
+ return NULL;\r
+}\r
+int ANX7150_DDC_Mass_Read(struct i2c_client *client, u8 *buf, u16 len)\r
+{\r
+ int rc = 0;\r
+ u32 i, j;\r
+ char c, c1,ddc_empty_cnt;\r
+\r
+ i = len;\r
+ while (i > 0)\r
+ {\r
+ //check DDC FIFO statue\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
+ if (c & ANX7150_DDC_CHSTATUS_DDC_OCCUPY)\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150 DDC channel is accessed by an external device, break!.\n");\r
+ break;\r
+ }\r
+ if (c & ANX7150_DDC_CHSTATUS_FIFO_FULL)\r
+ ANX7150_ddc_fifo_full = 1;\r
+ else\r
+ ANX7150_ddc_fifo_full = 0;\r
+ if (c & ANX7150_DDC_CHSTATUS_INPRO)\r
+ ANX7150_ddc_progress = 1;\r
+ else\r
+ ANX7150_ddc_progress = 0;\r
+ if (ANX7150_ddc_fifo_full)\r
+ {\r
+ hdmi_dbg(&client->dev, "DDC FIFO is full during edid reading");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
+ hdmi_dbg(&client->dev, "FIFO counter is %.2x\n", (u32) c);\r
+ for (j=0; j<c; j++)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
+ buf[len - i + j] = c1;\r
+\r
+ ANX7150_ddc_fifo_full = 0;\r
+ if(anx7150_mass_read_need_delay)\r
+ mdelay(1);\r
+ }\r
+ i = i - c;\r
+ //D("\n");\r
+ }\r
+ else if (!ANX7150_ddc_progress)\r
+ {\r
+ //D("ANX7150 DDC FIFO access finished.\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
+ //D("FIFO counter is %.2x\n", (u32) c);\r
+ if (!c)\r
+ {\r
+ i =0;\r
+ break;\r
+ }\r
+ for (j=0; j<c; j++)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
+ buf[len - i + j] = c1;\r
+ }\r
+ i = i - c;\r
+ //D("\ni=%d\n", i);\r
+ }\r
+ else\r
+ {\r
+ ddc_empty_cnt = 0x00;\r
+ for (c1=0; c1<0x0a; c1++)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
+ //D("DDC FIFO access is progressing.\n");\r
+ //D("DDC Channel status is 0x%.2x\n",(u32)c);\r
+ if (c & ANX7150_DDC_CHSTATUS_FIFO_EMPT)\r
+ ddc_empty_cnt++;\r
+ mdelay(1);\r
+ //D("ddc_empty_cnt = 0x%.2x\n",(u32)ddc_empty_cnt);\r
+ }\r
+ if (ddc_empty_cnt >= 0x0a)\r
+ break;\r
+ }\r
+ }\r
+ return (len - i);\r
+}\r
+\r
+static u8 ANX7150_Read_EDID_u8(u8 segmentpointer,u8 offset)\r
+{
+ /*u8 c;
+ anx7150_initddc_read(0xa0, segmentpointer, offset, 0x01, 0x00);\r
+ ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFOCNT_REG, &c);
+ while(c==0)
+ ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFO_ACC_REG, &c);
+ return c;*/
+
+ return ANX7150_EDID_Buf[offset];
+}\r
+static u8 ANX7150_Parse_EDIDHeader(void)\r
+{\r
+ u8 i,temp;\r
+ temp = 0;\r
+ // the EDID header should begin with 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00\r
+ if ((ANX7150_Read_EDID_u8(0, 0) == 0x00) && (ANX7150_Read_EDID_u8(0, 7) == 0x00))\r
+ {\r
+ for (i = 1; i < 7; i++)\r
+ {\r
+ if (ANX7150_Read_EDID_u8(0, i) != 0xff)\r
+ {\r
+ temp = 0x01;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ temp = 0x01;\r
+ }\r
+ if (temp == 0x01)\r
+ {\r
+ return 0;\r
+ }\r
+ else\r
+ {\r
+ return 1;\r
+ }\r
+}\r
+static u8 ANX7150_Parse_EDIDVersion(void)\r
+{\r
+\r
+ if (!((ANX7150_Read_EDID_u8(0, 0x12) == 1) && (ANX7150_Read_EDID_u8(0, 0x13) >= 3) ))\r
+ {\r
+ return 0;\r
+ }\r
+ else\r
+ {\r
+ return 1;\r
+ }\r
+}\r
+static void ANX7150_Parse_DTD(void)\r
+{
+ u32 temp;
+ unsigned long temp1,temp2;
+ u32 Hresolution,Vresolution,Hblanking,Vblanking;
+ u32 PixelCLK,Vtotal,H_image_size,V_image_size;
+ u8 Hz;
+ //float Ratio;
+
+ temp = ANX7150_edid_dtd[1];
+ temp = temp << 8;
+ PixelCLK = temp + ANX7150_edid_dtd[0];
+ // D("Pixel clock is 10000 * %u\n", temp);
+
+ temp = ANX7150_edid_dtd[4];
+ temp = (temp << 4) & 0x0f00;
+ Hresolution = temp + ANX7150_edid_dtd[2];
+ //D("Horizontal Active is %u\n", Hresolution);
+
+ temp = ANX7150_edid_dtd[4];
+ temp = (temp << 8) & 0x0f00;
+ Hblanking = temp + ANX7150_edid_dtd[3];
+ //D("Horizontal Blanking is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[7];
+ temp = (temp << 4) & 0x0f00;
+ Vresolution = temp + ANX7150_edid_dtd[5];
+ //D("Vertical Active is %u\n", Vresolution);
+
+ temp = ANX7150_edid_dtd[7];
+ temp = (temp << 8) & 0x0f00;
+ Vblanking = temp + ANX7150_edid_dtd[6];
+ //D("Vertical Blanking is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[11];
+ temp = (temp << 2) & 0x0300;
+ temp = temp + ANX7150_edid_dtd[8];
+ //D("Horizontal Sync Offset is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[11];
+ temp = (temp << 4) & 0x0300;
+ temp = temp + ANX7150_edid_dtd[9];
+ //D("Horizontal Sync Pulse is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[11];
+ temp = (temp << 2) & 0x0030;
+ temp = temp + (ANX7150_edid_dtd[10] >> 4);
+ //D("Vertical Sync Offset is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[11];
+ temp = (temp << 4) & 0x0030;
+ temp = temp + (ANX7150_edid_dtd[8] & 0x0f);
+ //D("Vertical Sync Pulse is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[14];
+ temp = (temp << 4) & 0x0f00;
+ H_image_size = temp + ANX7150_edid_dtd[12];
+ //D("Horizontal Image size is %u\n", temp);
+
+ temp = ANX7150_edid_dtd[14];
+ temp = (temp << 8) & 0x0f00;
+ V_image_size = temp + ANX7150_edid_dtd[13];
+ //D("Vertical Image size is %u\n", temp);
+
+ //D("Horizontal Border is %bu\n", ANX7150_edid_dtd[15]);
+
+ //D("Vertical Border is %bu\n", ANX7150_edid_dtd[16]);
+
+ temp1 = Hresolution + Hblanking;
+ Vtotal = Vresolution + Vblanking;
+ temp1 = temp1 * Vtotal;
+ temp2 = PixelCLK;
+ temp2 = temp2 * 10000;
+ if (temp1 == 0) //update
+ Hz=0;
+ else
+ Hz = temp2 / temp1;
+ //Hz = temp2 / temp1;
+ if ((Hz == 59) || (Hz == 60))
+ {
+ Hz = 60;
+ //D("_______________Vertical Active is %u\n", Vresolution);
+ if (Vresolution == 540)
+ ANX7150_edid_result.supported_1080i_60Hz = 1;
+ if (Vresolution == 1080)
+ ANX7150_edid_result.supported_1080p_60Hz = 1;
+ if (Vresolution == 720)
+ ANX7150_edid_result.supported_720p_60Hz = 1;
+ if ((Hresolution == 640) && (Vresolution == 480))
+ ANX7150_edid_result.supported_640x480p_60Hz = 1;
+ if ((Hresolution == 720) && (Vresolution == 480))
+ ANX7150_edid_result.supported_720x480p_60Hz = 1;
+ if ((Hresolution == 720) && (Vresolution == 240))
+ ANX7150_edid_result.supported_720x480i_60Hz = 1;
+ }
+ if (Hz == 50)
+ {
+ //D("+++++++++++++++Vertical Active is %u\n", Vresolution);
+ if (Vresolution == 540)
+ ANX7150_edid_result.supported_1080i_50Hz = 1;
+ if (Vresolution == 1080)
+ ANX7150_edid_result.supported_1080p_50Hz = 1;
+ if (Vresolution == 720)
+ ANX7150_edid_result.supported_720p_50Hz = 1;
+ if (Vresolution == 576)
+ ANX7150_edid_result.supported_576p_50Hz = 1;
+ if (Vresolution == 288)
+ ANX7150_edid_result.supported_576i_50Hz = 1;
+ }
+ //D("Fresh rate :% bu Hz\n", Hz);
+ //Ratio = H_image_size;
+ //Ratio = Ratio / V_image_size;
+ //D("Picture ratio : %f \n", Ratio);
+}\r
+static void ANX7150_Parse_DTDinBlockONE(void)\r
+{
+ u8 i;
+ for (i = 0; i < 18; i++)
+ {
+ ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x36));
+ }
+ //D("Parse the first DTD in Block one:\n");
+ ANX7150_Parse_DTD();
+
+ if ((ANX7150_Read_EDID_u8(0, 0x48) == 0)
+ && (ANX7150_Read_EDID_u8(0, 0x49) == 0)
+ && (ANX7150_Read_EDID_u8(0, 0x4a) == 0))
+ {
+ ;//D("the second DTD in Block one is not used to descript video timing.\n");
+ }
+ else
+ {
+ for (i = 0; i < 18; i++)
+ {
+ ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x48));
+ }
+ ANX7150_Parse_DTD();
+ }
+
+ if ((ANX7150_Read_EDID_u8(0,0x5a) == 0)
+ && (ANX7150_Read_EDID_u8(0,0x5b) == 0)
+ && (ANX7150_Read_EDID_u8(0,0x5c) == 0))
+ {
+ ;//D("the third DTD in Block one is not used to descript video timing.\n");
+ }
+ else
+ {
+ for (i = 0; i < 18; i++)
+ {
+ ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x5a));
+ }
+ ANX7150_Parse_DTD();
+ }
+
+ if ((ANX7150_Read_EDID_u8(0,0x6c) == 0)
+ && (ANX7150_Read_EDID_u8(0,0x6d) == 0)
+ && (ANX7150_Read_EDID_u8(0,0x6e) == 0))
+ {
+ ;//D("the fourth DTD in Block one is not used to descript video timing.\n");
+ }
+ else
+ {
+ for (i = 0; i < 18; i++)
+ {
+ ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0,(i + 0x6c));
+ }
+ ANX7150_Parse_DTD();
+ }
+}\r
+static void ANX7150_Parse_NativeFormat(void)\r
+{
+ u8 temp;
+ temp = ANX7150_Read_EDID_u8(0,0x83) & 0xf0;
+ /*if(temp & 0x80)
+ ;//D("DTV supports underscan.\n");
+ if(temp & 0x40)
+ ;//D("DTV supports BasicAudio.\n");*/
+ if (temp & 0x20)
+ {
+ //D("DTV supports YCbCr 4:4:4.\n");
+ ANX7150_edid_result.ycbcr444_supported= 1;
+ }
+ if (temp & 0x10)
+ {
+ //D("DTV supports YCbCr 4:2:2.\n");
+ ANX7150_edid_result.ycbcr422_supported= 1;
+ }
+}\r
+static void ANX7150_Parse_DTDinExtBlock(void)\r
+{
+ u8 i,DTDbeginAddr;
+ DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2, 0x82)
+ + 0x80;
+ while (DTDbeginAddr < (0x6c + 0x80))
+ {
+ if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,DTDbeginAddr) == 0)
+ && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 1)) == 0)
+ && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 2)) == 0))
+ {
+ ;//D("this DTD in Extension Block is not used to descript video timing.\n");
+ }
+ else
+ {
+ for (i = 0; i < 18; i++)
+ {
+ ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(i + DTDbeginAddr));
+ }
+ //D("Parse the DTD in Extension Block :\n");
+ ANX7150_Parse_DTD();
+ }
+ DTDbeginAddr = DTDbeginAddr + 18;
+ }
+}\r
+static void ANX7150_Parse_AudioSTD(void)\r
+{
+ u8 i,AudioFormat,STDReg_tmp,STDAddr_tmp;
+ STDReg_tmp = ANX7150_stdreg & 0x1f;
+ STDAddr_tmp = ANX7150_stdaddr + 1;
+ i = 0;
+ while (i < STDReg_tmp)
+ {
+ AudioFormat = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp ) & 0xF8) >> 3;
+ ANX7150_edid_result.AudioChannel[i/3] = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x07) + 1;
+ ANX7150_edid_result.AudioFormat[i/3] = AudioFormat;
+ ANX7150_edid_result.AudioFs[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 1)) & 0x7f;
+
+ if (AudioFormat == 1)
+ ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) & 0x07;
+ else
+ ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) << 3;
+
+ i = i + 3;
+ STDAddr_tmp = STDAddr_tmp + 3;
+ }
+}\r
+static void ANX7150_Parse_VideoSTD(void)\r
+{
+ u8 i,STDReg_tmp,STDAddr_tmp;
+ u8 SVD_ID[34];
+ STDReg_tmp = ANX7150_stdreg & 0x1f;
+ STDAddr_tmp = ANX7150_stdaddr + 1;
+ i = 0;
+ while (i < STDReg_tmp)
+ {
+ SVD_ID[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x7F;
+ //D("ANX7150_edid_result.SVD_ID[%.2x]=0x%.2x\n",(u32)i,(u32)ANX7150_edid_result.SVD_ID[i]);
+ //if(ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x80)
+ // D(" Native mode");
+ if (SVD_ID[i] == 1)
+ ANX7150_edid_result.supported_640x480p_60Hz = 1;
+ else if (SVD_ID[i] == 4)
+ ANX7150_edid_result.supported_720p_60Hz = 1;
+ else if (SVD_ID[i] == 19)
+ ANX7150_edid_result.supported_720p_50Hz = 1;
+ else if (SVD_ID[i] == 16)
+ ANX7150_edid_result.supported_1080p_60Hz = 1;
+ else if (SVD_ID[i] == 31)
+ ANX7150_edid_result.supported_1080p_50Hz = 1;
+ else if (SVD_ID[i] == 5)
+ ANX7150_edid_result.supported_1080i_60Hz = 1;
+ else if (SVD_ID[i] == 20)
+ ANX7150_edid_result.supported_1080i_50Hz = 1;
+ else if ((SVD_ID[i] == 2) ||(SVD_ID[i] == 3))
+ ANX7150_edid_result.supported_720x480p_60Hz = 1;
+ else if ((SVD_ID[i] == 6) ||(SVD_ID[i] == 7))
+ ANX7150_edid_result.supported_720x480i_60Hz = 1;
+ else if ((SVD_ID[i] == 17) ||(SVD_ID[i] == 18))
+ ANX7150_edid_result.supported_576p_50Hz = 1;
+ else if ((SVD_ID[i] == 21) ||(SVD_ID[i] == 22))
+ ANX7150_edid_result.supported_576i_50Hz = 1;
+
+ i = i + 1;
+ STDAddr_tmp = STDAddr_tmp + 1;
+ }
+}\r
+static void ANX7150_Parse_SpeakerSTD(void)\r
+{
+ ANX7150_edid_result.SpeakerFormat = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) ;
+}\r
+static void ANX7150_Parse_VendorSTD(void)\r
+{\r
+ //u8 c;\r
+ if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) == 0x03)\r
+ && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 2)) == 0x0c)\r
+ && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 3)) == 0x00))\r
+ {\r
+ ANX7150_edid_result.is_HDMI = 1;\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c |ANX7150_SYS_CTRL1_HDMI);\r
+ }\r
+ else\r
+ {\r
+ ANX7150_edid_result.is_HDMI = 0;\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c & (~ANX7150_SYS_CTRL1_HDMI));\r
+ }\r
+}\r
+\r
+static void ANX7150_Parse_STD(void)\r
+{
+ u8 DTDbeginAddr;
+ ANX7150_stdaddr = 0x84;
+ DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,0x82) + 0x80;
+ // D("Video DTDbeginAddr Register :%.2x\n", (u32) DTDbeginAddr);
+ while (ANX7150_stdaddr < DTDbeginAddr)
+ {
+ ANX7150_stdreg = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,ANX7150_stdaddr);
+ switch (ANX7150_stdreg & 0xe0)
+ {
+ case 0x20:
+ ANX7150_Parse_AudioSTD();
+ ANX7150_sau_length = ANX7150_stdreg & 0x1f;
+ break;
+ case 0x40:
+ ANX7150_Parse_VideoSTD();
+ ANX7150_svd_length = ANX7150_stdreg & 0x1f;
+ break;
+ case 0x80:
+ ANX7150_Parse_SpeakerSTD();
+ break;
+ case 0x60:
+ ANX7150_Parse_VendorSTD();
+ break;
+ default:
+ break;
+ }
+ ANX7150_stdaddr = ANX7150_stdaddr + (ANX7150_stdreg & 0x1f) + 0x01;
+ }
+}\r
+static u8 ANX7150_EDID_Checksum(u8 block_number)\r
+{
+ u8 i, real_checksum;
+ u8 edid_block_checksum;
+
+ edid_block_checksum = 0;
+ for (i = 0; i < 127; i ++)
+ {
+ if ((block_number / 2) * 2 == block_number)
+ edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i);
+ else
+ edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i + 0x80);
+ }
+ edid_block_checksum = (~edid_block_checksum) + 1;
+ // D("edid_block_checksum = 0x%.2x\n",(u32)edid_block_checksum);
+ if ((block_number / 2) * 2 == block_number)
+ real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0x7f);
+ else
+ real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0xff);
+ if (real_checksum == edid_block_checksum)
+ return 1;
+ else
+ return 0;
+}\r
+static u8 ANX7150_Parse_ExtBlock(void)\r
+{
+ u8 i,c;
+
+ for (i = 0; i < ANX7150_Read_EDID_u8(0, 0x7e); i++) //read in blocks
+ {
+ c = ANX7150_Read_EDID_u8(i/2, 0x80);
+ if ( c == 0x02)
+ {
+ ANX7150_ext_block_num = i + 1;
+ ANX7150_Parse_DTDinExtBlock();
+ ANX7150_Parse_STD();
+ if (!(ANX7150_EDID_Checksum(ANX7150_ext_block_num)))
+ {
+ ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;
+ return ANX7150_edid_result.edid_errcode;
+ }
+ }
+ else
+ {
+ ANX7150_edid_result.edid_errcode = ANX7150_EDID_ExtBlock_NotFor_861B;
+ return ANX7150_edid_result.edid_errcode;
+ }
+ }
+
+ return 0;
+}\r
+int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev)\r
+{\r
+ int rc = 0, i;\r
+ char c;\r
+\r
+ if(dev->rk29_output_status == RK29_OUTPUT_STATUS_LCD)\r
+ anx7150_mass_read_need_delay = 1;\r
+ else\r
+ anx7150_mass_read_need_delay = 0;\r
+\r
+ /* Clear HDCP Authentication indicator */\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ ANX7150_hdcp_auth_en = 0;\r
+\r
+\r
+ ANX7150_EDID_Buf = ANX7150_Read_EDID(client);\r
+ \r
+ if(!ANX7150_EDID_Buf){\r
+ ANX7150_edid_result.edid_errcode = ANX7150_EDID_BadHeader;\r
+ dev_err(&client->dev, "READ EDID ERROR\n");\r
+ goto err;\r
+ }\r
+\r
+/*\r
+ if(ANX7150_EDID_Checksum(0) == 0)\r
+ {\r
+ D("EDID Block one check sum error, Stop parsing\n");\r
+ ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;\r
+ return ANX7150_edid_result.edid_errcode;\r
+ }\r
+*/\r
+\r
+ //ANX7150_Parse_BasicDis();\r
+ ANX7150_Parse_DTDinBlockONE();\r
+\r
+ if(ANX7150_EDID_Buf[0x7e] == 0)\r
+ {\r
+ hdmi_dbg(&client->dev, "No EDID extension blocks.\n");\r
+ ANX7150_edid_result.edid_errcode = ANX7150_EDID_No_ExtBlock;\r
+ return ANX7150_edid_result.edid_errcode;\r
+ }\r
+ \r
+ ANX7150_Parse_NativeFormat();\r
+ ANX7150_Parse_ExtBlock();\r
+\r
+ if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_ExtBlock_NotFor_861B){\r
+ dev_err(&client->dev,"EDID ExtBlock not support for 861B, Stop parsing\n");\r
+ goto err;\r
+ }\r
+\r
+ if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_CheckSum_ERR){\r
+ dev_err(&client->dev,"EDID Block check sum error, Stop parsing\n");\r
+ goto err;\r
+ }\r
+\r
+ hdmi_dbg(&client->dev,"EDID parsing finished!\n");\r
+\r
+ {\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.edid_errcode = 0x%.2x\n",(u32)ANX7150_edid_result.edid_errcode);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.is_HDMI = 0x%.2x\n",(u32)ANX7150_edid_result.is_HDMI);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr422_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr422_supported);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr444_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr444_supported);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_50Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_50Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_50Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_640x480p_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480p_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480i_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576p_50Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576i_50Hz);\r
+ if (!ANX7150_edid_result.edid_errcode)\r
+ {\r
+ for (i = 0; i < ANX7150_sau_length/3; i++)\r
+ {\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioChannel = 0x%.2x\n",(u32)ANX7150_edid_result.AudioChannel[i]);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFormat = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFormat[i]);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFs = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFs[i]);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioLength = 0x%.2x\n",(u32)ANX7150_edid_result.AudioLength[i]);\r
+ }\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.SpeakerFormat = 0x%.2x\n",(u32)ANX7150_edid_result.SpeakerFormat);\r
+ }\r
+ }\r
+ \r
+ ANX7150_parse_edid_done = 1;\r
+ kfree(ANX7150_EDID_Buf);\r
+ ANX7150_EDID_Buf = NULL;\r
+ return 0;\r
+ \r
+err:\r
+ if(ANX7150_EDID_Buf){\r
+ kfree(ANX7150_EDID_Buf);\r
+ ANX7150_EDID_Buf = NULL;\r
+ }\r
+ return ANX7150_edid_result.edid_errcode;\r
+}\r
+int ANX7150_GET_SENSE_STATE(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+\r
+ hdmi_dbg(&client->dev, "enter\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
+\r
+ return (c & ANX7150_SYS_STATE_RSV_DET) ? 1 : 0;\r
+}\r
+int ANX7150_Get_Optimal_resolution(int resolution_set)\r
+{\r
+ int resolution_real;\r
+ int find_resolution = 0;\r
+\r
+ switch(resolution_set){\r
+ case HDMI_1280x720p_50Hz:\r
+ if(ANX7150_edid_result.supported_720p_50Hz){\r
+ resolution_real = HDMI_1280x720p_50Hz;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_1280x720p_60Hz:\r
+ if(ANX7150_edid_result.supported_720p_60Hz){\r
+ resolution_real = HDMI_1280x720p_60Hz;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_720x576p_50Hz_4x3:\r
+ if(ANX7150_edid_result.supported_576p_50Hz){\r
+ resolution_real = HDMI_720x576p_50Hz_4x3;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_720x576p_50Hz_16x9:\r
+ if(ANX7150_edid_result.supported_576p_50Hz){\r
+ resolution_real = HDMI_720x576p_50Hz_16x9;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_720x480p_60Hz_4x3:\r
+ if(ANX7150_edid_result.supported_720x480p_60Hz){\r
+ resolution_real = HDMI_720x480p_60Hz_4x3;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_720x480p_60Hz_16x9:\r
+ if(ANX7150_edid_result.supported_720x480p_60Hz){\r
+ resolution_real = HDMI_720x480p_60Hz_16x9;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_1920x1080p_50Hz:\r
+ if(ANX7150_edid_result.supported_1080p_50Hz){\r
+ resolution_real = HDMI_1920x1080p_50Hz;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ case HDMI_1920x1080p_60Hz:\r
+ if(ANX7150_edid_result.supported_1080p_60Hz){\r
+ resolution_real = HDMI_1920x1080p_60Hz;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if(find_resolution == 0){\r
+\r
+ if(ANX7150_edid_result.supported_720p_50Hz)\r
+ resolution_real = HDMI_1280x720p_50Hz;\r
+ else if(ANX7150_edid_result.supported_720p_60Hz)\r
+ resolution_real = HDMI_1280x720p_60Hz;\r
+ else if(ANX7150_edid_result.supported_576p_50Hz)\r
+ resolution_real = HDMI_720x576p_50Hz_4x3;\r
+ else if(ANX7150_edid_result.supported_720x480p_60Hz)\r
+ resolution_real = HDMI_720x480p_60Hz_4x3;\r
+ else if(ANX7150_edid_result.supported_1080p_50Hz)\r
+ resolution_real = HDMI_1920x1080p_50Hz;\r
+ else if(ANX7150_edid_result.supported_1080p_60Hz)\r
+ resolution_real = HDMI_1920x1080p_60Hz;\r
+ else\r
+ resolution_real = HDMI_1280x720p_50Hz;\r
+ }\r
+\r
+ return resolution_real;\r
+}\r
+void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF)\r
+{ \r
+ ANX7150_HDCP_enable = HDCP_ONorOFF;// 1: on; 0:off\r
+}\r
+static void ANX7150_API_Video_Config(u8 video_id,u8 input_pixel_rpt_time)\r
+{
+ ANX7150_video_timing_id = video_id;
+ ANX7150_in_pix_rpt = input_pixel_rpt_time;
+}\r
+static void ANX7150_API_Packets_Config(u8 pkt_sel)\r
+{
+ s_ANX7150_packet_config.packets_need_config = pkt_sel;
+}\r
+static void ANX7150_API_AVI_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
+ u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10,u8 pb11,u8 pb12,u8 pb13)
+{
+ s_ANX7150_packet_config.avi_info.pb_u8[1] = pb1;
+ s_ANX7150_packet_config.avi_info.pb_u8[2] = pb2;
+ s_ANX7150_packet_config.avi_info.pb_u8[3] = pb3;
+ s_ANX7150_packet_config.avi_info.pb_u8[4] = pb4;
+ s_ANX7150_packet_config.avi_info.pb_u8[5] = pb5;
+ s_ANX7150_packet_config.avi_info.pb_u8[6] = pb6;
+ s_ANX7150_packet_config.avi_info.pb_u8[7] = pb7;
+ s_ANX7150_packet_config.avi_info.pb_u8[8] = pb8;
+ s_ANX7150_packet_config.avi_info.pb_u8[9] = pb9;
+ s_ANX7150_packet_config.avi_info.pb_u8[10] = pb10;
+ s_ANX7150_packet_config.avi_info.pb_u8[11] = pb11;
+ s_ANX7150_packet_config.avi_info.pb_u8[12] = pb12;
+ s_ANX7150_packet_config.avi_info.pb_u8[13] = pb13;
+}\r
+static void ANX7150_API_AUD_INFO_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
+ u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10)
+{
+ s_ANX7150_packet_config.audio_info.pb_u8[1] = pb1;
+ s_ANX7150_packet_config.audio_info.pb_u8[2] = pb2;
+ s_ANX7150_packet_config.audio_info.pb_u8[3] = pb3;
+ s_ANX7150_packet_config.audio_info.pb_u8[4] = pb4;
+ s_ANX7150_packet_config.audio_info.pb_u8[5] = pb5;
+ s_ANX7150_packet_config.audio_info.pb_u8[6] = pb6;
+ s_ANX7150_packet_config.audio_info.pb_u8[7] = pb7;
+ s_ANX7150_packet_config.audio_info.pb_u8[8] = pb8;
+ s_ANX7150_packet_config.audio_info.pb_u8[9] = pb9;
+ s_ANX7150_packet_config.audio_info.pb_u8[10] = pb10;
+}\r
+static void ANX7150_API_AUD_CHStatus_Config(u8 MODE,u8 PCM_MODE,u8 SW_CPRGT,u8 NON_PCM,\r
+ u8 PROF_APP,u8 CAT_CODE,u8 CH_NUM,u8 SOURCE_NUM,u8 CLK_ACCUR,u8 Fs)
+{
+ //MODE: 0x00 = PCM Audio
+ //PCM_MODE: 0x00 = 2 audio channels without pre-emphasis;
+ //0x01 = 2 audio channels with 50/15 usec pre-emphasis;
+ //SW_CPRGT: 0x00 = copyright is asserted;
+ // 0x01 = copyright is not asserted;
+ //NON_PCM: 0x00 = Represents linear PCM
+ //0x01 = For other purposes
+ //PROF_APP: 0x00 = consumer applications;
+ // 0x01 = professional applications;
+
+ //CAT_CODE: Category code
+ //CH_NUM: 0x00 = Do not take into account
+ // 0x01 = left channel for stereo channel format
+ // 0x02 = right channel for stereo channel format
+ //SOURCE_NUM: source number
+ // 0x00 = Do not take into account
+ // 0x01 = 1; 0x02 = 2; 0x03 = 3
+ //CLK_ACCUR: 0x00 = level II
+ // 0x01 = level I
+ // 0x02 = level III
+ // else reserved;
+
+ s_ANX7150_audio_config.i2s_config.Channel_status1 = (MODE << 7) | (PCM_MODE << 5) |
+ (SW_CPRGT << 2) | (NON_PCM << 1) | PROF_APP;
+ s_ANX7150_audio_config.i2s_config.Channel_status2 = CAT_CODE;
+ s_ANX7150_audio_config.i2s_config.Channel_status3 = (CH_NUM << 7) | SOURCE_NUM;
+ s_ANX7150_audio_config.i2s_config.Channel_status4 = (CLK_ACCUR << 5) | Fs;\r
+}\r
+void ANX7150_API_System_Config(void)\r
+{\r
+ ANX7150_API_Video_Config(g_video_format,input_pixel_clk_1x_repeatition);\r
+ ANX7150_API_Packets_Config(ANX7150_avi_sel | ANX7150_audio_sel);\r
+ if (s_ANX7150_packet_config.packets_need_config & ANX7150_avi_sel)\r
+ ANX7150_API_AVI_Config( 0x00,source_ratio,null,null,null,null,null,null,null,null,null,null,null);\r
+ if (s_ANX7150_packet_config.packets_need_config & ANX7150_audio_sel)\r
+ ANX7150_API_AUD_INFO_Config(null,null,null,null,null,null,null,null,null,null);\r
+ ANX7150_API_AUD_CHStatus_Config(null,null,null,null,null,null,null,null,null,g_audio_format);\r
+\r
+// ANX7150_system_config_done = 1;\r
+}\r
+\r
+static int anx7150_blue_screen_format_config(struct i2c_client *client)\r
+{\r
+ int rc = 0 ;\r
+ char c;\r
+ \r
+ // TODO:Add ITU 601 format.(Now only ITU 709 format added)\r
+ switch (ANX7150_RGBorYCbCr)\r
+ {\r
+ case ANX7150_RGB: //select RGB mode\r
+ c = 0x10;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
+ c = 0xeb;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
+ c = 0x10;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
+ break;\r
+ case ANX7150_YCbCr422: //select YCbCr4:2:2 mode\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
+ c = 0xad;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
+ c = 0x2a;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
+ break;\r
+ case ANX7150_YCbCr444: //select YCbCr4:4:4 mode\r
+ c = 0x1a;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
+ c = 0xad;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
+ c = 0x2a;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ return rc;\r
+}\r
+static void ANX7150_Get_Video_Timing(void)\r
+{\r
+ u8 i;\r
+ \r
+//#ifdef ITU656\r
+ for (i = 0; i < 18; i++)\r
+ {\r
+ switch (ANX7150_video_timing_id)\r
+ {\r
+ case ANX7150_V640x480p_60Hz:\r
+ //D("640x480p_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_640x480p_60Hz[i];\r
+ break;\r
+ case ANX7150_V720x480p_60Hz_4x3:\r
+ case ANX7150_V720x480p_60Hz_16x9:\r
+ //D("720x480p_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480p_60Hz[i];\r
+ break;\r
+ case ANX7150_V1280x720p_60Hz:\r
+ //D("1280x720p_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_60Hz[i];\r
+ break;\r
+ case ANX7150_V1920x1080i_60Hz:\r
+ //D("1920x1080i_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_60Hz[i];\r
+ break;\r
+ case ANX7150_V720x480i_60Hz_4x3:\r
+ case ANX7150_V720x480i_60Hz_16x9:\r
+ //D("720x480i_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480i_60Hz[i];\r
+ break;\r
+ case ANX7150_V720x576p_50Hz_4x3:\r
+ case ANX7150_V720x576p_50Hz_16x9:\r
+ //D("720x576p_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576p_50Hz[i];\r
+ break;\r
+ case ANX7150_V1280x720p_50Hz:\r
+ //D("1280x720p_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_50Hz[i];\r
+ break;\r
+ case ANX7150_V1920x1080i_50Hz:\r
+ //D("1920x1080i_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_50Hz[i];\r
+ break;\r
+ case ANX7150_V720x576i_50Hz_4x3:\r
+ case ANX7150_V720x576i_50Hz_16x9:\r
+ //D("720x576i_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576i_50Hz[i];\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
+ }\r
+ /*#else\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ switch(ANX7150_video_timing_id)\r
+ {\r
+ case ANX7150_V640x480p_60Hz:\r
+ //D("640x480p_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V720x480p_60Hz_4x3:\r
+ case ANX7150_V720x480p_60Hz_16x9:\r
+ //D("720x480p_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 18 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V1280x720p_60Hz:\r
+ //D("1280x720p_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 36 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V1920x1080i_60Hz:\r
+ //D("1920x1080i_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 54 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V720x480i_60Hz_4x3:\r
+ case ANX7150_V720x480i_60Hz_16x9:\r
+ //D("720x480i_60Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 72 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V720x576p_50Hz_4x3:\r
+ case ANX7150_V720x576p_50Hz_16x9:\r
+ //D("720x576p_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 90 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V1280x720p_50Hz:\r
+ //D("1280x720p_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 108 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V1920x1080i_50Hz:\r
+ //D("1920x1080i_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 126 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+ case ANX7150_V720x576i_50Hz_4x3:\r
+ case ANX7150_V720x576i_50Hz_16x9:\r
+ //D("720x576i_50Hz!\n");\r
+ ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 144 + i);\r
+ DRVDelayMs(3);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
+ }\r
+ #endif*/\r
+}\r
+static void ANX7150_Parse_Video_Format(void)\r
+{\r
+ switch (ANX7150_video_format_config)\r
+ {\r
+ case ANX7150_RGB_YCrCb444_SepSync:\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ //D("RGB_YCrCb444_SepSync mode!\n");\r
+ break;\r
+ case ANX7150_YCrCb422_SepSync:\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ //D("YCrCb422_SepSync mode!\n");\r
+ break;\r
+ case ANX7150_YCrCb422_EmbSync:\r
+ //D("YCrCb422_EmbSync mode!\n");\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_emb_sync_mode = 1;\r
+ ANX7150_Get_Video_Timing();\r
+ break;\r
+ case ANX7150_YCMux422_SepSync_Mode1:\r
+ //D("YCMux422_SepSync_Mode1 mode!\n");\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_ycmux_u8_sel = 0;\r
+ ANX7150_demux_yc_en = 1;\r
+ break;\r
+ case ANX7150_YCMux422_SepSync_Mode2:\r
+ //D("YCMux422_SepSync_Mode2 mode!\n");\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_ycmux_u8_sel = 1;\r
+ ANX7150_demux_yc_en = 1;\r
+ break;\r
+ case ANX7150_YCMux422_EmbSync_Mode1:\r
+ //D("YCMux422_EmbSync_Mode1 mode!\n");\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_emb_sync_mode = 1;\r
+ ANX7150_ycmux_u8_sel = 0;\r
+ ANX7150_demux_yc_en = 1;\r
+ ANX7150_Get_Video_Timing();\r
+ break;\r
+ case ANX7150_YCMux422_EmbSync_Mode2:\r
+ //D("YCMux422_EmbSync_Mode2 mode!\n");\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_emb_sync_mode = 1;\r
+ ANX7150_ycmux_u8_sel = 1;\r
+ ANX7150_demux_yc_en = 1;\r
+ ANX7150_Get_Video_Timing();\r
+ break;\r
+ case ANX7150_RGB_YCrCb444_DDR_SepSync:\r
+ //D("RGB_YCrCb444_DDR_SepSync mode!\n");\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_ddr_bus_mode = 1;\r
+ break;\r
+ case ANX7150_RGB_YCrCb444_DDR_EmbSync:\r
+ //D("RGB_YCrCb444_DDR_EmbSync mode!\n");\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_de_gen_en = 0;\r
+ ANX7150_emb_sync_mode = 1;\r
+ ANX7150_ddr_bus_mode = 1;\r
+ ANX7150_Get_Video_Timing();\r
+ break;\r
+ case ANX7150_RGB_YCrCb444_SepSync_No_DE:\r
+ //D("RGB_YCrCb444_SepSync_No_DE mode!\n");\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 1;\r
+ ANX7150_Get_Video_Timing();\r
+ break;\r
+ case ANX7150_YCrCb422_SepSync_No_DE:\r
+ //D("YCrCb422_SepSync_No_DE mode!\n");\r
+ ANX7150_emb_sync_mode = 0;\r
+ ANX7150_demux_yc_en = 0;\r
+ ANX7150_ddr_bus_mode = 0;\r
+ ANX7150_de_gen_en = 1;\r
+ ANX7150_Get_Video_Timing();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+static int anx7150_de_generator(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ u8 video_type,hsync_pol,vsync_pol,v_fp,v_bp,vsync_width;\r
+ u8 hsync_width_low,hsync_width_high,v_active_low,v_active_high;\r
+ u8 h_active_low,h_active_high,h_res_low,h_res_high,h_bp_low,h_bp_high;\r
+ u32 hsync_width,h_active,h_res,h_bp;\r
+\r
+ video_type = ANX7150_video_timing_parameter[15];\r
+ hsync_pol = ANX7150_video_timing_parameter[16];\r
+ vsync_pol = ANX7150_video_timing_parameter[17];\r
+ v_fp = ANX7150_video_timing_parameter[12];\r
+ v_bp = ANX7150_video_timing_parameter[11];\r
+ vsync_width = ANX7150_video_timing_parameter[10];\r
+ hsync_width = ANX7150_video_timing_parameter[5];\r
+ hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
+ v_active_high = ANX7150_video_timing_parameter[9];\r
+ v_active_low = ANX7150_video_timing_parameter[8];\r
+ h_active = ANX7150_video_timing_parameter[3];\r
+ h_active = (h_active << 8) + ANX7150_video_timing_parameter[2];\r
+ h_res = ANX7150_video_timing_parameter[1];\r
+ h_res = (h_res << 8) + ANX7150_video_timing_parameter[0];\r
+ h_bp = ANX7150_video_timing_parameter[7];\r
+ h_bp = (h_bp << 8) + ANX7150_video_timing_parameter[6];\r
+ if (ANX7150_demux_yc_en)\r
+ {\r
+ hsync_width = 2* hsync_width;\r
+ h_active = 2 * h_active;\r
+ h_res = 2 * h_res;\r
+ h_bp = 2 * h_bp;\r
+ }\r
+ hsync_width_low = hsync_width & 0xff;\r
+ hsync_width_high = (hsync_width >> 8) & 0xff;\r
+ h_active_low = h_active & 0xff;\r
+ h_active_high = (h_active >> 8) & 0xff;\r
+ h_res_low = h_res & 0xff;\r
+ h_res_high = (h_res >> 8) & 0xff;\r
+ h_bp_low = h_bp & 0xff;\r
+ h_bp_high = (h_bp >> 8) & 0xff;\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = (c & 0xf7) | video_type;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = (c & 0xdf) | hsync_pol;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = (c & 0xbf) | vsync_pol;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = v_active_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEL_REG, &c);\r
+ c = v_active_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEH_REG, &c);\r
+ c = vsync_width;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
+ c = v_bp;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_TAIL2VIDLINE_REG, &c);\r
+ c = h_active_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXL_REG, &c);\r
+ c = h_active_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXH_REG, &c);\r
+ c = h_res_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESL_REG, &c);\r
+ c = h_res_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESH_REG, &c);\r
+ c = hsync_width_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
+ c = hsync_width_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
+ c = h_bp_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHL_REG, &c);\r
+ c = h_bp_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHH_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c |= ANX7150_VID_CAPCTRL0_DEGEN_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+\r
+ return rc;\r
+}\r
+static int anx7150_embed_sync_decode(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ char c;\r
+ u8 video_type,hsync_pol,vsync_pol,v_fp,vsync_width;\r
+ u8 h_fp_low,h_fp_high,hsync_width_low,hsync_width_high;\r
+ u32 h_fp,hsync_width;\r
+ \r
+ video_type = ANX7150_video_timing_parameter[15];\r
+ hsync_pol = ANX7150_video_timing_parameter[16];\r
+ vsync_pol = ANX7150_video_timing_parameter[17];\r
+ v_fp = ANX7150_video_timing_parameter[12];\r
+ vsync_width = ANX7150_video_timing_parameter[10];\r
+ h_fp = ANX7150_video_timing_parameter[14];\r
+ h_fp = (h_fp << 8) + ANX7150_video_timing_parameter[13];\r
+ hsync_width = ANX7150_video_timing_parameter[5];\r
+ hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
+ if (ANX7150_demux_yc_en)\r
+ {\r
+ h_fp = 2 * h_fp;\r
+ hsync_width = 2* hsync_width;\r
+ }\r
+ h_fp_low = h_fp & 0xff;\r
+ h_fp_high = (h_fp >> 8) & 0xff;\r
+ hsync_width_low = hsync_width & 0xff;\r
+ hsync_width_high = (hsync_width >> 8) & 0xff;\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = (c & 0xf7) | video_type;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = (c & 0xdf) | hsync_pol;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ c = (c & 0xbf) | vsync_pol;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c = c | ANX7150_VID_CAPCTRL0_EMSYNC_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+\r
+ c = v_fp;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINE2VSYNC_REG, &c);\r
+ c = vsync_width;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
+ c = h_fp_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHL_REG, &c);\r
+ c = h_fp_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHH_REG, &c);\r
+ c = hsync_width_low;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
+ c = hsync_width_high;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
+ return rc;\r
+}\r
+int ANX7150_Blue_Screen(struct anx7150_pdata *anx)\r
+{\r
+ return anx7150_blue_screen_format_config(anx->client);\r
+}\r
+//******************************Video Config***************************************\r
+int ANX7150_Config_Video(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ int retry = 0;\r
+ char c,TX_is_HDMI;\r
+ char cspace_y2r, y2r_sel, up_sample,range_y2r;\r
+\r
+ cspace_y2r = 0;\r
+ y2r_sel = 0;\r
+ up_sample = 0;\r
+ range_y2r = 0;\r
+\r
+ //ANX7150_RGBorYCbCr = 0x00; //RGB\r
+ //ANX7150_RGBorYCbCr = ANX7150_INPUT_COLORSPACE; //update\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+/*\r
+ if (!ANX7150_system_config_done)\r
+ {\r
+ D("System has not finished config!\n");\r
+ return;\r
+ }\r
+*/\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
+ if (!(c & 0x02))\r
+ {\r
+ hdmi_dbg(&client->dev, "No clock detected !\n");\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL2_REG, 0x02);\r
+ return -1;\r
+ }\r
+\r
+ rc = anx7150_clean_hdcp(client);\r
+\r
+ //color space issue\r
+ switch (ANX7150_video_timing_id)\r
+ {\r
+ case ANX7150_V1280x720p_50Hz:\r
+ case ANX7150_V1280x720p_60Hz:\r
+ case ANX7150_V1920x1080i_60Hz:\r
+ case ANX7150_V1920x1080i_50Hz:\r
+ case ANX7150_V1920x1080p_60Hz:\r
+ case ANX7150_V1920x1080p_50Hz:\r
+ y2r_sel = ANX7150_CSC_BT709;\r
+ break;\r
+ default:\r
+ y2r_sel = ANX7150_CSC_BT601;\r
+ break;\r
+ }\r
+ //rang[0~255]/[16~235] select\r
+ if (ANX7150_video_timing_id == ANX7150_V640x480p_60Hz)\r
+ range_y2r = 1;//rang[0~255]\r
+ else\r
+ range_y2r = 0;//rang[16~235]\r
+ if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr422) && (!ANX7150_edid_result.ycbcr422_supported))\r
+ {\r
+ up_sample = 1;\r
+ if (ANX7150_edid_result.ycbcr444_supported)\r
+ cspace_y2r = 0;\r
+ else\r
+ cspace_y2r = 1;\r
+ }\r
+ if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr444) && (!ANX7150_edid_result.ycbcr444_supported))\r
+ {\r
+ cspace_y2r = 1;\r
+ }\r
+ //Config the embeded blue screen format according to output video format.\r
+ rc = anx7150_blue_screen_format_config(client);\r
+\r
+ ANX7150_Parse_Video_Format();\r
+\r
+ if (ANX7150_de_gen_en)\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_de_gen_en!\n");\r
+ rc = anx7150_de_generator(client);\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c &= (~ANX7150_VID_CAPCTRL0_DEGEN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ }\r
+ if (ANX7150_emb_sync_mode)\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_Embed_Sync_Decode!\n");\r
+ rc = anx7150_embed_sync_decode(client);\r
+ \r
+ if (ANX7150_ddr_bus_mode) //jack wen; for DDR embeded sync\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ c |= (0x04);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ c &= (0xfb);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c &= (~ANX7150_VID_CAPCTRL0_EMSYNC_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ }\r
+ if (ANX7150_demux_yc_en)\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c |= (ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ \r
+ if (ANX7150_ycmux_u8_sel)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D1-4\r
+ hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D1-4\n");\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+\r
+ c = 0x0d;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
+ c = 0x0c;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
+ c = 0x0b;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
+ c = 0x0a;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
+ c = 0x09;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
+ c = 0x08;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
+ c = 0x01;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
+ //\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c &= (~ANX7150_VID_CTRL_YCu8_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D5-8,\r
+ hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D5-8\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ \r
+ c = 0x0d;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
+ c = 0x0c;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
+ c = 0x0b;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
+ c = 0x0a;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
+ c = 0x09;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
+ c = 0x08;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
+ c = 0x01;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
+ //\r
+ }\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c &= (~ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ //jack wen\r
+\r
+ //\r
+\r
+ }\r
+ if (ANX7150_ddr_bus_mode)\r
+ {\r
+ //D("ANX7150_ddr_bus_mode!\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c |= (ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ //jack wen\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ c = (c & 0xfc) | 0x02;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ \r
+ //jack wen\r
+\r
+ if (ANX7150_ddr_edge)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c |= (ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ }\r
+\r
+ //jack wen for DDR+seperate maping\r
+ if (ANX7150_video_format_config == 0x07)//jack wen, DDR yc422, 601,\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_DDR_601_Maping!\n");\r
+ \r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+\r
+ c = 0x0b;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL23, &c);\r
+ c = 0x0a;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL22, &c);\r
+ c = 0x09;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL21, &c);\r
+ c = 0x08;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL20, &c);\r
+ c = 0x07;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL19, &c);\r
+ c = 0x06;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL18, &c);\r
+ c = 0x05;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL17, &c);\r
+ c = 0x04;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL16, &c);\r
+\r
+ c = 0x17;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
+ c = 0x16;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
+ c = 0x15;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL13, &c);\r
+ c = 0x14;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
+ c = 0x13;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
+ c = 0x12;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
+ c = 0x11;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
+ c = 0x10;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
+\r
+ c = 0x03;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
+ c = 0x02;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
+ c = 0x01;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
+ c = 0x0f;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
+ c = 0x0e;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL2, &c);\r
+ c = 0x0d;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL1, &c);\r
+ c = 0x0c;\r
+ rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL0, &c);\r
+\r
+ }\r
+ else if (ANX7150_video_format_config == 0x08)//jack wen, DDR yc422, 656,\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150_DDR_656_Maping!\n");\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c &= (~ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+ c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ c &= (0xfc);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
+ }\r
+\r
+ if (cspace_y2r)\r
+ {\r
+ hdmi_dbg(&client->dev, "Color space Y2R enabled********\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c |= (ANX7150_VID_MODE_CSPACE_Y2R);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ if (y2r_sel)\r
+ {\r
+ hdmi_dbg(&client->dev, "Y2R_SEL!\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c |= (ANX7150_VID_MODE_Y2R_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c &= (~ANX7150_VID_MODE_Y2R_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c); \r
+ }\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c &= (~ANX7150_VID_MODE_CSPACE_Y2R);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ }\r
+\r
+ if (up_sample)\r
+ {\r
+ hdmi_dbg(&client->dev, "UP_SAMPLE!\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c |= (ANX7150_VID_MODE_UPSAMPLE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c &= (~ANX7150_VID_MODE_UPSAMPLE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ }\r
+\r
+ if (range_y2r)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c |= (ANX7150_VID_MODE_RANGE_Y2R);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ }\r
+ else\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c &= (~ANX7150_VID_MODE_RANGE_Y2R);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ }\r
+\r
+ if (!ANX7150_pix_rpt_set_by_sys)\r
+ {\r
+ if ((ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_16x9)\r
+ || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_16x9)\r
+ || (ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_4x3)\r
+ || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_4x3))\r
+ ANX7150_tx_pix_rpt = 1;\r
+ else\r
+ ANX7150_tx_pix_rpt = 0;\r
+ }\r
+ //set input pixel repeat times\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ c = ((c & 0xfc) |ANX7150_in_pix_rpt);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
+ //set link pixel repeat times\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c = ((c & 0xfc) |ANX7150_tx_pix_rpt);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+\r
+ if ((ANX7150_in_pix_rpt != ANX7150_in_pix_rpt_bkp)\r
+ ||(ANX7150_tx_pix_rpt != ANX7150_tx_pix_rpt_bkp) )\r
+ {\r
+ c = 0x02;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
+ hdmi_dbg(&client->dev, "MISC_Reset!\n");\r
+ ANX7150_in_pix_rpt_bkp = ANX7150_in_pix_rpt;\r
+ ANX7150_tx_pix_rpt_bkp = ANX7150_tx_pix_rpt;\r
+ }\r
+ //enable video input\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ c |= (ANX7150_VID_CTRL_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
+ //D("Video configure OK!\n");\r
+\r
+ retry = 0;\r
+ do{\r
+ mdelay(60);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_STATUS_REG, &c);\r
+ if (c & ANX7150_VID_STATUS_VID_STABLE){\r
+ hdmi_dbg(&client->dev, "Video stable, continue!\n");\r
+ break;\r
+ }\r
+ else{\r
+ hdmi_dbg(&client->dev,"Video not stable!, retry = %d\n", retry);\r
+ }\r
+ }while(retry++ < 5);\r
+\r
+ if (cspace_y2r)\r
+ ANX7150_RGBorYCbCr = ANX7150_RGB;\r
+ //Enable video CLK,Format change after config video.\r
+ // ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
+ // ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, c |0x01);//3\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
+ c |= (0x48);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
+ c |= (0x40);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
+ \r
+ if (ANX7150_edid_result.is_HDMI)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c |= (0x02);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ hdmi_dbg(&client->dev,"ANX7150 is set to HDMI mode\n");\r
+ }\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ TX_is_HDMI = c & 0x02;\r
+\r
+ if (TX_is_HDMI == 0x02)\r
+ {\r
+ anx7150_set_avmute(client);//wen\r
+ }\r
+\r
+ //reset TMDS link to align 4 channels xy 061120\r
+ hdmi_dbg(&client->dev,"reset TMDS link to align 4 channels\n");\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
+ c |= (ANX7150_TX_RST);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
+ c &= (~ANX7150_TX_RST);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
+ \r
+ //Enable TMDS clock output // just enable u87, and let the other u8s along to avoid overwriting.\r
+ hdmi_dbg(&client->dev,"Enable TMDS clock output\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+ c |= (ANX7150_TMDS_CLKCH_MUTE);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
+ if(ANX7150_HDCP_enable)\r
+ mdelay(100); //400ms only for HDCP CTS\r
+\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_VID_MODE_REG, &c); //zy 061110\r
+ return 0;\r
+}\r
+static u8 anx7150_config_i2s(struct i2c_client *client)\r
+{\r
+ int rc;\r
+ char c = 0x00;\r
+ u8 exe_result = 0x00;\r
+ char c1 = 0x00;\r
+\r
+ hdmi_dbg(&client->dev,"ANX7150: config i2s audio.\n");\r
+\r
+ //select SCK as source\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= ~ANX7150_HDMI_AUDCTRL1_CLK_SEL;\r
+ hdmi_dbg(&client->dev,"select SCK as source, c = 0x%.2x\n",(u32)c);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+\r
+ //config i2s channel\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c1 = s_ANX7150_audio_config.i2s_config.audio_channel; // need u8[5:2]\r
+ c1 &= 0x3c;\r
+ c &= ~0x3c;\r
+ c |= c1;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ hdmi_dbg(&client->dev,"config i2s channel, c = 0x%.2x\n",(u32)c);\r
+ \r
+ //config i2s format\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_I2S_CTRL_REG, &c);\r
+ c = s_ANX7150_audio_config.i2s_config.i2s_format;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
+ hdmi_dbg(&client->dev,"config i2s format, c = 0x%.2x\n",(u32)c);\r
+\r
+ //map i2s fifo\r
+\r
+ //TODO: config I2S channel map register according to system\r
+\r
+\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_CTRL_REG, c);\r
+\r
+ //swap right/left channel\r
+ /*ANX7150_i2c_read_p0_reg(ANX7150_I2SCH_SWCTRL_REG, &c);\r
+ c1 = 0x00;\r
+ c1 &= 0xf0;\r
+ c &= ~0xf0;\r
+ c |= c1;\r
+ ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_SWCTRL_REG, c);\r
+ D("map i2s ffio, c = 0x%.2x\n",(u32)c);*/\r
+\r
+ //down sample\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c1 = s_ANX7150_audio_config.down_sample;\r
+ c1 &= 0x60;\r
+ c &= ~0x60;\r
+ c |= c1;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ hdmi_dbg(&client->dev,"down sample, c = 0x%.2x\n",(u32)c);\r
+\r
+ //config i2s channel status(5 regs)\r
+ c = s_ANX7150_audio_config.i2s_config.Channel_status1;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS1_REG, &c);\r
+ c = s_ANX7150_audio_config.i2s_config.Channel_status2;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS2_REG, &c);\r
+ c = s_ANX7150_audio_config.i2s_config.Channel_status3;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS3_REG, &c);\r
+ c = s_ANX7150_audio_config.i2s_config.Channel_status4;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ hdmi_dbg(&client->dev,"@@@@@@@@config i2s channel status4, c = 0x%.2x\n",(unsigned int)c);//jack wen\r
+\r
+ c = s_ANX7150_audio_config.i2s_config.Channel_status5;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS5_REG, &c);\r
+ hdmi_dbg(&client->dev,"config i2s channel status, c = 0x%.2x\n",(u32)c);\r
+\r
+ exe_result = ANX7150_i2s_input;\r
+ //D("return = 0x%.2x\n",(u32)exe_result);\r
+\r
+ // open corresponding interrupt\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, (c | 0x22) );\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0x20) );\r
+\r
+\r
+ return exe_result;\r
+}\r
+\r
+static u8 anx7150_config_spdif(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ u8 exe_result = 0x00;\r
+ char c = 0x00;\r
+ char c1 = 0x00;\r
+ // u8 c2 = 0x00;\r
+ // u8 freq_mclk = 0x00;\r
+\r
+ hdmi_dbg(&client->dev, "ANX7150: config SPDIF audio.\n");\r
+\r
+\r
+ //Select MCLK\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c |= (ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ //D("ANX7150: enable SPDIF audio.\n");\r
+ //Enable SPDIF\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c |= (ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ //adjust MCLK phase in interrupt routine\r
+\r
+ // adjust FS_FREQ //FS_FREQ\r
+ c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
+ c &= ANX7150_SPDIFCH_STATUS_FS_FREG;\r
+ c = c >> 4;\r
+\r
+ if ( c != c1)\r
+ {\r
+ //D("adjust FS_FREQ by system!\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ c &= 0xf0;\r
+ c |= c1;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+\r
+ //enable using FS_FREQ from 0x59\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c |= (0x02);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ }\r
+\r
+ // down sample\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c1 = s_ANX7150_audio_config.down_sample;\r
+ c1 &= 0x60;\r
+ c &= ~0x60;\r
+ c |= c1;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+\r
+ if (s_ANX7150_audio_config.down_sample) //zy 060816\r
+ {\r
+ // adjust FS_FREQ by system because down sample\r
+ //D("adjust FS_FREQ by system because down sample!\n");\r
+\r
+ c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ \r
+ c &= 0xf0;\r
+ c |= c1;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ }\r
+\r
+\r
+ // spdif is stable\r
+ hdmi_dbg(&client->dev, "config SPDIF audio done");\r
+ exe_result = ANX7150_spdif_input;\r
+\r
+ // open corresponding interrupt\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
+ c |= (0x32);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0xa1) );\r
+ return exe_result;\r
+}\r
+\r
+static u8 anx7150_config_super_audio(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ u8 exe_result = 0x00;\r
+ u8 c = 0x00;\r
+\r
+\r
+ //D("ANX7150: config one u8 audio.\n");\r
+\r
+ // select sck as source\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= (~ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+\r
+ // Enable stream 0x60\r
+ c = s_ANX7150_audio_config.super_audio_config.one_u8_ctrl;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
+\r
+\r
+ // Map stream 0x61\r
+ // TODO: config super audio map register according to system\r
+\r
+ exe_result = ANX7150_super_audio_input;\r
+ return exe_result;\r
+\r
+}\r
+\r
+u8 ANX7150_Config_Audio(struct i2c_client *client)\r
+{\r
+ int rc;\r
+ char c = 0x00;\r
+ u8 exe_result = 0x00;\r
+ u8 audio_layout = 0x00;\r
+ u8 fs = 0x00;\r
+ u32 ACR_N = 0x0000;\r
+\r
+ //set audio clock edge\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c = ((c & 0xf7) | ANX7150_audio_clock_edge);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ \r
+ //cts get select from SCK\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c = (c & 0xef);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ hdmi_dbg(&client->dev, "audio_type = 0x%.2x\n",(u32)s_ANX7150_audio_config.audio_type);\r
+ if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
+ {\r
+ hdmi_dbg(&client->dev, "Config I2s.\n");\r
+ exe_result |= anx7150_config_i2s(client);\r
+ }\r
+ else\r
+ {\r
+ //disable I2S audio input\r
+ hdmi_dbg(&client->dev, "Disable I2S audio input.\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= 0xc3;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ }\r
+\r
+ if (s_ANX7150_audio_config.audio_type & ANX7150_spdif_input)\r
+ {\r
+ exe_result |= anx7150_config_spdif(client);\r
+ }\r
+ else\r
+ {\r
+ //disable SPDIF audio input\r
+ hdmi_dbg(&client->dev, "Disable SPDIF audio input.\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= ~ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ }\r
+\r
+ if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
+ {\r
+ exe_result |= anx7150_config_super_audio(client);\r
+ }\r
+ else\r
+ {\r
+ //disable super audio output\r
+ hdmi_dbg(&client->dev, "ANX7150: disable super audio output.\n");\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
+ }\r
+\r
+ if ((s_ANX7150_audio_config.audio_type & 0x07) == 0x00)\r
+ {\r
+ hdmi_dbg(&client->dev, "ANX7150 input no audio type.\n");\r
+ }\r
+\r
+ //audio layout\r
+ if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
+ {\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ audio_layout = s_ANX7150_audio_config.audio_layout;\r
+\r
+ //HDMI_RX_ReadI2C_RX0(0x15, &c);\r
+#if 0\r
+ if ((c & 0x08) ==0x08 ) //u8[5:3]\r
+ {\r
+ audio_layout = 0x80;\r
+ }\r
+ else\r
+ {\r
+ audio_layout = 0x00;\r
+ }\r
+#endif\r
+ }\r
+ if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
+ if ( c & 0xfc) //u8[5:3]\r
+ {\r
+ audio_layout = 0x80;\r
+ }\r
+ }\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c &= ~0x80;\r
+ c |= audio_layout;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+\r
+ if ( (s_ANX7150_audio_config.audio_type & 0x07) == exe_result )\r
+ {\r
+ //Initial N value\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ fs = c & 0x0f;\r
+ // set default value to N\r
+ ACR_N = ANX7150_N_48k;\r
+ switch (fs)\r
+ {\r
+ case(0x00)://44.1k\r
+ ACR_N = ANX7150_N_44k;\r
+ break;\r
+ case(0x02)://48k\r
+ ACR_N = ANX7150_N_48k;\r
+ break;\r
+ case(0x03)://32k\r
+ ACR_N = ANX7150_N_32k;\r
+ break;\r
+ case(0x08)://88k\r
+ ACR_N = ANX7150_N_88k;\r
+ break;\r
+ case(0x0a)://96k\r
+ ACR_N = ANX7150_N_96k;\r
+ break;\r
+ case(0x0c)://176k\r
+ ACR_N = ANX7150_N_176k;\r
+ break;\r
+ case(0x0e)://192k\r
+ ACR_N = ANX7150_N_192k;\r
+ break;\r
+ default:\r
+ dev_err(&client->dev, "note wrong fs.\n");\r
+ break;\r
+ }\r
+ // write N(ACR) to corresponding regs\r
+ c = ACR_N;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N1_SW_REG, &c);\r
+ c = ACR_N>>8;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N2_SW_REG, &c);\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N3_SW_REG, &c);\r
+ \r
+ // set the relation of MCLK and Fs xy 070117\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c = (c & 0xf8) | FREQ_MCLK;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ hdmi_dbg(&client->dev, "Audio MCLK input mode is: %.2x\n",(u32)FREQ_MCLK);\r
+\r
+ //Enable control of ACR\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ c |= (ANX7150_INFO_PKTCTRL1_ACR_EN);\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ //audio enable:\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c |= (ANX7150_HDMI_AUDCTRL1_IN_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ }\r
+\r
+ return exe_result;\r
+\r
+}\r
+static u8 ANX7150_Checksum(infoframe_struct *p)\r
+{
+ u8 checksum = 0x00;
+ u8 i;
+
+ checksum = p->type + p->length + p->version;
+ for (i=1; i <= p->length; i++)
+ {
+ checksum += p->pb_u8[i];
+ }
+ checksum = ~checksum;
+ checksum += 0x01;
+
+ return checksum;
+}\r
+static u8 anx7150_load_infoframe(struct i2c_client *client, packet_type member,\r
+ infoframe_struct *p)\r
+{\r
+ int rc = 0;\r
+ u8 exe_result = 0x00;\r
+ u8 address[8] = {0x00,0x20,0x40,0x60,0x80,0x80,0xa0,0xa0};\r
+ u8 i;\r
+ char c;\r
+\r
+ p->pb_u8[0] = ANX7150_Checksum(p);\r
+\r
+ // write infoframe to according regs\r
+ c = p->type;\r
+ rc = anx7150_i2c_write_p1_reg(client, address[member], &c);\r
+ c = p->version;\r
+ rc = anx7150_i2c_write_p1_reg(client, address[member]+1, &c);\r
+ c = p->length;\r
+ rc = anx7150_i2c_write_p1_reg(client, address[member]+2, &c);\r
+\r
+ for (i=0; i <= p->length; i++)\r
+ {\r
+ c = p->pb_u8[i];\r
+ rc = anx7150_i2c_write_p1_reg(client, address[member]+3+i, &c);\r
+ rc = anx7150_i2c_read_p1_reg(client, address[member]+3+i, &c);\r
+ }\r
+ return exe_result;\r
+}\r
+\r
+//*************** Config Packet ****************************\r
+u8 ANX7150_Config_Packet(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ u8 exe_result = 0x00; // There is no use in current solution\r
+ u8 info_packet_sel;\r
+ char c;\r
+\r
+ info_packet_sel = s_ANX7150_packet_config.packets_need_config;\r
+ hdmi_dbg(&client->dev, "info_packet_sel = 0x%.2x\n",(u32) info_packet_sel);\r
+ // New packet?\r
+ if ( info_packet_sel != 0x00)\r
+ {\r
+ // avi infoframe\r
+ if ( info_packet_sel & ANX7150_avi_sel )\r
+ {\r
+ c = s_ANX7150_packet_config.avi_info.pb_u8[1]; //color space\r
+ c &= 0x9f;\r
+ c |= (ANX7150_RGBorYCbCr << 5);\r
+ s_ANX7150_packet_config.avi_info.pb_u8[1] = c | 0x10;\r
+ switch(ANX7150_video_timing_id) \r
+ {\r
+ case ANX7150_V720x480p_60Hz_4x3:\r
+ case ANX7150_V720x480p_60Hz_16x9:\r
+ case ANX7150_V720x576p_50Hz_4x3:\r
+ case ANX7150_V720x576p_50Hz_16x9:\r
+ s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x58;\r
+ break;\r
+ case ANX7150_V1280x720p_50Hz:\r
+ case ANX7150_V1280x720p_60Hz:\r
+ case ANX7150_V1920x1080p_50Hz:\r
+ case ANX7150_V1920x1080p_60Hz:\r
+ s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xa8;\r
+ break;\r
+ default:\r
+ s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xa8;\r
+ break;\r
+ }\r
+\r
+ c = s_ANX7150_packet_config.avi_info.pb_u8[4];// vid ID\r
+ c = c & 0x80;\r
+ s_ANX7150_packet_config.avi_info.pb_u8[4] = c | ANX7150_video_timing_id;\r
+ c = s_ANX7150_packet_config.avi_info.pb_u8[5]; //repeat times\r
+ c = c & 0xf0;\r
+ c |= (ANX7150_tx_pix_rpt & 0x0f);\r
+ s_ANX7150_packet_config.avi_info.pb_u8[5] = c;\r
+ hdmi_dbg(&client->dev, "config avi infoframe packet.\n");\r
+ // Disable repeater\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL1_AVI_RPT;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+\r
+ // Enable?wait:go\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ if (c & ANX7150_INFO_PKTCTRL1_AVI_EN)\r
+ {\r
+ //D("wait disable, config avi infoframe packet.\n");\r
+ return exe_result; //jack wen\r
+ }\r
+\r
+ // load packet data to regs\r
+ rc = anx7150_load_infoframe(client, ANX7150_avi_infoframe,\r
+ &(s_ANX7150_packet_config.avi_info));\r
+ // Enable and repeater\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ c |= 0x30;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
+\r
+ // complete avi packet\r
+ hdmi_dbg(&client->dev, "config avi infoframe packet done.\n");\r
+ s_ANX7150_packet_config.packets_need_config &= ~ANX7150_avi_sel;\r
+\r
+ }\r
+\r
+ // audio infoframe\r
+ if ( info_packet_sel & ANX7150_audio_sel )\r
+ {\r
+ hdmi_dbg(&client->dev, "config audio infoframe packet.\n");\r
+\r
+ // Disable repeater\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+\r
+ // Enable?wait:go\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ if (c & ANX7150_INFO_PKTCTRL2_AIF_EN)\r
+ {\r
+ //D("wait disable, config audio infoframe packet.\n");\r
+ //return exe_result;//jack wen\r
+ }\r
+ // config packet\r
+\r
+ // load packet data to regs\r
+ \r
+ anx7150_load_infoframe( client, ANX7150_audio_infoframe,\r
+ &(s_ANX7150_packet_config.audio_info));\r
+ // Enable and repeater\r
+ rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0x03;\r
+ rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
+\r
+ // complete avi packet\r
+\r
+ hdmi_dbg(&client->dev, "config audio infoframe packet done.\n");\r
+ s_ANX7150_packet_config.packets_need_config &= ~ANX7150_audio_sel;\r
+\r
+ }\r
+\r
+ // config other 4 packets\r
+ /*\r
+\r
+ if( info_packet_sel & 0xfc )\r
+ {\r
+ D("other packets.\n");\r
+\r
+ //find the current type need config\r
+ if(info_packet_sel & ANX7150_spd_sel) type_sel = ANX7150_spd_sel;\r
+ else if(info_packet_sel & ANX7150_mpeg_sel) type_sel = ANX7150_mpeg_sel;\r
+ else if(info_packet_sel & ANX7150_acp_sel) type_sel = ANX7150_acp_sel;\r
+ else if(info_packet_sel & ANX7150_isrc1_sel) type_sel = ANX7150_isrc1_sel;\r
+ else if(info_packet_sel & ANX7150_isrc2_sel) type_sel = ANX7150_isrc2_sel;\r
+ else type_sel = ANX7150_vendor_sel;\r
+\r
+\r
+ // Disable repeater\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+\r
+ switch(type_sel)\r
+ {\r
+ case ANX7150_spd_sel:\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL1_SPD_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
+\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ if(c & ANX7150_INFO_PKTCTRL1_SPD_EN)\r
+ {\r
+ D("wait disable, config spd infoframe packet.\n");\r
+ return exe_result;\r
+ }\r
+ break;\r
+\r
+ case ANX7150_mpeg_sel:\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_MPEG_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ if(c & ANX7150_INFO_PKTCTRL2_MPEG_EN)\r
+ {\r
+ D("wait disable, config mpeg infoframe packet.\n");\r
+ return exe_result;\r
+ }\r
+ break;\r
+\r
+ case ANX7150_acp_sel:\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
+ {\r
+ D("wait disable, config mpeg infoframe packet.\n");\r
+ return exe_result;\r
+ }\r
+ break;\r
+\r
+ case ANX7150_isrc1_sel:\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
+ {\r
+ D("wait disable, config isrc1 packet.\n");\r
+ return exe_result;\r
+ }\r
+ break;\r
+\r
+ case ANX7150_isrc2_sel:\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
+ {\r
+ D("wait disable, config isrc2 packet.\n");\r
+ return exe_result;\r
+ }\r
+ break;\r
+\r
+ case ANX7150_vendor_sel:\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
+ {\r
+ D("wait disable, config vendor packet.\n");\r
+ return exe_result;\r
+ }\r
+ break;\r
+\r
+ default : break;\r
+ }\r
+\r
+\r
+ // config packet\r
+ // TODO: config packet in top level\r
+\r
+ // load packet data to regs\r
+ switch(type_sel)\r
+ {\r
+ case ANX7150_spd_sel:\r
+ ANX7150_Load_Infoframe( ANX7150_spd_infoframe,\r
+ &(s_ANX7150_packet_config.spd_info));\r
+ D("config spd done.\n");\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
+ c |= 0xc0;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
+ break;\r
+\r
+ case ANX7150_mpeg_sel:\r
+ ANX7150_Load_Infoframe( ANX7150_mpeg_infoframe,\r
+ &(s_ANX7150_packet_config.mpeg_info));\r
+ D("config mpeg done.\n");\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0x0c;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ break;\r
+\r
+ case ANX7150_acp_sel:\r
+ ANX7150_Load_Packet( ANX7150_acp_packet,\r
+ &(s_ANX7150_packet_config.acp_pkt));\r
+ D("config acp done.\n");\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0x30;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ break;\r
+\r
+ case ANX7150_isrc1_sel:\r
+ ANX7150_Load_Packet( ANX7150_isrc1_packet,\r
+ &(s_ANX7150_packet_config.acp_pkt));\r
+ D("config isrc1 done.\n");\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0x30;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ break;\r
+\r
+ case ANX7150_isrc2_sel:\r
+ ANX7150_Load_Packet( ANX7150_isrc2_packet,\r
+ &(s_ANX7150_packet_config.acp_pkt));\r
+ D("config isrc2 done.\n");\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0xc0;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ break;\r
+\r
+ case ANX7150_vendor_sel:\r
+ ANX7150_Load_Infoframe( ANX7150_vendor_infoframe,\r
+ &(s_ANX7150_packet_config.vendor_info));\r
+ D("config vendor done.\n");\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0xc0;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+ break;\r
+\r
+ default : break;\r
+ }\r
+\r
+ // Enable and repeater\r
+ ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
+ c |= 0x03;\r
+ ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
+\r
+ // complete config packet\r
+ D("config other packets done.\n");\r
+ s_ANX7150_packet_config.packets_need_config &= ~type_sel;\r
+\r
+ }\r
+ */\r
+ }\r
+\r
+\r
+ if ( s_ANX7150_packet_config.packets_need_config == 0x00)\r
+ {\r
+ hdmi_dbg(&client->dev, "config packets done\n");\r
+ //ANX7150_Set_System_State(ANX7150_HDCP_AUTHENTICATION);\r
+ }\r
+\r
+\r
+ return exe_result;\r
+}\r
+//******************** HDCP process ********************************\r
+static int anx7150_hardware_hdcp_auth_init(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ u8 c;\r
+\r
+// ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c); //72:07.2 hdcp on\r
+// ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, (c | ANX7150_SYS_CTRL1_HDCPMODE));\r
+ // disable hw hdcp\r
+// ANX7150_i2c_read_p0_reg(ANX7150_HDCP_CTRL0_REG, &c);\r
+// ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, (c & (~ANX7150_HDCP_CTRL0_HW_AUTHEN)));\r
+\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, 0x03); //h/w auth off, jh simplay/hdcp\r
+ c = 0x00;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //bit 0/1 off, as from start, we don't know if Bksv/srm/KSVList valid or not. SY.\r
+\r
+ // DDC reset\r
+ rc = anx7150_rst_ddcchannel(client);\r
+\r
+ anx7150_initddc_read(client, 0x74, 0x00, 0x40, 0x01, 0x00);\r
+ mdelay(5);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bcaps);\r
+ hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): ANX7150_hdcp_bcaps = 0x%.2x\n", (u32)ANX7150_hdcp_bcaps);\r
+\r
+ if (ANX7150_hdcp_bcaps & 0x02)\r
+ { //enable 1.1 feature\r
+ hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps supports 1.1\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
+ c |= ANX7150_HDCP_CTRL1_HDCP11_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
+ }\r
+ else\r
+ { //disable 1.1 feature and enable HDCP two special point check\r
+ hdmi_dbg(&client->dev, "bcaps don't support 1.1\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
+ c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
+ }\r
+ //handle repeater bit. SY.\r
+ if (ANX7150_hdcp_bcaps & 0x40)\r
+ {\r
+ //repeater\r
+ hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a repeater\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c |= ANX7150_HDCP_CTRL0_RX_REP;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ }\r
+ else\r
+ {\r
+ //receiver\r
+ hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a receiver\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= ~ANX7150_HDCP_CTRL0_RX_REP;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ }\r
+ anx7150_rst_ddcchannel(client);\r
+ ANX7150_hdcp_auth_en = 0;\r
+\r
+ return rc;\r
+}\r
+static u8 anx7150_bksv_srm(struct i2c_client *client)\r
+{
+ int rc = 0;\r
+#if 1
+ u8 bksv[5],i,bksv_one,c1;
+ anx7150_initddc_read(client, 0x74, 0x00, 0x00, 0x05, 0x00);\r
+ mdelay(15);\r
+ for (i = 0; i < 5; i ++)
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &bksv[i]);\r
+ }
+
+ bksv_one = 0;
+ for (i = 0; i < 8; i++)
+ {
+ c1 = 0x01 << i;
+ if (bksv[0] & c1)
+ bksv_one ++;
+ if (bksv[1] & c1)
+ bksv_one ++;
+ if (bksv[2] & c1)
+ bksv_one ++;
+ if (bksv[3] & c1)
+ bksv_one ++;
+ if (bksv[4] & c1)
+ bksv_one ++;
+ }
+ //wen HDCP CTS
+ if (bksv_one != 20)
+ {
+ hdmi_dbg(&client->dev, "BKSV check fail\n");\r
+ return 0;
+ }
+ else
+ {
+ hdmi_dbg(&client->dev, "BKSV check OK\n");\r
+ return 1;
+ }
+#endif
+
+#if 0 //wen HDCP CTS
+ /*address by gerard.zhu*/
+ u8 i,j,bksv_ones_count,bksv_data[Bksv_Data_Nums] = {0};
+ ANX7150_DDC_Addr bksv_ddc_addr;
+ u32 bksv_length;
+ ANX7150_DDC_Type ddc_type;
+
+ i = 0;
+ j = 0;
+ bksv_ones_count = 0;
+ bksv_ddc_addr.dev_addr = HDCP_Dev_Addr;
+ bksv_ddc_addr.sgmt_addr = 0;
+ bksv_ddc_addr.offset_addr = HDCP_Bksv_Offset;
+ bksv_length = Bksv_Data_Nums;
+ ddc_type = DDC_Hdcp;
+
+ if (!ANX7150_DDC_Read(bksv_ddc_addr, bksv_data, bksv_length, ddc_type))
+ {
+ /*Judge validity for Bksv*/
+ while (i < Bksv_Data_Nums)
+ {
+ while (j < 8)
+ {
+ if (((bksv_data[i] >> j) & 0x01) == 1)
+ {
+ bksv_ones_count++;
+ }
+ j++;
+ }
+ i++;
+ j = 0;
+ }
+ if (bksv_ones_count != 20)
+ {
+ rk29printk ("!!!!BKSV 1s ¡Ù20\n"); //update rk29printk ("!!!!BKSV 1s ¡Ù20\n");
+ return 0;
+ }
+ }
+ /*end*/
+
+ D("bksv is ready.\n");
+ // TODO: Compare the bskv[] value to the revocation list to decide if this value is a illegal BKSV. This is system depended.
+ //If illegal, return 0; legal, return 1. Now just return 1
+ return 1;
+#endif
+}\r
+\r
+static u8 anx7150_is_ksvlist_vld(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+//wen HDCP CTS\r
+#if 1\r
+ hdmi_dbg(&client->dev, "ANX7150_IS_KSVList_VLD() is called.\n");\r
+ anx7150_initddc_read(client, 0x74, 0x00, 0x41, 0x02, 0x00); //Bstatus, two u8s\r
+ mdelay(5);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[0]);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[1]);\r
+\r
+ if ((ANX7150_hdcp_bstatus[0] & 0x80) | (ANX7150_hdcp_bstatus[1] & 0x08))\r
+ {\r
+ hdmi_dbg(&client->dev, "Max dev/cascade exceeded: ANX7150_hdcp_bstatus[0]: 0x%x,ANX7150_hdcp_bstatus[1]:0x%x\n", (u32)ANX7150_hdcp_bstatus[0],(u32)ANX7150_hdcp_bstatus[1]);\r
+ return 0;//HDCP topology error. More than 127 RX are attached or more than seven levels of repeater are cascaded.\r
+ }\r
+ return 1;\r
+#endif\r
+//wen HDCP CTS\r
+\r
+}\r
+\r
+static void anx7150_show_video_parameter(struct i2c_client *client)\r
+{\r
+ int rc = 0;\r
+ // int h_res,h_act,v_res,v_act,h_fp,hsync_width,h_bp;\r
+ char c, c1;\r
+\r
+ hdmi_dbg(&client->dev, "\n\n**********************************ANX7150 Info**********************************\n");\r
+\r
+ hdmi_dbg(&client->dev, " ANX7150 mode = Normal mode\n");\r
+ if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 0))\r
+ hdmi_dbg(&client->dev, " Input video format = YC_MUX\n");\r
+ if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 1))\r
+ hdmi_dbg(&client->dev, " Input video format = 656\n");\r
+ if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 1))\r
+ hdmi_dbg(&client->dev, " Input video format = YC_MUX + 656\n");\r
+ if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 0))\r
+ hdmi_dbg(&client->dev, " Input video format = Seperate Sync\n");\r
+ if (ANX7150_de_gen_en)\r
+ hdmi_dbg(&client->dev, " DE generator = Enable\n");\r
+ else\r
+ hdmi_dbg(&client->dev, " DE generator = Disable\n");\r
+ if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 0))\r
+ hdmi_dbg(&client->dev, " Input video format = DDR mode\n");\r
+ else if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 1))\r
+ hdmi_dbg(&client->dev, " Input video format = DDR mode + 656\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c1);\r
+ c1 = (c1 & 0x02);\r
+ if (c1)\r
+ {\r
+ hdmi_dbg(&client->dev, " Output video mode = HDMI\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, 0x04, &c);\r
+ c = (c & 0x60) >> 5;\r
+ switch (c)\r
+ {\r
+ case ANX7150_RGB:\r
+ hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
+ break;\r
+ case ANX7150_YCbCr422:\r
+ hdmi_dbg(&client->dev, " Output video color format = YCbCr422\n");\r
+ break;\r
+ case ANX7150_YCbCr444:\r
+ hdmi_dbg(&client->dev, " Output video color format = YCbCr444\n");\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hdmi_dbg(&client->dev, " Output video mode = DVI\n");\r
+ hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
+ }\r
+\r
+ /*for(i = 0x10; i < 0x25; i ++)\r
+ {\r
+ ANX7150_i2c_read_p0_reg(i, &c );\r
+ D("0x%.2x = 0x%.2x\n",(unsigned int)i,(unsigned int)c);\r
+ }*/\r
+ /* ANX7150_i2c_read_p0_reg(ANX7150_VID_STATUS_REG, &c);\r
+ if((c & ANX7150_VID_STATUS_TYPE) == 0x04)\r
+ D("Video Type = Interlace");\r
+ else\r
+ D("Video Type = Progressive");\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESH_REG, &c);\r
+ h_res = c;\r
+ h_res = h_res << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESL_REG, &c);\r
+ h_res = h_res + c;\r
+ D("H_resolution = %u\n",h_res);\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXH_REG, &c);\r
+ h_act = c;\r
+ h_act = h_act << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXL_REG, &c);\r
+ h_act = h_act + c;\r
+ D("H_active = %u\n",h_act);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESH_REG, &c);\r
+ v_res = c;\r
+ v_res = v_res << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESL_REG, &c);\r
+ v_res = v_res + c;\r
+ D("V_resolution = %u\n",v_res);\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEH_REG, &c);\r
+ v_act = c;\r
+ v_act = v_act << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEL_REG, &c);\r
+ v_act = v_act + c;\r
+ D("V_active = %u\n",v_act);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHH_REG, &c);\r
+ h_fp = c;\r
+ h_fp = h_fp << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHL_REG, &c);\r
+ h_fp = h_fp + c;\r
+ D("H_FP = %u\n",h_fp);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHH_REG, &c);\r
+ h_bp = c;\r
+ h_bp = h_bp << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHL_REG, &c);\r
+ h_bp = h_bp + c;\r
+ D("H_BP = %u\n",h_bp);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDH_REG, &c);\r
+ hsync_width = c;\r
+ hsync_width = hsync_width << 8;\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDL_REG, &c);\r
+ hsync_width = hsync_width + c;\r
+ D("Hsync_width = %u\n",hsync_width);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTLINE2VSYNC_REG, &c);\r
+ D("Vsync_FP = %bu\n",c);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG, &c);\r
+ D("Vsync_BP = %bu\n",c);\r
+\r
+ ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCWIDLINE_REG, &c);\r
+ D("Vsync_width = %bu\n",c);*/\r
+ {\r
+ hdmi_dbg(&client->dev, " Normal mode output video format: \n");\r
+ switch (ANX7150_video_timing_id)\r
+ {\r
+ case ANX7150_V720x480p_60Hz_4x3:\r
+ case ANX7150_V720x480p_60Hz_16x9:\r
+ hdmi_dbg(&client->dev, "720x480p@60\n");\r
+ if (ANX7150_edid_result.supported_720x480p_60Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V1280x720p_60Hz:\r
+ hdmi_dbg(&client->dev, "1280x720p@60\n");\r
+ if (ANX7150_edid_result.supported_720p_60Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V1920x1080i_60Hz:\r
+ hdmi_dbg(&client->dev, "1920x1080i@60\n");\r
+ if (ANX7150_edid_result.supported_1080i_60Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V1920x1080p_60Hz:\r
+ hdmi_dbg(&client->dev, "1920x1080p@60\n");\r
+ if (ANX7150_edid_result.supported_1080p_60Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V1920x1080p_50Hz:\r
+ hdmi_dbg(&client->dev, "1920x1080p@50\n");\r
+ if (ANX7150_edid_result.supported_1080p_50Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V1280x720p_50Hz:\r
+ hdmi_dbg(&client->dev, "1280x720p@50\n");\r
+ if (ANX7150_edid_result.supported_720p_50Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V1920x1080i_50Hz:\r
+ hdmi_dbg(&client->dev, "1920x1080i@50\n");\r
+ if (ANX7150_edid_result.supported_1080i_50Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V720x576p_50Hz_4x3:\r
+ case ANX7150_V720x576p_50Hz_16x9:\r
+ hdmi_dbg(&client->dev, "720x576p@50\n");\r
+ if (ANX7150_edid_result.supported_576p_50Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V720x576i_50Hz_4x3:\r
+ case ANX7150_V720x576i_50Hz_16x9:\r
+ hdmi_dbg(&client->dev, "720x576i@50\n");\r
+ if (ANX7150_edid_result.supported_576i_50Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ case ANX7150_V720x480i_60Hz_4x3:\r
+ case ANX7150_V720x480i_60Hz_16x9:\r
+ hdmi_dbg(&client->dev, "720x480i@60\n");\r
+ if (ANX7150_edid_result.supported_720x480i_60Hz)\r
+ hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
+ break;\r
+ default:\r
+ hdmi_dbg(&client->dev, "unknown(video ID is: %.2x).\n",(u32)ANX7150_video_timing_id);\r
+ break;\r
+ }\r
+ }\r
+ if (c1)//HDMI output\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c = c & 0x03;\r
+ hdmi_dbg(&client->dev, " MCLK Frequence = ");\r
+\r
+ switch (c)\r
+ {\r
+ case 0x00:\r
+ hdmi_dbg(&client->dev, "128 * Fs.\n");\r
+ break;\r
+ case 0x01:\r
+ hdmi_dbg(&client->dev, "256 * Fs.\n");\r
+ break;\r
+ case 0x02:\r
+ hdmi_dbg(&client->dev, "384 * Fs.\n");\r
+ break;\r
+ case 0x03:\r
+ hdmi_dbg(&client->dev, "512 * Fs.\n");\r
+ break;\r
+ default :\r
+ hdmi_dbg(&client->dev, "Wrong MCLK output.\n");\r
+ break;\r
+ }\r
+\r
+ if ( ANX7150_AUD_HW_INTERFACE == 0x01)\r
+ {\r
+ hdmi_dbg(&client->dev, " Input Audio Interface = I2S.\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ }\r
+ else if (ANX7150_AUD_HW_INTERFACE == 0x02)\r
+ {\r
+ hdmi_dbg(&client->dev, " Input Audio Interface = SPDIF.\n");\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
+ c=c>>4;\r
+ }\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
+ hdmi_dbg(&client->dev, " Audio Fs = ");\r
+ c &= 0x0f;\r
+ switch (c)\r
+ {\r
+ case 0x00:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 44.1 KHz.\n");\r
+ break;\r
+ case 0x02:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 48 KHz.\n");\r
+ break;\r
+ case 0x03:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 32 KHz.\n");\r
+ break;\r
+ case 0x08:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 88.2 KHz.\n");\r
+ break;\r
+ case 0x0a:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 96 KHz.\n\n");\r
+ break;\r
+ case 0x0c:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 176.4 KHz.\n");\r
+ break;\r
+ case 0x0e:\r
+ hdmi_dbg(&client->dev, " Audio Fs = 192 KHz.\n");\r
+ hdmi_dbg(&client->dev, "192 KHz.\n");\r
+ break;\r
+ default :\r
+ hdmi_dbg(&client->dev, " Audio Fs = Wrong Fs output.\n");\r
+ hdmi_dbg(&client->dev, "Wrong Fs output.\n");\r
+ break;\r
+ }\r
+\r
+ if (ANX7150_HDCP_enable == 1)\r
+ hdmi_dbg(&client->dev, " ANX7150_HDCP_Enable.\n");\r
+ else\r
+ hdmi_dbg(&client->dev, " ANX7150_HDCP_Disable.\n");\r
+\r
+ }\r
+ hdmi_dbg(&client->dev, "\n********************************************************************************\n\n");\r
+}\r
+void ANX7150_HDCP_Process(struct i2c_client *client, int enable)\r
+{\r
+ int rc = 0;\r
+ char c,i;\r
+ //u8 c1;\r
+ u8 Bksv_valid=0;//wen HDCP CTS\r
+\r
+ if (ANX7150_HDCP_enable)\r
+ { //HDCP_EN =1 means to do HDCP authentication,SWITCH4 = 0 means not to do HDCP authentication.\r
+\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c | 0x04);//power on HDCP, 090630\r
+\r
+ //ANX7150_i2c_read_p0_reg(ANX7150_INTR2_MASK_REG, &c);\r
+ //ANX7150_i2c_write_p0_reg(ANX7150_INTR2_MASK_REG, c |0x03);\r
+ mdelay(10);//let unencrypted video play a while, required by HDCP CTS. SY//wen HDCP CTS\r
+ anx7150_set_avmute(client);//before auth, set_avmute//wen\r
+ mdelay(10);//wen HDCP CTS\r
+\r
+ if ( !ANX7150_hdcp_init_done )\r
+ {\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ c |= ANX7150_SYS_CTRL1_HDCPMODE;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
+ if (ANX7150_edid_result.is_HDMI)\r
+ rc = anx7150_hardware_hdcp_auth_init(client);\r
+ else\r
+ { //DVI, disable 1.1 feature and enable HDCP two special point check\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
+ c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
+ }\r
+\r
+ //wen HDCP CTS\r
+ if (!anx7150_bksv_srm(client))\r
+ {\r
+ anx7150_blue_screen_enable(client);\r
+ anx7150_clear_avmute(client);\r
+ Bksv_valid=0;\r
+ return;\r
+ }\r
+ else //SY.\r
+ {\r
+ Bksv_valid=1;\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c |= 0x03;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ }\r
+\r
+ ANX7150_hdcp_init_done = 1;\r
+//wen HDCP CTS\r
+ }\r
+\r
+\r
+//wen HDCP CTS\r
+ if ((Bksv_valid) && (!ANX7150_hdcp_auth_en))\r
+ {\r
+ hdmi_dbg(&client->dev, "enable hw hdcp\n");\r
+ anx7150_rst_ddcchannel(client);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c |= ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ ANX7150_hdcp_auth_en = 1;\r
+ }\r
+\r
+ if ((Bksv_valid) && (ANX7150_hdcp_wait_100ms_needed))\r
+ {\r
+ ANX7150_hdcp_wait_100ms_needed = 0;\r
+ //disable audio\r
+\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ \r
+ hdmi_dbg(&client->dev, "++++++++ANX7150_hdcp_wait_100ms_needed+++++++++\n");\r
+ mdelay(150); // 100 -> 150\r
+ return;\r
+ }\r
+//wen HDCP CTS\r
+\r
+ if (ANX7150_hdcp_auth_pass) //wen HDCP CTS\r
+ {\r
+ //Clear the SRM_Check_Pass u8, then when reauthentication occurs, firmware can catch it.\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= 0xfc;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+\r
+ //Enable HDCP Hardware encryption\r
+ if (!ANX7150_hdcp_encryption)\r
+ {\r
+ anx7150_hdcp_encryption_enable(client);\r
+ }\r
+ if (ANX7150_send_blue_screen)\r
+ {\r
+ anx7150_blue_screen_disable(client);\r
+ }\r
+ if (ANX7150_avmute_enable)\r
+ {\r
+ anx7150_clear_avmute(client);\r
+ }\r
+\r
+ i = 0;\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
+ while((c&0x04)==0x00)//wait for encryption.\r
+ {\r
+ mdelay(2);\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
+ i++;\r
+ if (i > 10)\r
+ break;\r
+ }\r
+\r
+ //enable audio SY.\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ hdmi_dbg(&client->dev, "@@@@@ HDCP Auth PASSED! @@@@@\n");\r
+\r
+ if (ANX7150_hdcp_bcaps & 0x40) //repeater\r
+ {\r
+ hdmi_dbg(&client->dev, "Find a repeater!\n");\r
+ //actually it is KSVList check. we can't do SRM check due to the lack of SRM file. SY.\r
+ if (!ANX7150_srm_checked)\r
+ {\r
+ if (!anx7150_is_ksvlist_vld(client))\r
+ {\r
+ hdmi_dbg(&client->dev, "ksvlist not good. disable encryption");\r
+ anx7150_hdcp_encryption_disable(client);\r
+ anx7150_blue_screen_enable(client);\r
+ anx7150_clear_avmute(client);\r
+ ANX7150_ksv_srm_pass = 0;\r
+ anx7150_clean_hdcp(client);//SY.\r
+ //remove below will pass 1b-05/1b-06\r
+ //ANX7150_Set_System_State(ANX7150_WAIT_HOTPLUG);//SY.\r
+ return;\r
+ }\r
+ ANX7150_srm_checked=1;\r
+ ANX7150_ksv_srm_pass = 1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hdmi_dbg(&client->dev, "Find a receiver.\n");\r
+ }\r
+ }\r
+ else //wen HDCP CTS\r
+ {\r
+ hdmi_dbg(&client->dev, "##### HDCP Auth FAILED! #####\n");\r
+ //also need to disable HW AUTHEN\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ c &= ~ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
+ ANX7150_hdcp_auth_en = 0;\r
+ //ANX7150_hdcp_init_done = 0;\r
+ //ANX7150_hdcp_wait_100ms_needed = 1; //wen, update 080703\r
+\r
+ if (ANX7150_hdcp_encryption)\r
+ {\r
+ anx7150_hdcp_encryption_disable(client);\r
+ }\r
+ if (!ANX7150_send_blue_screen)\r
+ {\r
+ anx7150_blue_screen_enable(client);\r
+ }\r
+ if (ANX7150_avmute_enable)\r
+ {\r
+ anx7150_clear_avmute(client);\r
+ }\r
+ //disable audio\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ \r
+ return;\r
+ }\r
+\r
+ }\r
+ else //wen HDCP CTS\r
+ {\r
+ hdmi_dbg(&client->dev, "hdcp pin is off.\n");\r
+ if (ANX7150_send_blue_screen)\r
+ {\r
+ anx7150_blue_screen_disable(client);\r
+ }\r
+ if (ANX7150_avmute_enable)\r
+ {\r
+ anx7150_clear_avmute(client);\r
+ }\r
+ //enable audio SY.\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
+ }\r
+\r
+//wen HDCP CTS\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c); //72:07.1 hdmi or dvi mode\r
+ c = c & 0x02;\r
+ if (c == 0x02)\r
+ {\r
+ hdmi_dbg(&client->dev, "end of ANX7150_HDCP_Process(): in HDMI mode.\n");\r
+ }\r
+ else\r
+ {\r
+ hdmi_dbg(&client->dev, "!end of ANX7150_HDCP_Process(): in DVI mode.\n");\r
+ //To-Do: Config to DVI mode.\r
+ }\r
+\r
+ anx7150_show_video_parameter(client);\r
+ if(!enable)\r
+ anx7150_set_avmute(client);\r
+}\r
+\r
+void HDMI_Set_Video_Format(u8 video_format) //CPU set the lowpower mode\r
+{ \r
+ switch (video_format)\r
+ {\r
+ case HDMI_1280x720p_50Hz:\r
+ g_video_format = ANX7150_V1280x720p_50Hz;\r
+ break;\r
+ case HDMI_1280x720p_60Hz:\r
+ g_video_format = ANX7150_V1280x720p_60Hz;\r
+ break;\r
+ case HDMI_720x576p_50Hz_4x3:\r
+ g_video_format = ANX7150_V720x576p_50Hz_4x3;\r
+ break;\r
+ case HDMI_720x576p_50Hz_16x9:\r
+ g_video_format = ANX7150_V720x576p_50Hz_16x9;\r
+ break;\r
+ case HDMI_720x480p_60Hz_4x3:\r
+ g_video_format = ANX7150_V720x480p_60Hz_4x3;\r
+ break;\r
+ case HDMI_720x480p_60Hz_16x9:\r
+ g_video_format = ANX7150_V720x480p_60Hz_16x9;\r
+ break;\r
+ case HDMI_1920x1080p_50Hz:\r
+ g_video_format = ANX7150_V1920x1080p_50Hz;\r
+ break;\r
+ case HDMI_1920x1080p_60Hz:\r
+ g_video_format = ANX7150_V1920x1080p_60Hz;\r
+ break;\r
+ default:\r
+ g_video_format = ANX7150_V1280x720p_50Hz;\r
+ break;\r
+ }\r
+// ANX7150_system_config_done = 0;\r
+}\r
+void HDMI_Set_Audio_Fs( u8 audio_fs) //ANX7150 call this to check lowpower\r
+{\r
+ g_audio_format = audio_fs;\r
+// ANX7150_system_config_done = 0;\r
+}\r
+int ANX7150_PLAYBACK_Process(void)\r
+{\r
+// D("enter\n");\r
+\r
+ if ((s_ANX7150_packet_config.packets_need_config != 0x00) && (ANX7150_edid_result.is_HDMI == 1))\r
+ {\r
+ return 1;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+#ifndef _ANX7150_HW_H\r
+#define _ANX7150_HW_H\r
+\r
+#include <linux/hdmi.h>\r
+\r
+#define EDID_LENGTH 128\r
+struct est_timings {\r
+ u8 t1;\r
+ u8 t2;\r
+ u8 mfg_rsvd;\r
+} __attribute__((packed));\r
+\r
+struct std_timing {\r
+ u8 hsize; /* need to multiply by 8 then add 248 */\r
+ u8 vfreq_aspect;\r
+} __attribute__((packed));\r
+\r
+/* If detailed data is pixel timing */\r
+struct detailed_pixel_timing {\r
+ u8 hactive_lo;\r
+ u8 hblank_lo;\r
+ u8 hactive_hblank_hi;\r
+ u8 vactive_lo;\r
+ u8 vblank_lo;\r
+ u8 vactive_vblank_hi;\r
+ u8 hsync_offset_lo;\r
+ u8 hsync_pulse_width_lo;\r
+ u8 vsync_offset_pulse_width_lo;\r
+ u8 hsync_vsync_offset_pulse_width_hi;\r
+ u8 width_mm_lo;\r
+ u8 height_mm_lo;\r
+ u8 width_height_mm_hi;\r
+ u8 hborder;\r
+ u8 vborder;\r
+ u8 misc;\r
+} __attribute__((packed));\r
+\r
+/* If it's not pixel timing, it'll be one of the below */\r
+struct detailed_data_string {\r
+ u8 str[13];\r
+} __attribute__((packed));\r
+\r
+struct detailed_data_monitor_range {\r
+ u8 min_vfreq;\r
+ u8 max_vfreq;\r
+ u8 min_hfreq_khz;\r
+ u8 max_hfreq_khz;\r
+ u8 pixel_clock_mhz; /* need to multiply by 10 */\r
+ __le16 sec_gtf_toggle; /* A000=use above, 20=use below */\r
+ u8 hfreq_start_khz; /* need to multiply by 2 */\r
+ u8 c; /* need to divide by 2 */\r
+ __le16 m;\r
+ u8 k;\r
+ u8 j; /* need to divide by 2 */\r
+} __attribute__((packed));\r
+\r
+struct detailed_data_wpindex {\r
+ u8 white_yx_lo; /* Lower 2 bits each */\r
+ u8 white_x_hi;\r
+ u8 white_y_hi;\r
+ u8 gamma; /* need to divide by 100 then add 1 */\r
+} __attribute__((packed));\r
+\r
+struct detailed_data_color_point {\r
+ u8 windex1;\r
+ u8 wpindex1[3];\r
+ u8 windex2;\r
+ u8 wpindex2[3];\r
+} __attribute__((packed));\r
+\r
+struct cvt_timing {\r
+ u8 code[3];\r
+} __attribute__((packed));\r
+\r
+struct detailed_non_pixel {\r
+ u8 pad1;\r
+ u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name\r
+ fb=color point data, fa=standard timing data,\r
+ f9=undefined, f8=mfg. reserved */\r
+ u8 pad2;\r
+ union {\r
+ struct detailed_data_string str;\r
+ struct detailed_data_monitor_range range;\r
+ struct detailed_data_wpindex color;\r
+ struct std_timing timings[6];\r
+ struct cvt_timing cvt[4];\r
+ } data;\r
+} __attribute__((packed));\r
+\r
+struct detailed_timing {\r
+ __le16 pixel_clock; /* need to multiply by 10 KHz */\r
+ union {\r
+ struct detailed_pixel_timing pixel_data;\r
+ struct detailed_non_pixel other_data;\r
+ } data;\r
+} __attribute__((packed));\r
+\r
+struct edid {\r
+ u8 header[8];\r
+ /* Vendor & product info */\r
+ u8 mfg_id[2];\r
+ u8 prod_code[2];\r
+ u32 serial; /* FIXME: byte order */\r
+ u8 mfg_week;\r
+ u8 mfg_year;\r
+ /* EDID version */\r
+ u8 version;\r
+ u8 revision;\r
+ /* Display info: */\r
+ u8 input;\r
+ u8 width_cm;\r
+ u8 height_cm;\r
+ u8 gamma;\r
+ u8 features;\r
+ /* Color characteristics */\r
+ u8 red_green_lo;\r
+ u8 black_white_lo;\r
+ u8 red_x;\r
+ u8 red_y;\r
+ u8 green_x;\r
+ u8 green_y;\r
+ u8 blue_x;\r
+ u8 blue_y;\r
+ u8 white_x;\r
+ u8 white_y;\r
+ /* Est. timings and mfg rsvd timings*/\r
+ struct est_timings established_timings;\r
+ /* Standard timings 1-8*/\r
+ struct std_timing standard_timings[8];\r
+ /* Detailing timings 1-4 */\r
+ struct detailed_timing detailed_timings[4];\r
+ /* Number of 128 byte ext. blocks */\r
+ u8 extensions;\r
+ /* Checksum */\r
+ u8 checksum;\r
+} __attribute__((packed));\r
+\r
+extern u8 timer_slot,misc_reset_needed;\r
+extern u8 bist_switch_value_pc,switch_value;\r
+extern u8 switch_value_sw_backup,switch_value_pc_backup;\r
+extern u8 ANX7150_system_state;\r
+extern u8 ANX7150_srm_checked;\r
+extern u8 ANX7150_HDCP_enable;\r
+extern u8 ANX7150_INT_Done;\r
+extern u8 FREQ_MCLK;\r
+//extern u8 int_s1, int_s2, int_s3;\r
+extern u8 HDMI_Mode_Auto_Manual,HDMI_Lowpower_Mode;\r
+\r
+struct anx7150_interrupt_s{\r
+ int hotplug_change;\r
+ int video_format_change;\r
+ int auth_done;\r
+ int auth_state_change;\r
+ int pll_lock_change;\r
+ int rx_sense_change;\r
+ int HDCP_link_change;\r
+ int audio_clk_change;\r
+ int audio_FIFO_overrun;\r
+ int SPDIF_bi_phase_error;\r
+ int SPDIF_error;\r
+};\r
+typedef struct\r
+{\r
+ u8 is_HDMI;\r
+ u8 ycbcr444_supported;\r
+ u8 ycbcr422_supported;\r
+ u8 supported_1080p_60Hz;\r
+ u8 supported_1080p_50Hz;\r
+ u8 supported_1080i_60Hz;\r
+ u8 supported_1080i_50Hz;\r
+ u8 supported_720p_60Hz;\r
+ u8 supported_720p_50Hz;\r
+ u8 supported_576p_50Hz;\r
+ u8 supported_576i_50Hz;\r
+ u8 supported_640x480p_60Hz;\r
+ u8 supported_720x480p_60Hz;\r
+ u8 supported_720x480i_60Hz;\r
+ u8 AudioFormat[10];//MAX audio STD block is 10(0x1f / 3)\r
+ u8 AudioChannel[10];\r
+ u8 AudioFs[10];\r
+ u8 AudioLength[10];\r
+ u8 SpeakerFormat;u8 edid_errcode;}ANX7150_edid_result_4_system;\r
+ extern ANX7150_edid_result_4_system ANX7150_edid_result;\r
+//#define ITU656\r
+//#ifdef ITU656\r
+struct ANX7150_video_timingtype{ //CEA-861C format\r
+ u8 ANX7150_640x480p_60Hz[18];//format 1\r
+ u8 ANX7150_720x480p_60Hz[18];//format 2 & 3\r
+ u8 ANX7150_1280x720p_60Hz[18];//format 4\r
+ u8 ANX7150_1920x1080i_60Hz[18];//format 5\r
+ u8 ANX7150_720x480i_60Hz[18];//format 6 & 7\r
+ u8 ANX7150_1920x1080p_60Hz[18];\r
+ //u8 ANX7150_720x240p_60Hz[18];//format 8 & 9\r
+ //u8 ANX7150_2880x480i_60Hz[18];//format 10 & 11\r
+ //u8 ANX7150_2880x240p_60Hz[18];//format 12 & 13\r
+ //u8 ANX7150_1440x480p_60Hz[18];//format 14 & 15\r
+ //u8 ANX7150_1920x1080p_60Hz[18];//format 16\r
+ u8 ANX7150_720x576p_50Hz[18];//format 17 & 18\r
+ u8 ANX7150_1280x720p_50Hz[18];//format 19\r
+ u8 ANX7150_1920x1080i_50Hz[18];//format 20*/\r
+ u8 ANX7150_720x576i_50Hz[18];//format 21 & 22\r
+ u8 ANX7150_1920x1080p_50Hz[18];\r
+ /* u8 ANX7150_720x288p_50Hz[18];//formats 23 & 24\r
+ u8 ANX7150_2880x576i_50Hz[18];//formats 25 & 26\r
+ u8 ANX7150_2880x288p_50Hz[18];//formats 27 & 28\r
+ u8 ANX7150_1440x576p_50Hz[18];//formats 29 & 30\r
+ u8 ANX7150_1920x1080p_50Hz[18];//format 31\r
+ u8 ANX7150_1920x1080p_24Hz[18];//format 32\r
+ u8 ANX7150_1920x1080p_25Hz[18];//format 33\r
+ u8 ANX7150_1920x1080p_30Hz[18];//format 34*/\r
+};\r
+//#endif\r
+// 8 type of packets are legal, It is possible to sent 6 types in the same time;\r
+// So select 6 types below at most;\r
+// avi_infoframe and audio_infoframe have fixxed address;\r
+// config other selected types of packet to the rest 4 address with no limits.\r
+typedef enum\r
+{\r
+ ANX7150_avi_infoframe,\r
+ ANX7150_audio_infoframe,\r
+ /*ANX7150_spd_infoframe,\r
+ ANX7150_mpeg_infoframe,\r
+ ANX7150_acp_packet,\r
+ ANX7150_isrc1_packet,\r
+ ANX7150_isrc2_packet,\r
+ ANX7150_vendor_infoframe,*/\r
+}packet_type;\r
+\r
+typedef struct\r
+{\r
+ u8 type;\r
+ u8 version;\r
+ u8 length;\r
+ u8 pb_u8[28];\r
+}infoframe_struct;\r
+\r
+typedef struct\r
+{\r
+ u8 packets_need_config; //which infoframe packet is need updated\r
+ infoframe_struct avi_info;\r
+ infoframe_struct audio_info;\r
+ /* for the funture use\r
+ infoframe_struct spd_info;\r
+ infoframe_struct mpeg_info;\r
+ infoframe_struct acp_pkt;\r
+ infoframe_struct isrc1_pkt;\r
+ infoframe_struct isrc2_pkt;\r
+ infoframe_struct vendor_info; */\r
+\r
+} config_packets;\r
+/*\r
+ u8 i2s_format;\r
+\r
+ u8(s) Name Type Default Description\r
+ 7 EXT_VUCP R/W 0x0\r
+ Enable indicator of VUCP u8s extraction from input\r
+ I2S audio stream. 0 = disable; 1 = enable.\r
+ 6:5 MCLK_PHS_CTRL R/W 0x0\r
+ MCLK phase control for audio SPDIF input, which value\r
+ is depended on the value of MCLK frequency set and not great than it.\r
+ 4 Reserved\r
+ 3 SHIFT_CTRL R/W 0x0\r
+ WS to SD shift first u8. 0 = fist u8 shift (Philips Spec); 1 = no shift.\r
+ 2 DIR_CTRL R/W 0x0\r
+ SD data Indian (MSB or LSB first) control. 0 = MSB first; 1 = LSB first.\r
+ 1 WS_POL R/W 0x0\r
+ Word select left/right polarity select. 0 = left polarity\r
+ when works select is low; 1 = left polarity when word select is high.\r
+ 0 JUST_CTRL R/W 0x0\r
+ SD Justification control. 1 = data is right justified;\r
+ 0 = data is left justified.\r
+\r
+*/\r
+/*\r
+ u8 audio_channel\r
+u8(s) Name Type Default Description\r
+5 AUD_SD3_IN R/W 0x0 Set I2S input channel #3 enable. 0 = disable; 1 = enable.\r
+4 AUD_SD2_IN R/W 0x0 Set I2S input channel #2 enable. 0 = disable; 1 = enable.\r
+3 AUD_SD1_IN R/W 0x0 Set I2S input channel #1 enable. 0 = disable; 1 = enable.\r
+2 AUD_SD0_IN R/W 0x0 Set I2S input channel #0 enable. 0 = disable; 1 = enable.\r
+\r
+\r
+*/\r
+/*\r
+ u8 i2s_map0\r
+u8(s) Name Type Default Description\r
+7:6 FIFO3_SEL R/W 0x3 I2S Channel data stream select for audio FIFO 3. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
+5:4 FIFO2_SEL R/W 0x2 I2S Channel data stream select for audio FIFO 2. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
+3:2 FIFO1_SEL R/W 0x1 I2S Channel data stream select for audio FIFO 1. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
+1:0 FIFO0_SEL R/W 0x0 I2S Channel data stream select for audio FIFO 0. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
+\r
+ u8 i2s_map1\r
+u8(s) Name Type Default Description\r
+7 SW3 R/W 0x0 Swap left/right channel on I2S channel 3. 1 = swap; 0 = no swap.\r
+6 SW2 R/W 0x0 Swap left/right channel on I2S channel 2. 1 = swap; 0 = no swap.\r
+5 SW1 R/W 0x0 Swap left/right channel on I2S channel 1. 1 = swap; 0 = no swap.\r
+4 SW0 R/W 0x0 Swap left/right channel on I2S channel 0. 1 = swap; 0 = no swap.\r
+3:1 IN_WORD_LEN R/W 0x5 Input I2S audio word length (corresponding to channel status u8s [35:33]). When IN_WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when IN_WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
+0 IN_WORD_MAX R/W 0x1 Input I2S audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
+*/\r
+/*\r
+ u8 Channel_status1\r
+u8(s) Name Type Default Description\r
+7:6 MODE R/W 0x0 00 = PCM Audio\r
+5:3 PCM_MODE R/W 0x0 000 = 2 audio channels without pre-emphasis;\r
+ 001 = 2 audio channels with 50/15 usec pre-emphasis\r
+2 SW_CPRGT R/W 0x0 0 = software for which copyright is asserted;\r
+ 1 = software for which no copyright is asserted\r
+1 NON_PCM R/W 0x0 0 = audio sample word represents linear PCM samples;\r
+ 1 = audio sample word used for other purposes.\r
+0 PROF_APP R/W 0x0 0 = consumer applications; 1 = professional applications.\r
+\r
+ u8 Channel_status2\r
+u8(s) Name Type Default Description\r
+7:0 CAT_CODE R/W 0x0 Category code (corresponding to channel status u8s [15:8])\r
+\r
+ u8 Channel_status3\r
+u8(s) Name Type Default Description\r
+7:4 CH_NUM R/W 0x0 Channel number (corresponding to channel status u8s [23:20])\r
+3:0 SOURCE_NUM R/W 0x0 Source number (corresponding to channel status u8s [19:16])\r
+\r
+ u8 Channel_status4\r
+u8(s) Name Type Default Description\r
+7:6 CHNL_u81 R/W 0x0 corresponding to channels status u8s [31:30]\r
+5:4 CLK_ACCUR R/W 0x0 Clock accuracy (corresponding to channels status u8s [29:28]). These two u8s define the sampling frequency tolerance. The u8s are set in the transmitter.\r
+3:0 FS_FREQ R/W 0x0 Sampling clock frequency (corresponding to channel status u8s [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
+\r
+ u8 Channel_status5\r
+u8(s) Name Type Default Description\r
+7:4 CHNL_u82 R/W 0x0 corresponding to channels status u8s [39:36]\r
+3:1 WORD_LENGTH R/W 0x5 Audio word length (corresponding to channel status u8s [35:33]). When WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
+0 WORD_MAX R/W 0x1 Audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
+\r
+*/\r
+typedef struct\r
+{\r
+ u8 audio_channel;\r
+ u8 i2s_format;\r
+ u8 i2s_swap;\r
+ u8 Channel_status1;\r
+ u8 Channel_status2;\r
+ u8 Channel_status3;\r
+ u8 Channel_status4;\r
+ u8 Channel_status5;\r
+} i2s_config_struct;\r
+/*\r
+ u8 FS_FREQ;\r
+\r
+ 7:4 FS_FREQ R 0x0\r
+ Sampling clock frequency (corresponding to channel status u8s [27:24]).\r
+ 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz;\r
+ 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
+*/\r
+\r
+typedef struct\r
+{\r
+ u8 one_u8_ctrl;\r
+\r
+} super_audio_config_struct;\r
+\r
+typedef struct\r
+{\r
+ u8 audio_type; // audio type\r
+ // #define ANX7150_i2s_input 0x01\r
+ // #define ANX7150_spdif_input 0x02\r
+ // #define ANX7150_super_audio_input 0x04\r
+\r
+ u8 down_sample; // 0x72:0x50\r
+ // 0x00: 00 no down sample\r
+ // 0x20: 01 2 to 1 down sample\r
+ // 0x60: 11 4 to 1 down sample\r
+ // 0x40: 10 reserved\r
+ u8 audio_layout;//audio layout;\r
+ //0x00, 2-channel\r
+ //0x80, 8-channel\r
+\r
+ i2s_config_struct i2s_config;\r
+ super_audio_config_struct super_audio_config;\r
+\r
+} audio_config_struct;\r
+\r
+/*added by gerard.zhu*/\r
+/*DDC type*/\r
+typedef enum {\r
+ DDC_Hdcp,\r
+ DDC_Edid,\r
+}ANX7150_DDC_Type;\r
+\r
+/*Read DDC status type*/\r
+typedef enum {\r
+ report,\r
+ Judge,\r
+}ANX7150_DDC_Status_Check_Type;\r
+\r
+/*Define DDC address struction*/\r
+typedef struct {\r
+ u8 dev_addr;\r
+ u8 sgmt_addr;\r
+ u8 offset_addr;\r
+}ANX7150_DDC_Addr;\r
+\r
+/*DDC status u8*/\r
+#define DDC_Error_u8 0x07\r
+#define DDC_Occup_u8 0x06\r
+#define DDC_Fifo_Full_u8 0x05\r
+#define DDC_Fifo_Empt_u8 0x04\r
+#define DDC_No_Ack_u8 0x03\r
+#define DDC_Fifo_Rd_u8 0x02\r
+#define DDC_Fifo_Wr_u8 0x01\r
+#define DDC_Progress_u8 0x00\r
+\r
+#define YCbCr422 0x20\r
+#define null 0\r
+#define source_ratio 0x08\r
+\r
+/*DDC Command*/\r
+#define Abort_Current_Operation 0x00\r
+#define Sequential_u8_Read 0x01\r
+#define Sequential_u8_Write 0x02\r
+#define Implicit_Offset_Address_Read 0x3\r
+#define Enhanced_DDC_Sequenital_Read 0x04\r
+#define Clear_DDC_Fifo 0x05\r
+#define I2c_reset 0x06\r
+\r
+/*DDC result*/\r
+#define DDC_NO_Err 0x00\r
+#define DDC_Status_Err 0x01\r
+#define DDC_Data_Addr_Err 0x02\r
+#define DDC_Length_Err 0x03\r
+\r
+/*checksum result*/\r
+#define Edid_Checksum_No_Err 0x00\r
+#define Edid_Checksum_Err 0x01\r
+\r
+/*HDCP device base address*/\r
+#define HDCP_Dev_Addr 0x74\r
+\r
+/*HDCP Bksv offset*/\r
+#define HDCP_Bksv_Offset 0x00\r
+\r
+/*HDCP Bcaps offset*/\r
+#define HDCP_Bcaps_Offset 0x40\r
+\r
+/*HDCP Bstatus offset*/\r
+#define HDCP_Bstatus_offset 0x41\r
+\r
+/*HDCP KSV Fifo offset */\r
+#define HDCP_Ksv_Fifo_Offset 0x43\r
+\r
+/*HDCP bksv data nums*/\r
+#define Bksv_Data_Nums 5\r
+\r
+/*HDCP ksvs data number by defult*/\r
+#define ksvs_data_nums 50\r
+\r
+/*DDC Max u8s*/\r
+#define DDC_Max_Length 1024\r
+\r
+/*DDC fifo depth*/\r
+#define DDC_Fifo_Depth 16\r
+\r
+/*DDC read delay ms*/\r
+#define DDC_Read_Delay 3\r
+\r
+/*DDC Write delay ms*/\r
+#define DDC_Write_Delay 3\r
+/*end*/\r
+\r
+extern u8 ANX7150_parse_edid_done;\r
+extern u8 ANX7150_system_config_done;\r
+extern u8 ANX7150_video_format_config,ANX7150_video_timing_id;\r
+extern u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
+extern u8 ANX7150_ddr_edge;\r
+extern u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
+extern u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
+extern u8 ANX7150_pix_rpt_set_by_sys;\r
+extern u8 ANX7150_RGBorYCbCr;\r
+extern audio_config_struct s_ANX7150_audio_config;\r
+extern config_packets s_ANX7150_packet_config;\r
+\r
+//********************** BIST Enable***********************************\r
+\r
+\r
+#define ddr_falling_edge 1\r
+#define ddr_rising_edge 0\r
+\r
+#define input_pixel_clk_1x_repeatition 0x00\r
+#define input_pixel_clk_2x_repeatition 0x01\r
+#define input_pixel_clk_4x_repeatition 0x03\r
+\r
+//***********************Video Config***********************************\r
+#define ANX7150_RGB_YCrCb444_SepSync 0\r
+#define ANX7150_YCrCb422_SepSync 1\r
+#define ANX7150_YCrCb422_EmbSync 2\r
+#define ANX7150_YCMux422_SepSync_Mode1 3\r
+#define ANX7150_YCMux422_SepSync_Mode2 4\r
+#define ANX7150_YCMux422_EmbSync_Mode1 5\r
+#define ANX7150_YCMux422_EmbSync_Mode2 6\r
+#define ANX7150_RGB_YCrCb444_DDR_SepSync 7\r
+#define ANX7150_RGB_YCrCb444_DDR_EmbSync 8\r
+\r
+#define ANX7150_RGB_YCrCb444_SepSync_No_DE 9\r
+#define ANX7150_YCrCb422_SepSync_No_DE 10\r
+\r
+#define ANX7150_Progressive 0\r
+#define ANX7150_Interlace 0x08\r
+#define ANX7150_Neg_Hsync_pol 0x20\r
+#define ANX7150_Pos_Hsync_pol 0\r
+#define ANX7150_Neg_Vsync_pol 0x40\r
+#define ANX7150_Pos_Vsync_pol 0\r
+\r
+#define ANX7150_V640x480p_60Hz 1\r
+#define ANX7150_V720x480p_60Hz_4x3 2\r
+#define ANX7150_V720x480p_60Hz_16x9 3\r
+#define ANX7150_V1280x720p_60Hz 4\r
+#define ANX7150_V1280x720p_50Hz 19\r
+#define ANX7150_V1920x1080i_60Hz 5\r
+#define ANX7150_V1920x1080p_60Hz 16\r
+#define ANX7150_V1920x1080p_50Hz 31\r
+#define ANX7150_V1920x1080i_50Hz 20\r
+#define ANX7150_V720x480i_60Hz_4x3 6\r
+#define ANX7150_V720x480i_60Hz_16x9 7\r
+#define ANX7150_V720x576i_50Hz_4x3 21\r
+#define ANX7150_V720x576i_50Hz_16x9 22\r
+#define ANX7150_V720x576p_50Hz_4x3 17\r
+#define ANX7150_V720x576p_50Hz_16x9 18\r
+\r
+#define ANX7150_RGB 0x00\r
+#define ANX7150_YCbCr422 0x01\r
+#define ANX7150_YCbCr444 0x02\r
+#define ANX7150_CSC_BT709 1\r
+#define ANX7150_CSC_BT601 0\r
+\r
+#define ANX7150_EMBEDED_BLUE_SCREEN_ENABLE 1\r
+#define ANX7150_HDCP_FAIL_THRESHOLD 10\r
+\r
+#define ANX7150_avi_sel 0x01\r
+#define ANX7150_audio_sel 0x02\r
+#define ANX7150_spd_sel 0x04\r
+#define ANX7150_mpeg_sel 0x08\r
+#define ANX7150_acp_sel 0x10\r
+#define ANX7150_isrc1_sel 0x20\r
+#define ANX7150_isrc2_sel 0x40\r
+#define ANX7150_vendor_sel 0x80\r
+\r
+// audio type\r
+#define ANX7150_i2s_input 0x01\r
+#define ANX7150_spdif_input 0x02\r
+#define ANX7150_super_audio_input 0x04\r
+// freq_mclk\r
+#define ANX7150_mclk_128_Fs 0x00\r
+#define ANX7150_mclk_256_Fs 0x01\r
+#define ANX7150_mclk_384_Fs 0x02\r
+#define ANX7150_mclk_512_Fs 0x03\r
+// thresholds\r
+#define ANX7150_spdif_stable_th 0x03\r
+// fs -> N(ACR)\r
+#define ANX7150_N_32k 0x1000\r
+#define ANX7150_N_44k 0x1880\r
+#define ANX7150_N_88k 0x3100\r
+#define ANX7150_N_176k 0x6200\r
+#define ANX7150_N_48k 0x1800\r
+#define ANX7150_N_96k 0x3000\r
+#define ANX7150_N_192k 0x6000\r
+\r
+#define spdif_error_th 0x0a\r
+\r
+#define Hresolution_1920 1920\r
+#define Vresolution_540 540\r
+#define Vresolution_1080 1080\r
+#define Hresolution_1280 1280\r
+#define Vresolution_720 720\r
+#define Hresolution_640 640\r
+#define Vresolution_480 480\r
+#define Hresolution_720 720\r
+#define Vresolution_240 240\r
+#define Vresolution_576 576\r
+#define Vresolution_288 288\r
+#define Hz_50 50\r
+#define Hz_60 60\r
+#define Interlace_EDID 0\r
+#define Progressive_EDID 1\r
+#define ratio_16_9 1.777778\r
+#define ratio_4_3 1.333333\r
+\r
+#define ANX7150_EDID_BadHeader 0x01\r
+#define ANX7150_EDID_861B_not_supported 0x02\r
+#define ANX7150_EDID_CheckSum_ERR 0x03\r
+#define ANX7150_EDID_No_ExtBlock 0x04\r
+#define ANX7150_EDID_ExtBlock_NotFor_861B 0x05\r
+\r
+#define ANX7150_VND_IDL_REG 0x00\r
+#define ANX7150_VND_IDH_REG 0x01\r
+#define ANX7150_DEV_IDL_REG 0x02\r
+#define ANX7150_DEV_IDH_REG 0x03\r
+#define ANX7150_DEV_REV_REG 0x04\r
+\r
+#define ANX7150_SRST_REG 0x05\r
+#define ANX7150_TX_RST 0x40\r
+#define ANX7150_SRST_VIDCAP_RST 0x20 // u8 position\r
+#define ANX7150_SRST_AFIFO_RST 0x10 // u8 position\r
+#define ANX7150_SRST_HDCP_RST 0x08 // u8 position\r
+#define ANX7150_SRST_VID_FIFO_RST 0x04 // u8 position\r
+#define ANX7150_SRST_AUD_RST 0x02 // u8 position\r
+#define ANX7150_SRST_SW_RST 0x01 // u8 position\r
+\r
+#define ANX7150_SYS_STATE_REG 0x06\r
+#define ANX7150_SYS_STATE_AUD_CLK_DET 0x20 // u8 position\r
+#define ANX7150_SYS_STATE_AVMUTE 0x10 // u8 position\r
+#define ANX7150_SYS_STATE_HP 0x08 // u8 position\r
+#define ANX7150_SYS_STATE_VSYNC 0x04 // u8 position\r
+#define ANX7150_SYS_STATE_CLK_DET 0x02 // u8 position\r
+#define ANX7150_SYS_STATE_RSV_DET 0x01 // u8 position\r
+\r
+#define ANX7150_SYS_CTRL1_REG 0x07\r
+#define ANX7150_SYS_CTRL1_LINKMUTE_EN 0x80 // u8 position\r
+#define ANX7150_SYS_CTRL1_HDCPHPD_RST 0x40 // u8 position\r
+#define ANX7150_SYS_CTRL1_PDINT_SEL 0x20 // u8 position\r
+#define ANX7150_SYS_CTRL1_DDC_FAST 0x10 // u8 position\r
+#define ANX7150_SYS_CTRL1_DDC_SWCTRL 0x08 // u8 position\r
+#define ANX7150_SYS_CTRL1_HDCPMODE 0x04 // u8 position\r
+#define ANX7150_SYS_CTRL1_HDMI 0x02 // u8 position\r
+#define ANX7150_SYS_CTRL1_PWDN_CTRL 0x01 // u8 position\r
+\r
+#define ANX7150_SYS_CTRL2_REG 0x08\r
+#define ANX7150_SYS_CTRL2_DDC_RST 0x08 // u8 position\r
+#define ANX7150_SYS_CTRL2_TMDSBIST_RST 0x04 // u8 position\r
+#define ANX7150_SYS_CTRL2_MISC_RST 0x02 // u8 position\r
+#define ANX7150_SYS_CTRL2_HW_RST 0x01 // u8 position\r
+\r
+#define ANX7150_SYS_CTRL3_REG 0x09\r
+#define ANX7150_SYS_CTRL3_I2C_PWON 0x02\r
+#define ANX7150_SYS_CTRL3_PWON_ALL 0x01\r
+\r
+#define ANX7150_SYS_CTRL4_REG 0x0b\r
+\r
+#define ANX7150_VID_STATUS_REG 0x10\r
+#define ANX7150_VID_STATUS_VID_STABLE 0x20 // u8 position\r
+#define ANX7150_VID_STATUS_EMSYNC_ERR 0x10 // u8 position\r
+#define ANX7150_VID_STATUS_FLD_POL 0x08 // u8 position\r
+#define ANX7150_VID_STATUS_TYPE 0x04 // u8 position\r
+#define ANX7150_VID_STATUS_VSYNC_POL 0x02 // u8 position\r
+#define ANX7150_VID_STATUS_HSYNC_POL 0x01 // u8 position\r
+\r
+#define ANX7150_VID_MODE_REG 0x11\r
+#define ANX7150_VID_MODE_CHKSHARED_EN 0x80 // u8 position\r
+#define ANX7150_VID_MODE_LINKVID_EN 0x40 // u8 position\r
+#define ANX7150_VID_MODE_RANGE_Y2R 0x20 // u8 position\r
+#define ANX7150_VID_MODE_CSPACE_Y2R 0x10 // u8 position\r
+#define ANX7150_VID_MODE_Y2R_SEL 0x08 // u8 position\r
+#define ANX7150_VID_MODE_UPSAMPLE 0x04 // u8 position\r
+\r
+#define ANX7150_VID_CTRL_REG 0x12\r
+#define ANX7150_VID_CTRL_IN_EN 0x10 // u8 position\r
+#define ANX7150_VID_CTRL_YCu8_SEL 0x08 // u8 position\r
+#define ANX7150_VID_CTRL_u8CTRL_EN 0x04 // u8 position\r
+\r
+#define ANX7150_VID_CAPCTRL0_REG 0x13\r
+#define ANX7150_VID_CAPCTRL0_DEGEN_EN 0x80 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_EMSYNC_EN 0x40 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_DEMUX_EN 0x20 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_INV_IDCK 0x10 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_DV_BUSMODE 0x08 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_DDR_EDGE 0x04 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_VIDu8_SWAP 0x02 // u8 position\r
+#define ANX7150_VID_CAPCTRL0_VIDBIST_EN 0x01 // u8 position\r
+\r
+#define ANX7150_VID_CAPCTRL1_REG 0x14\r
+#define ANX7150_VID_CAPCTRL1_FORMAT_SEL 0x80 // u8 position\r
+#define ANX7150_VID_CAPCTRL1_VSYNC_POL 0x40 // u8 position\r
+#define ANX7150_VID_CAPCTRL1_HSYNC_POL 0x20 // u8 position\r
+#define ANX7150_VID_CAPCTRL1_INV_FLDPOL 0x10 // u8 position\r
+#define ANX7150_VID_CAPCTRL1_VID_TYPE 0x08 // u8 position\r
+\r
+#define ANX7150_H_RESL_REG 0x15\r
+#define ANX7150_H_RESH_REG 0x16\r
+#define ANX7150_VID_PIXL_REG 0x17\r
+#define ANX7150_VID_PIXH_REG 0x18\r
+#define ANX7150_H_FRONTPORCHL_REG 0x19\r
+#define ANX7150_H_FRONTPORCHH_REG 0x1A\r
+#define ANX7150_HSYNC_ACT_WIDTHL_REG 0x1B\r
+#define ANX7150_HSYNC_ACT_WIDTHH_REG 0x1C\r
+#define ANX7150_H_BACKPORCHL_REG 0x1D\r
+#define ANX7150_H_BACKPORCHH_REG 0x1E\r
+#define ANX7150_V_RESL_REG 0x1F\r
+#define ANX7150_V_RESH_REG 0x20\r
+#define ANX7150_ACT_LINEL_REG 0x21\r
+#define ANX7150_ACT_LINEH_REG 0x22\r
+#define ANX7150_ACT_LINE2VSYNC_REG 0x23\r
+#define ANX7150_VSYNC_WID_REG 0x24\r
+#define ANX7150_VSYNC_TAIL2VIDLINE_REG 0x25\r
+#define ANX7150_VIDF_HRESL_REG 0x26\r
+#define ANX7150_VIDF_HRESH_REG 0x27\r
+#define ANX7150_VIDF_PIXL_REG 0x28\r
+#define ANX7150_VIDF_PIXH_REG 0x29\r
+#define ANX7150_VIDF_HFORNTPORCHL_REG 0x2A\r
+#define ANX7150_VIDF_HFORNTPORCHH_REG 0x2B\r
+#define ANX7150_VIDF_HSYNCWIDL_REG 0x2C\r
+#define ANX7150_VIDF_HSYNCWIDH_REG 0x2D\r
+#define ANX7150_VIDF_HBACKPORCHL_REG 0x2E\r
+#define ANX7150_VIDF_HBACKPORCHH_REG 0x2F\r
+#define ANX7150_VIDF_VRESL_REG 0x30\r
+#define ANX7150_VIDF_VRESH_REG 0x31\r
+#define ANX7150_VIDF_ACTVIDLINEL_REG 0x32\r
+#define ANX7150_VIDF_ACTVIDLINEH_REG 0x33\r
+#define ANX7150_VIDF_ACTLINE2VSYNC_REG 0x34\r
+#define ANX7150_VIDF_VSYNCWIDLINE_REG 0x35\r
+#define ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG 0x36\r
+\r
+//Video input data u8 control registers\r
+\r
+#define VID_u8_CTRL0 0x37 //added\r
+#define VID_u8_CTRL1 0x38\r
+#define VID_u8_CTRL2 0x39\r
+#define VID_u8_CTRL3 0x3A\r
+#define VID_u8_CTRL4 0x3B\r
+#define VID_u8_CTRL5 0x3C\r
+#define VID_u8_CTRL6 0x3D\r
+#define VID_u8_CTRL7 0x3E\r
+#define VID_u8_CTRL8 0x3F\r
+#define VID_u8_CTRL9 0x48\r
+#define VID_u8_CTRL10 0x49\r
+#define VID_u8_CTRL11 0x4A\r
+#define VID_u8_CTRL12 0x4B\r
+#define VID_u8_CTRL13 0x4C\r
+#define VID_u8_CTRL14 0x4D\r
+#define VID_u8_CTRL15 0x4E\r
+#define VID_u8_CTRL16 0x4F\r
+#define VID_u8_CTRL17 0x89\r
+#define VID_u8_CTRL18 0x8A\r
+#define VID_u8_CTRL19 0x8B\r
+#define VID_u8_CTRL20 0x8C\r
+#define VID_u8_CTRL21 0x8D\r
+#define VID_u8_CTRL22 0x8E\r
+#define VID_u8_CTRL23 0x8F\r
+\r
+\r
+#define ANX7150_INTR_STATE_REG 0x40\r
+\r
+#define ANX7150_INTR_CTRL_REG 0x41\r
+\r
+#define ANX7150_INTR_CTRL_SOFT_INTR 0x04 // u8 position\r
+#define ANX7150_INTR_CTRL_TYPE 0x02 // u8 position\r
+#define ANX7150_INTR_CTRL_POL 0x01 // u8 position\r
+\r
+#define ANX7150_INTR1_STATUS_REG 0x42\r
+#define ANX7150_INTR1_STATUS_CTS_CHG 0x80 // u8 position\r
+#define ANX7150_INTR1_STATUS_AFIFO_UNDER 0x40 // u8 position\r
+#define ANX7150_INTR1_STATUS_AFIFO_OVER 0x20 // u8 position\r
+#define ANX7150_INTR1_STATUS_SPDIF_ERR 0x10 // u8 position\r
+#define ANX7150_INTR1_STATUS_SW_INT 0x08 // u8 position\r
+#define ANX7150_INTR1_STATUS_HP_CHG 0x04 // u8 position\r
+#define ANX7150_INTR1_STATUS_CTS_OVRWR 0x02 // u8 position\r
+#define ANX7150_INTR1_STATUS_CLK_CHG 0x01 // u8 position\r
+\r
+#define ANX7150_INTR2_STATUS_REG 0x43\r
+#define ANX7150_INTR2_STATUS_ENCEN_CHG 0x80 // u8 position\r
+#define ANX7150_INTR2_STATUS_HDCPLINK_CHK 0x40 // u8 position\r
+#define ANX7150_INTR2_STATUS_HDCPENHC_CHK 0x20 // u8 position\r
+#define ANX7150_INTR2_STATUS_BKSV_RDY 0x10 // u8 position\r
+#define ANX7150_INTR2_STATUS_PLLLOCK_CHG 0x08 // u8 position\r
+#define ANX7150_INTR2_STATUS_SHA_DONE 0x04 // u8 position\r
+#define ANX7150_INTR2_STATUS_AUTH_CHG 0x02 // u8 position\r
+#define ANX7150_INTR2_STATUS_AUTH_DONE 0x01 // u8 position\r
+\r
+#define ANX7150_INTR3_STATUS_REG 0x44\r
+#define ANX7150_INTR3_STATUS_SPDIFBI_ERR 0x80 // u8 position\r
+#define ANX7150_INTR3_STATUS_VIDF_CHG 0x40 // u8 position\r
+#define ANX7150_INTR3_STATUS_AUDCLK_CHG 0x20 // u8 position\r
+#define ANX7150_INTR3_STATUS_DDCACC_ERR 0x10 // u8 position\r
+#define ANX7150_INTR3_STATUS_DDC_NOACK 0x08 // u8 position\r
+#define ANX7150_INTR3_STATUS_VSYNC_DET 0x04 // u8 position\r
+#define ANX7150_INTR3_STATUS_RXSEN_CHG 0x02 // u8 position\r
+#define ANX7150_INTR3_STATUS_SPDIF_UNSTBL 0x01 // u8 position\r
+\r
+#define ANX7150_INTR1_MASK_REG 0x45\r
+#define ANX7150_INTR2_MASK_REG 0x46\r
+#define ANX7150_INTR3_MASK_REG 0x47\r
+\r
+#define ANX7150_HDMI_AUDCTRL0_REG 0x50\r
+#define ANX7150_HDMI_AUDCTRL0_LAYOUT 0x80 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL0_DOWN_SMPL 0x60 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL0_CTSGEN_SC 0x10 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL0_INV_AUDCLK 0x08 // u8 position\r
+\r
+#define ANX7150_HDMI_AUDCTRL1_REG 0x51\r
+#define ANX7150_HDMI_AUDCTRL1_IN_EN 0x80 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN 0x40 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_SD3IN_EN 0x20 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_SD2IN_EN 0x10 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_SD1IN_EN 0x08 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_SD0IN_EN 0x04 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_SPDIFFS_OVRWR 0x02 // u8 position\r
+#define ANX7150_HDMI_AUDCTRL1_CLK_SEL 0x01 // u8 position\r
+\r
+#define ANX7150_I2S_CTRL_REG 0x52\r
+#define ANX7150_I2S_CTRL_VUCP 0x80 // u8 position\r
+#define SPDIF_IN_SEL 0x10 //0-spdif, 1-multi with sd0\r
+#define ANX7150_I2S_CTRL_SHIFT_CTRL 0x08 // u8 position\r
+#define ANX7150_I2S_CTRL_DIR_CTRL 0x04 // u8 position\r
+#define ANX7150_I2S_CTRL_WS_POL 0x02 // u8 position\r
+#define ANX7150_I2S_CTRL_JUST_CTRL 0x01 // u8 position\r
+\r
+#define ANX7150_I2SCH_CTRL_REG 0x53\r
+#define ANX7150_I2SCH_FIFO3_SEL 0xC0 // u8 position\r
+#define ANX7150_I2SCH_FIFO2_SEL 0x30 // u8 position\r
+#define ANX7150_I2SCH_FIFO1_SEL 0x0C // u8 position\r
+#define ANX7150_I2SCH_FIFO0_SEL 0x03 // u8 position\r
+\r
+#define ANX7150_I2SCH_SWCTRL_REG 0x54\r
+\r
+#define ANX7150_I2SCH_SWCTRL_SW3 0x80 // u8 position\r
+#define ANX7150_I2SCH_SWCTRL_SW2 0x40 // u8 position\r
+#define ANX7150_I2SCH_SWCTRL_SW1 0x20 // u8 position\r
+#define ANX7150_I2SCH_SWCTRL_SW0 0x10 // u8 position\r
+#define ANX7150_I2SCH_SWCTRL_INWD_LEN 0xE0 // u8 position\r
+#define ANX7150_I2SCH_SWCTRL_INWD_MAX 0x01 // u8 position\r
+\r
+#define ANX7150_SPDIFCH_STATUS_REG 0x55\r
+#define ANX7150_SPDIFCH_STATUS_FS_FREG 0xF0 // u8 position\r
+#define ANX7150_SPDIFCH_STATUS_WD_LEN 0x0E // u8 position\r
+#define ANX7150_SPDIFCH_STATUS_WD_MX 0x01 // u8 position\r
+\r
+#define ANX7150_I2SCH_STATUS1_REG 0x56\r
+#define ANX7150_I2SCH_STATUS1_MODE 0xC0 // u8 position\r
+#define ANX7150_I2SCH_STATUS1_PCM_MODE 0x38 // u8 position\r
+#define ANX7150_I2SCH_STATUS1_SW_CPRGT 0x04 // u8 position\r
+#define ANX7150_I2SCH_STATUS1_NON_PCM 0x02 // u8 position\r
+#define ANX7150_I2SCH_STATUS1_PROF_APP 0x01 // u8 position\r
+\r
+#define ANX7150_I2SCH_STATUS2_REG 0x57\r
+\r
+#define ANX7150_I2SCH_STATUS3_REG 0x58\r
+#define ANX7150_I2SCH_STATUS3_CH_NUM 0xF0 // u8 position\r
+#define ANX7150_I2SCH_STATUS3_SRC_NUM 0x0F // u8 position\r
+\r
+\r
+\r
+#define ANX7150_I2SCH_STATUS4_REG 0x59\r
+\r
+#define ANX7150_I2SCH_STATUS5_REG 0x5A\r
+\r
+#define ANX7150_I2SCH_STATUS5_WORD_MAX 0x01 // u8 position\r
+\r
+#define ANX7150_HDMI_AUDSTATUS_REG 0x5B\r
+\r
+#define ANX7150_HDMI_AUDSTATUS_SPDIF_DET 0x01 // u8 position\r
+\r
+#define ANX7150_HDMI_AUDBIST_CTRL_REG 0x5C\r
+\r
+#define ANX7150_HDMI_AUDBIST_EN3 0x08 // u8 position\r
+#define ANX7150_HDMI_AUDBIST_EN2 0x04 // u8 position\r
+#define ANX7150_HDMI_AUDBIST_EN1 0x02 // u8 position\r
+#define ANX7150_HDMI_AUDBIST_EN0 0x01 // u8 position\r
+\r
+#define ANX7150_AUD_INCLK_CNT_REG 0x5D\r
+#define ANX7150_AUD_DEBUG_STATUS_REG 0x5E\r
+\r
+#define ANX7150_ONEu8_AUD_CTRL_REG 0x60\r
+\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN7 0x80 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN6 0x40 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN5 0x20 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN4 0x10 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN3 0x08 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN2 0x04 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN1 0x02 // u8 position\r
+#define ANX7150_ONEu8_AUD_CTRL_SEN0 0x01 // u8 position\r
+\r
+#define ANX7150_ONEu8_AUD0_CTRL_REG 0x61\r
+#define ANX7150_ONEu8_AUD1_CTRL_REG 0x62\r
+#define ANX7150_ONEu8_AUD2_CTRL_REG 0x63\r
+#define ANX7150_ONEu8_AUD3_CTRL_REG 0x64\r
+\r
+#define ANX7150_ONEu8_AUDCLK_CTRL_REG 0x65\r
+\r
+#define ANX7150_ONEu8_AUDCLK_DET 0x08 // u8 position\r
+\r
+#define ANX7150_SPDIF_ERR_THRSHLD_REG 0x66\r
+#define ANX7150_SPDIF_ERR_CNT_REG 0x67\r
+\r
+#define ANX7150_HDMI_LINK_CTRL_REG 0x70\r
+\r
+#define ANX7150_HDMI_LINK_DATA_MUTEEN1 0x80 // u8 position\r
+#define ANX7150_HDMI_LINK_DATA_MUTEEN0 0x40 // u8 position\r
+#define ANX7150_HDMI_LINK_CLK_MUTEEN2 0x20 // u8 position\r
+#define ANX7150_HDMI_LINK_CLK_MUTEEN1 0x10 // u8 position\r
+#define ANX7150_HDMI_LINK_CLK_MUTEEN0 0x08 // u8 position\r
+#define ANX7150_HDMI_LINK_DEC_DE 0x04 // u8 position\r
+#define ANX7150_HDMI_LINK_PRMB_INC 0x02 // u8 position\r
+#define ANX7150_HDMI_LINK_AUTO_PROG 0x01 // u8 position\r
+\r
+#define ANX7150_VID_CAPCTRL2_REG 0x71\r
+\r
+#define ANX7150_VID_CAPCTRL2_CHK_UPDATEEN 0x10 // u8 position\r
+\r
+#define ANX7150_LINK_MUTEEE_REG 0x72\r
+\r
+#define ANX7150_LINK_MUTEEE_AVMUTE_EN2 0x20 // u8 position\r
+#define ANX7150_LINK_MUTEEE_AVMUTE_EN1 0x10 // u8 position\r
+#define ANX7150_LINK_MUTEEE_AVMUTE_EN0 0x08 // u8 position\r
+#define ANX7150_LINK_MUTEEE_AUDMUTE_EN2 0x04 // u8 position\r
+#define ANX7150_LINK_MUTEEE_AUDMUTE_EN1 0x02 // u8 position\r
+#define ANX7150_LINK_MUTEEE_AUDMUTE_EN0 0x01 // u8 position\r
+\r
+#define ANX7150_SERDES_TEST0_REG 0x73\r
+#define ANX7150_SERDES_TEST1_REG 0x74\r
+#define ANX7150_SERDES_TEST2_REG 0x75\r
+\r
+#define ANX7150_PLL_TX_AMP 0x76\r
+\r
+\r
+#define ANX7150_DDC_SLV_ADDR_REG 0x80\r
+#define ANX7150_DDC_SLV_SEGADDR_REG 0x81\r
+#define ANX7150_DDC_SLV_OFFADDR_REG 0x82\r
+#define ANX7150_DDC_ACC_CMD_REG 0x83\r
+#define ANX7150_DDC_ACCNUM0_REG 0x84\r
+#define ANX7150_DDC_ACCNUM1_REG 0x85\r
+\r
+#define ANX7150_DDC_CHSTATUS_REG 0x86\r
+\r
+#define ANX7150_DDC_CHSTATUS_DDCERR 0x80 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_DDC_OCCUPY 0x40 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_FIFO_FULL 0x20 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_FIFO_EMPT 0x10 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_NOACK 0x08 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_FIFO_RD 0x04 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_FIFO_WR 0x02 // u8 position\r
+#define ANX7150_DDC_CHSTATUS_INPRO 0x01 // u8 position\r
+\r
+#define ANX7150_DDC_FIFO_ACC_REG 0x87\r
+#define ANX7150_DDC_FIFOCNT_REG 0x88\r
+\r
+#define ANX7150_SYS_PD_REG 0x90\r
+#define ANX7150_SYS_PD_PLL 0x80 // u8 position\r
+#define ANX7150_SYS_PD_TMDS 0x40 // u8 position\r
+#define ANX7150_SYS_PD_TMDS_CLK 0x20 // u8 position\r
+#define ANX7150_SYS_PD_MISC 0x10 // u8 position\r
+#define ANX7150_SYS_PD_LINK 0x08 // u8 position\r
+#define ANX7150_SYS_PD_IDCK 0x04 // u8 position\r
+#define ANX7150_SYS_PD_AUD 0x02 // u8 position\r
+#define ANX7150_SYS_PD_MACRO_ALL 0x01 // u8 position\r
+\r
+#define ANX7150_LINKFSM_DEBUG0_REG 0x91\r
+#define ANX7150_LINKFSM_DEBUG1_REG 0x92\r
+\r
+#define ANX7150_PLL_CTRL0_REG 0x93\r
+#define ANX7150_PLL_CTRL0_CPREG_BLEED 0x02 // u8 position\r
+#define ANX7150_PLL_CTRL0_TEST_EN 0x01 // u8 position\r
+\r
+#define ANX7150_PLL_CTRL1_REG 0x94\r
+#define ANX7150_PLL_CTRL1_TESTEN 0x80 // u8 position\r
+\r
+#define ANX7150_OSC_CTRL_REG 0x95\r
+#define ANX7150_OSC_CTRL_TESTEN 0x80 // u8 position\r
+#define ANX7150_OSC_CTRL_SEL_BG 0x40 // u8 position\r
+\r
+#define ANX7150_TMDS_CH0_CONFIG_REG 0x96\r
+#define ANX7150_TMDS_CH0_TESTEN 0x20 // u8 position\r
+#define ANX7150_TMDS_CH0_AMP 0x1C // u8 position\r
+#define ANX7150_TMDS_CHO_EMP 0x03 // u8 position\r
+\r
+#define ANX7150_TMDS_CH1_CONFIG_REG 0x97\r
+#define ANX7150_TMDS_CH1_TESTEN 0x20 // u8 position\r
+#define ANX7150_TMDS_CH1_AMP 0x1C // u8 position\r
+#define ANX7150_TMDS_CH1_EMP 0x03 // u8 position\r
+\r
+#define ANX7150_TMDS_CH2_CONFIG_REG 0x98\r
+#define ANX7150_TMDS_CH2_TESTEN 0x20 // u8 position\r
+#define ANX7150_TMDS_CH2_AMP 0x1C // u8 position\r
+#define ANX7150_TMDS_CH2_EMP 0x03 // u8 position\r
+\r
+#define ANX7150_TMDS_CLKCH_CONFIG_REG 0x99\r
+#define ANX7150_TMDS_CLKCH_MUTE 0x80 // u8 position\r
+#define ANX7150_TMDS_CLKCH_TESTEN 0x08 // u8 position\r
+#define ANX7150_TMDS_CLKCH_AMP 0x07 // u8 position\r
+\r
+#define ANX7150_CHIP_CTRL_REG 0x9A\r
+#define ANX7150_CHIP_CTRL_PRBS_GENEN 0x80 // u8 position\r
+#define ANX7150_CHIP_CTRL_LINK_DBGSEL 0x70 // u8 position\r
+#define ANX7150_CHIP_CTRL_VIDCHK_EN 0x08 // u8 position\r
+#define ANX7150_CHIP_CTRL_MISC_TIMER 0x04 // u8 position\r
+#define ANX7150_CHIP_CTRL_PLL_RNG 0x02 // u8 position\r
+#define ANX7150_CHIP_CTRL_PLL_MAN 0x01 // u8 position\r
+\r
+#define ANX7150_CHIP_STATUS_REG 0x9B\r
+#define ANX7150_CHIP_STATUS_GPIO 0x80 // u8 position\r
+#define ANX7150_CHIP_STATUS_SDA 0x40 // u8 position\r
+#define ANX7150_CHIP_STATUS_SCL 0x20 // u8 position\r
+#define ANX7150_CHIP_STATUS_PLL_HSPO 0x04 // u8 position\r
+#define ANX7150_CHIP_STATUS_PLL_LOCK 0x02 // u8 position\r
+#define ANX7150_CHIP_STATUS_MISC_LOCK 0x01 // u8 position\r
+\r
+#define ANX7150_DBG_PINGPIO_CTRL_REG 0x9C\r
+#define ANX7150_DBG_PINGPIO_VDLOW_SHAREDEN 0x04 // u8 position\r
+#define ANX7150_DBG_PINGPIO_GPIO_ADDREN 0x02 // u8 position\r
+#define ANX7150_DBG_PINGPIO_GPIO_OUT 0x01 // u8 position\r
+\r
+#define ANX7150_CHIP_DEBUG0_CTRL_REG 0x9D\r
+#define ANX7150_CHIP_DEBUG0_PRBS_ERR 0xE0 // u8 position\r
+#define ANX7150_CHIP_DEBUG0_CAPST 0x1F // u8 position\r
+\r
+#define ANX7150_CHIP_DEBUG1_CTRL_REG 0x9E\r
+#define ANX7150_CHIP_DEBUG1_SDA_SW 0x80 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_SCL_SW 0x40 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_SERDES_TESTEN 0x20 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_CLK_BYPASS 0x10 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_FORCE_PLLLOCK 0x08 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_PLLLOCK_BYPASS 0x04 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_FORCE_HP 0x02 // u8 position\r
+#define ANX7150_CHIP_DEBUG1_HP_DEGLITCH 0x01 // u8 position\r
+\r
+#define ANX7150_CHIP_DEBUG2_CTRL_REG 0x9F\r
+#define ANX7150_CHIP_DEBUG2_EXEMB_SYNCEN 0x04 // u8 position\r
+#define ANX7150_CHIP_DEBUG2_VIDBIST 0x02 // u8 position\r
+\r
+#define ANX7150_VID_INCLK_REG 0x5F\r
+\r
+#define ANX7150_HDCP_STATUS_REG 0xA0\r
+#define ANX7150_HDCP_STATUS_ADV_CIPHER 0x80 // u8 position\r
+#define ANX7150_HDCP_STATUS_R0_READY 0x10 // u8 position\r
+#define ANX7150_HDCP_STATUS_AKSV_ACT 0x08 // u8 position\r
+#define ANX7150_HDCP_STATUS_ENCRYPT 0x04 // u8 position\r
+#define ANX7150_HDCP_STATUS_AUTH_PASS 0x02 // u8 position\r
+#define ANX7150_HDCP_STATUS_KEY_DONE 0x01 // u8 position\r
+\r
+#define ANX7150_HDCP_CTRL0_REG 0xA1\r
+#define ANX7150_HDCP_CTRL0_STORE_AN 0x80 // u8 position\r
+#define ANX7150_HDCP_CTRL0_RX_REP 0x40 // u8 position\r
+#define ANX7150_HDCP_CTRL0_RE_AUTH 0x20 // u8 position\r
+#define ANX7150_HDCP_CTRL0_SW_AUTHOK 0x10 // u8 position\r
+#define ANX7150_HDCP_CTRL0_HW_AUTHEN 0x08 // u8 position\r
+#define ANX7150_HDCP_CTRL0_ENC_EN 0x04 // u8 position\r
+#define ANX7150_HDCP_CTRL0_BKSV_SRM 0x02 // u8 position\r
+#define ANX7150_HDCP_CTRL0_KSV_VLD 0x01 // u8 position\r
+\r
+#define ANX7150_HDCP_CTRL1_REG 0xA2\r
+#define ANX7150_LINK_CHK_12_EN 0x40\r
+#define ANX7150_HDCP_CTRL1_DDC_NOSTOP 0x20 // u8 position\r
+#define ANX7150_HDCP_CTRL1_DDC_NOACK 0x10 // u8 position\r
+#define ANX7150_HDCP_CTRL1_EDDC_NOACK 0x08 // u8 position\r
+#define ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN 0x04 // u8 position\r
+#define ANX7150_HDCP_CTRL1_RCV11_EN 0x02 // u8 position\r
+#define ANX7150_HDCP_CTRL1_HDCP11_EN 0x01 // u8 position\r
+\r
+#define ANX7150_HDCP_Link_Check_FRAME_NUM_REG 0xA3\r
+#define ANX7150_HDCP_AKSV1_REG 0xA5\r
+#define ANX7150_HDCP_AKSV2_REG 0xA6\r
+#define ANX7150_HDCP_AKSV3_REG 0xA7\r
+#define ANX7150_HDCP_AKSV4_REG 0xA8\r
+#define ANX7150_HDCP_AKSV5_REG 0xA9\r
+\r
+#define ANX7150_HDCP_AN1_REG 0xAA\r
+#define ANX7150_HDCP_AN2_REG 0xAB\r
+#define ANX7150_HDCP_AN3_REG 0xAC\r
+#define ANX7150_HDCP_AN4_REG 0xAD\r
+#define ANX7150_HDCP_AN5_REG 0xAE\r
+#define ANX7150_HDCP_AN6_REG 0xAF\r
+#define ANX7150_HDCP_AN7_REG 0xB0\r
+#define ANX7150_HDCP_AN8_REG 0xB1\r
+\r
+#define ANX7150_HDCP_BKSV1_REG 0xB2\r
+#define ANX7150_HDCP_BKSV2_REG 0xB3\r
+#define ANX7150_HDCP_BKSV3_REG 0xB4\r
+#define ANX7150_HDCP_BKSV4_REG 0xB5\r
+#define ANX7150_HDCP_BKSV5_REG 0xB6\r
+\r
+#define ANX7150_HDCP_RI1_REG 0xB7\r
+#define ANX7150_HDCP_RI2_REG 0xB8\r
+\r
+#define ANX7150_HDCP_PJ_REG 0xB9\r
+#define ANX7150_HDCP_RX_CAPS_REG 0xBA\r
+#define ANX7150_HDCP_BSTATUS0_REG 0xBB\r
+#define ANX7150_HDCP_BSTATUS1_REG 0xBC\r
+\r
+#define ANX7150_HDCP_AMO0_REG 0xD0\r
+#define ANX7150_HDCP_AMO1_REG 0xD1\r
+#define ANX7150_HDCP_AMO2_REG 0xD2\r
+#define ANX7150_HDCP_AMO3_REG 0xD3\r
+#define ANX7150_HDCP_AMO4_REG 0xD4\r
+#define ANX7150_HDCP_AMO5_REG 0xD5\r
+#define ANX7150_HDCP_AMO6_REG 0xD6\r
+#define ANX7150_HDCP_AMO7_REG 0xD7\r
+\r
+#define ANX7150_HDCP_DBG_CTRL_REG 0xBD\r
+\r
+#define ANX7150_HDCP_DBG_ENC_INC 0x08 // u8 position\r
+#define ANX7150_HDCP_DBG_DDC_SPEED 0x06 // u8 position\r
+#define ANX7150_HDCP_DBG_SKIP_RPT 0x01 // u8 position\r
+\r
+#define ANX7150_HDCP_KEY_STATUS_REG 0xBE\r
+#define ANX7150_HDCP_KEY_BIST_EN 0x04 // u8 position\r
+#define ANX7150_HDCP_KEY_BIST_ERR 0x02 // u8 position\r
+#define ANX7150_HDCP_KEY_CMD_DONE 0x01 // u8 position\r
+\r
+#define ANX7150_KEY_CMD_REGISTER 0xBF //added\r
+\r
+#define ANX7150_HDCP_AUTHDBG_STATUS_REG 0xC7\r
+#define ANX7150_HDCP_ENCRYPTDBG_STATUS_REG 0xC8\r
+#define ANX7150_HDCP_FRAME_NUM_REG 0xC9\r
+\r
+#define ANX7150_DDC_MSTR_INTER_REG 0xCA\r
+#define ANX7150_DDC_MSTR_LINK_REG 0xCB\r
+\r
+#define ANX7150_HDCP_BLUESCREEN0_REG 0xCC\r
+#define ANX7150_HDCP_BLUESCREEN1_REG 0xCD\r
+#define ANX7150_HDCP_BLUESCREEN2_REG 0xCE\r
+// DEV_ADDR = 0x7A or 0x7E\r
+#define ANX7150_INFO_PKTCTRL1_REG 0xC0\r
+#define ANX7150_INFO_PKTCTRL1_SPD_RPT 0x80 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_SPD_EN 0x40 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_AVI_RPT 0x20 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_AVI_EN 0x10 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_GCP_RPT 0x08 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_GCP_EN 0x04 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_ACR_NEW 0x02 // u8 position\r
+#define ANX7150_INFO_PKTCTRL1_ACR_EN 0x01 // u8 position\r
+\r
+#define ANX7150_INFO_PKTCTRL2_REG 0xC1\r
+#define ANX7150_INFO_PKTCTRL2_UD1_RPT 0x80 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_UD1_EN 0x40 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_UD0_RPT 0x20 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_UD0_EN 0x10 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_MPEG_RPT 0x08 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_MPEG_EN 0x04 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_AIF_RPT 0x02 // u8 position\r
+#define ANX7150_INFO_PKTCTRL2_AIF_EN 0x01 // u8 position\r
+\r
+#define ANX7150_ACR_N1_SW_REG 0xC2\r
+#define ANX7150_ACR_N2_SW_REG 0xC3\r
+#define ANX7150_ACR_N3_SW_REG 0xC4\r
+\r
+#define ANX7150_ACR_CTS1_SW_REG 0xC5\r
+#define ANX7150_ACR_CTS2_SW_REG 0xC6\r
+#define ANX7150_ACR_CTS3_SW_REG 0xC7\r
+\r
+#define ANX7150_ACR_CTS1_HW_REG 0xC8\r
+#define ANX7150_ACR_CTS2_HW_REG 0xC9\r
+#define ANX7150_ACR_CTS3_HW_REG 0xCA\r
+\r
+#define ANX7150_ACR_CTS_CTRL_REG 0xCB\r
+\r
+#define ANX7150_GNRL_CTRL_PKT_REG 0xCC\r
+#define ANX7150_GNRL_CTRL_CLR_AVMUTE 0x02 // u8 position\r
+#define ANX7150_GNRL_CTRL_SET_AVMUTE 0x01 // u8 position\r
+\r
+#define ANX7150_AUD_PKT_FLATCTRL_REG 0xCD\r
+#define ANX7150_AUD_PKT_AUTOFLAT_EN 0x80 // u8 position\r
+#define ANX7150_AUD_PKT_FLAT 0x07 // u8 position\r
+\r
+\r
+//select video hardware interface\r
+#define ANX7150_VID_HW_INTERFACE 0x03//0x00:RGB and YcbCr 4:4:4 Formats with Separate Syncs (24-bpp mode)\r
+ //0x01:YCbCr 4:2:2 Formats with Separate Syncs(16-bbp)\r
+ //0x02:YCbCr 4:2:2 Formats with Embedded Syncs(No HS/VS/DE)\r
+ //0x03:YC Mux 4:2:2 Formats with Separate Sync Mode1(u815:8 and u8 3:0 are used)\r
+ //0x04:YC Mux 4:2:2 Formats with Separate Sync Mode2(u811:0 are used)\r
+ //0x05:YC Mux 4:2:2 Formats with Embedded Sync Mode1(u815:8 and u8 3:0 are used)\r
+ //0x06:YC Mux 4:2:2 Formats with Embedded Sync Mode2(u811:0 are used)\r
+ //0x07:RGB and YcbCr 4:4:4 DDR Formats with Separate Syncs\r
+ //0x08:RGB and YcbCr 4:4:4 DDR Formats with Embedded Syncs\r
+ //0x09:RGB and YcbCr 4:4:4 Formats with Separate Syncs but no DE\r
+ //0x0a:YCbCr 4:2:2 Formats with Separate Syncs but no DE\r
+//select input color space\r
+#define ANX7150_INPUT_COLORSPACE 0x01//0x00: input color space is RGB\r
+ //0x01: input color space is YCbCr422\r
+ //0x02: input color space is YCbCr444\r
+//select input pixel clock edge for DDR mode\r
+#define ANX7150_IDCK_EDGE_DDR 0x00 //0x00:use rising edge to latch even numbered pixel data//jack wen\r
+ //0x01:use falling edge to latch even numbered pixel data\r
+\r
+//select audio hardware interface\r
+#define ANX7150_AUD_HW_INTERFACE 0x01//0x01:audio input comes from I2S\r
+ //0x02:audio input comes from SPDIF\r
+ //0x04:audio input comes from one u8 audio\r
+//select MCLK and Fs relationship if audio HW interface is I2S\r
+#define ANX7150_MCLK_Fs_RELATION 0x01//0x00:MCLK = 128 * Fs\r
+ //0x01:MCLK = 256 * Fs\r
+ //0x02:MCLK = 384 * Fs\r
+ //0x03:MCLK = 512 * Fs //wen updated error\r
+\r
+#define ANX7150_AUD_CLK_EDGE 0x00 //0x00:use MCLK and SCK rising edge to latch audio data\r
+ //0x08, revised by wen. //0x80:use MCLK and SCK falling edge to latch audio data\r
+//select I2S channel numbers if audio HW interface is I2S\r
+#define ANX7150_I2S_CH0_ENABLE 0x01 //0x01:enable channel 0 input; 0x00: disable\r
+#define ANX7150_I2S_CH1_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
+#define ANX7150_I2S_CH2_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
+#define ANX7150_I2S_CH3_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
+//select I2S word length if audio HW interface is I2S\r
+#define ANX7150_I2S_WORD_LENGTH 0x0b\r
+ //0x02 = 16u8s; 0x04 = 18 u8s; 0x08 = 19 u8s; 0x0a = 20 u8s(maximal word length is 20u8s); 0x0c = 17 u8s;\r
+ // 0x03 = 20u8s(maximal word length is 24u8s); 0x05 = 22 u8s; 0x09 = 23 u8s; 0x0b = 24 u8s; 0x0d = 21 u8s;\r
+\r
+//select I2S format if audio HW interface is I2S\r
+#define ANX7150_I2S_SHIFT_CTRL 0x00//0x00: fist u8 shift(philips spec)\r
+ //0x01:no shift\r
+#define ANX7150_I2S_DIR_CTRL 0x00//0x00:SD data MSB first\r
+ //0x01:LSB first\r
+#define ANX7150_I2S_WS_POL 0x00//0x00:left polarity when word select is low\r
+ //0x01:left polarity when word select is high\r
+#define ANX7150_I2S_JUST_CTRL 0x00//0x00:data is left justified\r
+ //0x01:data is right justified\r
+\r
+#define EDID_Parse_Enable 1 // cwz 0 for test, 1 normal\r
+//InfoFrame and Control Packet Registers\r
+// 0x7A or 0X7E\r
+/*\r
+#define AVI_HB0 0x00\r
+#define AVI_HB1 0x01\r
+#define AVI_HB2 0x02\r
+#define AVI_PB0 0x03\r
+#define AVI_PB1 0x04\r
+#define AVI_PB2 0x05\r
+#define AVI_PB3 0x06\r
+#define AVI_PB4 0x07\r
+#define AVI_PB5 0x08\r
+#define AVI_PB6 0x09\r
+#define AVI_PB7 0x0A\r
+#define AVI_PB8 0x0B\r
+#define AVI_PB9 0x0C\r
+#define AVI_PB10 0x0D\r
+#define AVI_PB11 0x0E\r
+#define AVI_PB12 0x0F\r
+#define AVI_PB13 0x10\r
+#define AVI_PB14 0x11\r
+#define AVI_PB15 0x12\r
+\r
+#define AUD_HBO 0x20\r
+#define AUD_HB1 0x21\r
+#define AUD_HB2 0x22\r
+#define AUD_PB0 0x23\r
+#define AUD_PB1 0x24\r
+#define AUD_PB2 0x25\r
+#define AUD_PB3 0x26\r
+#define AUD_PB4 0x27\r
+#define AUD_PB5 0x28\r
+#define AUD_PB6 0x29\r
+#define AUD_PB7 0x2A\r
+#define AUD_PB8 0x2B\r
+#define AUD_PB9 0x2C\r
+#define AUD_PB10 0x2D\r
+\r
+#define SPD_HBO 0x40\r
+#define SPD_HB1 0x41\r
+#define SPD_HB2 0x42\r
+#define SPD_PB0 0x43\r
+#define SPD_PB1 0x44\r
+#define SPD_PB2 0x45\r
+#define SPD_PB3 0x46\r
+#define SPD_PB4 0x47\r
+#define SPD_PB5 0x48\r
+#define SPD_PB6 0x49\r
+#define SPD_PB7 0x4A\r
+#define SPD_PB8 0x4B\r
+#define SPD_PB9 0x4C\r
+#define SPD_PB10 0x4D\r
+#define SPD_PB11 0x4E\r
+#define SPD_PB12 0x4F\r
+#define SPD_PB13 0x50\r
+#define SPD_PB14 0x51\r
+#define SPD_PB15 0x52\r
+#define SPD_PB16 0x53\r
+#define SPD_PB17 0x54\r
+#define SPD_PB18 0x55\r
+#define SPD_PB19 0x56\r
+#define SPD_PB20 0x57\r
+#define SPD_PB21 0x58\r
+#define SPD_PB22 0x59\r
+#define SPD_PB23 0x5A\r
+#define SPD_PB24 0x5B\r
+#define SPD_PB25 0x5C\r
+#define SPD_PB26 0x5D\r
+#define SPD_PB27 0x5E\r
+\r
+#define MPEG_HBO 0x60\r
+#define MPEG_HB1 0x61\r
+#define MPEG_HB2 0x62\r
+#define MPEG_PB0 0x63\r
+#define MPEG_PB1 0x64\r
+#define MPEG_PB2 0x65\r
+#define MPEG_PB3 0x66\r
+#define MPEG_PB4 0x67\r
+#define MPEG_PB5 0x68\r
+#define MPEG_PB6 0x69\r
+#define MPEG_PB7 0x6A\r
+#define MPEG_PB8 0x6B\r
+#define MPEG_PB9 0x6C\r
+#define MPEG_PB10 0x6D\r
+#define MPEG_PB11 0x6E\r
+#define MPEG_PB12 0x6F\r
+#define MPEG_PB13 0x70\r
+#define MPEG_PB14 0x71\r
+#define MPEG_PB15 0x72\r
+#define MPEG_PB16 0x73\r
+#define MPEG_PB17 0x74\r
+#define MPEG_PB18 0x75\r
+#define MPEG_PB19 0x76\r
+#define MPEG_PB20 0x77\r
+#define MPEG_PB21 0x78\r
+#define MPEG_PB22 0x79\r
+#define MPEG_PB23 0x7A\r
+#define MPEG_PB24 0x7B\r
+#define MPEG_PB25 0x7C\r
+#define MPEG_PB26 0x7D\r
+#define MPEG_PB27 0x7E\r
+\r
+#define USRDF0_HBO 0x80\r
+#define USRDF0_HB1 0x81\r
+#define USRDF0_HB2 0x82\r
+#define USRDF0_PB0 0x83\r
+#define USRDF0_PB1 0x84\r
+#define USRDF0_PB2 0x85\r
+#define USRDF0_PB3 0x86\r
+#define USRDF0_PB4 0x87\r
+#define USRDF0_PB5 0x88\r
+#define USRDF0_PB6 0x89\r
+#define USRDF0_PB7 0x8A\r
+#define USRDF0_PB8 0x8B\r
+#define USRDF0_PB9 0x8C\r
+#define USRDF0_PB10 0x8D\r
+#define USRDF0_PB11 0x8E\r
+#define USRDF0_PB12 0x8F\r
+#define USRDF0_PB13 0x90\r
+#define USRDF0_PB14 0x91\r
+#define USRDF0_PB15 0x92\r
+#define USRDF0_PB16 0x93\r
+#define USRDF0_PB17 0x94\r
+#define USRDF0_PB18 0x95\r
+#define USRDF0_PB19 0x96\r
+#define USRDF0_PB20 0x97\r
+#define USRDF0_PB21 0x98\r
+#define USRDF0_PB22 0x99\r
+#define USRDF0_PB23 0x9A\r
+#define USRDF0_PB24 0x9B\r
+#define USRDF0_PB25 0x9C\r
+#define USRDF0_PB26 0x9D\r
+#define USRDF0_PB27 0x9E\r
+\r
+#define USRDF1_HBO 0xA0\r
+#define USRDF1_HB1 0xA1\r
+#define USRDF1_HB2 0xA2\r
+#define USRDF1_PB0 0xA3\r
+#define USRDF1_PB1 0xA4\r
+#define USRDF1_PB2 0xA5\r
+#define USRDF1_PB3 0xA6\r
+#define USRDF1_PB4 0xA7\r
+#define USRDF1_PB5 0xA8\r
+#define USRDF1_PB6 0xA9\r
+#define USRDF1_PB7 0xAA\r
+#define USRDF1_PB8 0xAB\r
+#define USRDF1_PB9 0xAC\r
+#define USRDF1_PB10 0xAD\r
+#define USRDF1_PB11 0xAE\r
+#define USRDF1_PB12 0xAF\r
+#define USRDF1_PB13 0xB0\r
+#define USRDF1_PB14 0xB1\r
+#define USRDF1_PB15 0xB2\r
+#define USRDF1_PB16 0xB3\r
+#define USRDF1_PB17 0xB4\r
+#define USRDF1_PB18 0xB5\r
+#define USRDF1_PB19 0xB6\r
+#define USRDF1_PB20 0xB7\r
+#define USRDF1_PB21 0xB8\r
+#define USRDF1_PB22 0xB9\r
+#define USRDF1_PB23 0xBA\r
+#define USRDF1_PB24 0xBB\r
+#define USRDF1_PB25 0xBC\r
+#define USRDF1_PB26 0xBD\r
+#define USRDF1_PB27 0xBE\r
+*/\r
+ int anx7150_get_hpd(struct i2c_client *client);\r
+\r
+void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF);\r
+int anx7150_detect_device(struct anx7150_pdata *anx);\r
+u8 ANX7150_Get_System_State(void);\r
+int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state);\r
+int anx7150_unplug(struct i2c_client *client);\r
+int anx7150_plug(struct i2c_client *client);\r
+int ANX7150_API_Initial(struct i2c_client *client);\r
+void ANX7150_Shutdown(struct i2c_client *client);\r
+int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev);\r
+int ANX7150_GET_SENSE_STATE(struct i2c_client *client);\r
+int ANX7150_Get_Optimal_resolution(int resolution_set);\r
+void HDMI_Set_Video_Format(u8 video_format);\r
+void HDMI_Set_Audio_Fs( u8 audio_fs);\r
+void ANX7150_API_System_Config(void);\r
+u8 ANX7150_Config_Audio(struct i2c_client *client);\r
+u8 ANX7150_Config_Packet(struct i2c_client *client);\r
+void ANX7150_HDCP_Process(struct i2c_client *client,int enable);\r
+int ANX7150_PLAYBACK_Process(void);\r
+void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state);\r
+int ANX7150_Config_Video(struct i2c_client *client);\r
+int ANX7150_GET_RECIVER_TYPE(void);\r
+void HDMI_Set_Video_Format(u8 video_format);\r
+void HDMI_Set_Audio_Fs( u8 audio_fs);\r
+int ANX7150_PLAYBACK_Process(void);\r
+int ANX7150_Blue_Screen(struct anx7150_pdata *anx);\r
+int anx7150_set_avmute(struct i2c_client *client);\r
+int anx7150_initial(struct i2c_client *client);\r
+\r
+#endif\r
--- /dev/null
+#include <linux/hdmi.h>
+
+extern void rk29_backlight_set(bool on);
+void hdmi_set_backlight(int on)
+{
+ rk29_backlight_set(on);
+}
--- /dev/null
+#include <linux/hdmi.h>
+extern void codec_set_spk(bool on);
+
+void hdmi_set_spk(int on)
+{
+ codec_set_spk(on);
+}
--- /dev/null
+#include <linux/kernel.h>\r
+#include <linux/delay.h>\r
+#include <linux/module.h>\r
+#include <linux/err.h>\r
+\r
+#include <linux/hdmi.h>\r
+#include <linux/input.h>\r
+\r
+\r
+struct class *hdmi_class;\r
+struct hdmi_id_ref_info {\r
+ struct hdmi *hdmi;\r
+ int id;\r
+ int ref;\r
+}ref_info[HDMI_MAX_ID];\r
+#ifdef CONFIG_SYSFS\r
+\r
+extern int hdmi_create_attrs(struct hdmi *hdmi);\r
+extern void hdmi_remove_attrs(struct hdmi *hdmi);\r
+\r
+#else\r
+\r
+static inline int hdmi_create_attrs(struct hdmi *hdmi)\r
+{ return 0; }\r
+static inline void hdmi_remove_attrs(struct hdmi *hdmi) {}\r
+\r
+#endif /* CONFIG_SYSFS */\r
+static void __hdmi_changed(struct hdmi *hdmi)\r
+{\r
+ int precent;\r
+ \r
+ mutex_lock(&hdmi->lock);\r
+ precent = hdmi->ops->hdmi_precent(hdmi);\r
+\r
+ if(precent && hdmi->mode == DISP_ON_LCD && hdmi->display_on){\r
+ if(hdmi->ops->insert(hdmi) == 0){\r
+ hdmi->mode = DISP_ON_HDMI;\r
+ kobject_uevent(&hdmi->dev->kobj, KOBJ_CHANGE);\r
+ }\r
+ else\r
+ hdmi_dbg(hdmi->dev, "insert error\n");\r
+ }\r
+ else if((!precent || !hdmi->display_on) && hdmi->mode == DISP_ON_HDMI){\r
+ if(hdmi->ops->remove(hdmi) == 0){\r
+ hdmi->mode = DISP_ON_LCD;\r
+ kobject_uevent(&hdmi->dev->kobj, KOBJ_CHANGE);\r
+ }\r
+ else\r
+ hdmi_dbg(hdmi->dev, "remove error\n");\r
+ }\r
+ mutex_unlock(&hdmi->lock);\r
+ return;\r
+}\r
+\r
+void hdmi_changed(struct hdmi *hdmi, int msec)\r
+{ \r
+ schedule_delayed_work(&hdmi->work, msecs_to_jiffies(msec));\r
+ return;\r
+}\r
+void hdmi_suspend(struct hdmi *hdmi)\r
+{\r
+ del_timer(&hdmi->timer);\r
+ flush_delayed_work(&hdmi->work);\r
+ if(hdmi->mode == DISP_ON_HDMI){\r
+ hdmi->ops->remove(hdmi);\r
+ hdmi->mode = DISP_ON_LCD;\r
+ }\r
+ return;\r
+}\r
+void hdmi_resume(struct hdmi *hdmi)\r
+{\r
+ mod_timer(&hdmi->timer, jiffies + msecs_to_jiffies(10));\r
+ return;\r
+}\r
+\r
+static void hdmi_changed_work(struct work_struct *work)\r
+{\r
+ struct hdmi *hdmi = container_of(work, struct hdmi,\r
+ work.work);\r
+ \r
+ __hdmi_changed(hdmi);\r
+ return;\r
+}\r
+\r
+void *hdmi_priv(struct hdmi *hdmi)\r
+{\r
+ return (void *)hdmi->priv;\r
+}\r
+static void hdmi_detect_timer(unsigned long data)\r
+{\r
+ struct hdmi *hdmi = (struct hdmi*)data;\r
+ \r
+ int precent = hdmi->ops->hdmi_precent(hdmi);\r
+\r
+ if((precent && hdmi->mode == DISP_ON_LCD) ||\r
+ (!precent && hdmi->mode == DISP_ON_HDMI))\r
+ hdmi_changed(hdmi, 100);\r
+ mod_timer(&hdmi->timer, jiffies + msecs_to_jiffies(200));\r
+}\r
+struct hdmi *hdmi_register(int extra, struct device *parent)\r
+{\r
+ int rc = 0, i;\r
+ char name[8];\r
+ struct hdmi *hdmi = kzalloc(sizeof(struct hdmi)+ extra, GFP_KERNEL);\r
+\r
+ if(!hdmi)\r
+ return NULL;\r
+ for(i = 0; i < HDMI_MAX_ID; i++) \r
+ {\r
+ if(ref_info[i].ref == 0)\r
+ {\r
+ ref_info[i].ref = 1;\r
+ hdmi->id = i;\r
+ break;\r
+ }\r
+ }\r
+ if(i == HDMI_MAX_ID)\r
+ {\r
+ kfree(hdmi);\r
+ return NULL;\r
+ }\r
+ sprintf(name, "hdmi-%d", hdmi->id);\r
+ \r
+ hdmi->dev = device_create(hdmi_class, parent, 0,\r
+ "%s", name);\r
+ if (IS_ERR(hdmi->dev)) {\r
+ rc = PTR_ERR(hdmi->dev);\r
+ goto dev_create_failed;\r
+ }\r
+\r
+ dev_set_drvdata(hdmi->dev, hdmi);\r
+ ref_info[i].hdmi = hdmi;\r
+\r
+ INIT_DELAYED_WORK(&hdmi->work, hdmi_changed_work);\r
+\r
+ rc = hdmi_create_attrs(hdmi);\r
+ if (rc)\r
+ goto create_attrs_failed;\r
+\r
+ goto success;\r
+\r
+create_attrs_failed:\r
+ device_unregister(hdmi->dev);\r
+dev_create_failed:\r
+ hdmi_remove_attrs(hdmi);\r
+ kfree(hdmi);\r
+ return NULL;\r
+success:\r
+ mutex_init(&hdmi->lock);\r
+ setup_timer(&hdmi->timer, hdmi_detect_timer,(unsigned long)hdmi);\r
+ mod_timer(&hdmi->timer, jiffies + msecs_to_jiffies(200));\r
+ return hdmi;\r
+}\r
+void hdmi_unregister(struct hdmi *hdmi)\r
+{\r
+ int id;\r
+\r
+ if(!hdmi)\r
+ return;\r
+ id = hdmi->id;\r
+ flush_scheduled_work();\r
+ hdmi_remove_attrs(hdmi);\r
+ device_unregister(hdmi->dev);\r
+\r
+ kfree(hdmi);\r
+ hdmi = NULL;\r
+ ref_info[id].ref = 0;\r
+ ref_info[id].hdmi = NULL;\r
+}\r
+struct hdmi *get_hdmi_struct(int nr)\r
+{\r
+ if(ref_info[nr].ref == 0)\r
+ return NULL;\r
+ else\r
+ return ref_info[nr].hdmi;\r
+}\r
+int hdmi_is_insert(void)\r
+{\r
+ struct hdmi *hdmi = get_hdmi_struct(0);\r
+\r
+ if(hdmi && hdmi->ops && hdmi->ops->hdmi_precent)\r
+ return hdmi->ops->hdmi_precent(hdmi);\r
+ else\r
+ return 0;\r
+}\r
+int hdmi_get_scale(void)\r
+{\r
+ struct hdmi* hdmi = get_hdmi_struct(0);\r
+ if(!hdmi)\r
+ return 100;\r
+ else\r
+ return hdmi->scale;\r
+}\r
+\r
+int hdmi_set_scale(int event, char *data, int len)\r
+{\r
+ int result;\r
+ struct hdmi* hdmi = get_hdmi_struct(0);\r
+\r
+ if(!hdmi)\r
+ return -1;\r
+ if(len != 4)\r
+ return -1;\r
+ if(fb_get_video_mode() || hdmi->mode == DISP_ON_LCD)\r
+ return -1;\r
+\r
+ result = data[0] | data[1]<<1 | data[2]<<2;\r
+ if(event != MOUSE_NONE && (result & event) != event)\r
+ return -1;\r
+\r
+ hdmi->scale += data[3];\r
+ \r
+ hdmi->scale = (hdmi->scale>100)?100:hdmi->scale;\r
+ hdmi->scale = (hdmi->scale<MIN_SCALE)?MIN_SCALE:hdmi->scale;\r
+ return 0; \r
+}\r
+\r
+static int __init hdmi_class_init(void)\r
+{\r
+ int i;\r
+ \r
+ hdmi_class = class_create(THIS_MODULE, "hdmi");\r
+\r
+ if (IS_ERR(hdmi_class))\r
+ return PTR_ERR(hdmi_class);\r
+ for(i = 0; i < HDMI_MAX_ID; i++) {\r
+ ref_info[i].id = i;\r
+ ref_info[i].ref = 0;\r
+ ref_info[i].hdmi = NULL;\r
+ }\r
+ return 0;\r
+}\r
+\r
+static void __exit hdmi_class_exit(void)\r
+{\r
+ class_destroy(hdmi_class);\r
+}\r
+EXPORT_SYMBOL(hdmi_changed);\r
+EXPORT_SYMBOL(hdmi_register);\r
+EXPORT_SYMBOL(hdmi_unregister);\r
+EXPORT_SYMBOL(get_hdmi_struct);\r
+\r
+subsys_initcall(hdmi_class_init);\r
+module_exit(hdmi_class_exit);\r
+\r
--- /dev/null
+#include <linux/console.h>
+#include <linux/fb.h>
+
+#include <linux/completion.h>
+#include "../display/screen/screen.h"
+#include <linux/hdmi.h>
+#include "../rk29_fb.h"
+
+
+/* Base */
+#define LCD_ACLK 500000000// 312000000
+
+#define OUT_TYPE SCREEN_HDMI
+#define OUT_FACE OUT_P888
+#define DCLK_POL 1
+#define SWAP_RB 0
+
+
+/* 720p@50Hz Timing */
+#define OUT_CLK0 74250000
+#define H_PW0 40
+#define H_BP0 220
+#define H_VD0 1280
+#define H_FP0 440
+#define V_PW0 5
+#define V_BP0 20
+#define V_VD0 720
+#define V_FP0 5
+
+/* 720p@60Hz Timing */
+#define OUT_CLK1 74250000
+#define H_PW1 40
+#define H_BP1 220
+#define H_VD1 1280
+#define H_FP1 110
+#define V_PW1 5
+#define V_BP1 20
+#define V_VD1 720
+#define V_FP1 5
+
+/* 576p@50Hz Timing */
+#define OUT_CLK2 27000000
+#define H_PW2 64
+#define H_BP2 68
+#define H_VD2 720
+#define H_FP2 12
+#define V_PW2 5
+#define V_BP2 39
+#define V_VD2 576
+#define V_FP2 5
+
+/* 720x480p@60Hz Timing */
+#define OUT_CLK3 27000000
+#define H_PW3 62
+#define H_BP3 60
+#define H_VD3 720
+#define H_FP3 16
+#define V_PW3 5
+#define V_BP3 35
+#define V_VD3 480
+#define V_FP3 5
+
+/* 1080p@50Hz Timing */
+#define OUT_CLK5 148500000
+#define H_PW4 44
+#define H_BP4 148
+#define H_VD4 1920
+#define H_FP4 528
+#define V_PW4 5
+#define V_BP4 35
+#define V_VD4 1080
+#define V_FP4 5
+
+/* 1080p@60Hz Timing */
+#define OUT_CLK4 148500000
+#define H_PW5 44
+#define H_BP5 148
+#define H_VD5 1920
+#define H_FP5 88
+#define V_PW5 5
+#define V_BP5 35
+#define V_VD5 1080
+#define V_FP5 5
+
+
+extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable );
+
+static int anx7150_init(void)
+{
+ return 0;
+}
+
+static int anx7150_standby(u8 enable)
+{
+ return 0;
+}
+
+
+struct rk29fb_screen hdmi_info[] = {
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD0,
+ .y_res = V_VD0,
+ .pixclock = OUT_CLK0,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP0,
+ .right_margin = H_FP0,
+ .hsync_len = H_PW0,
+ .upper_margin = V_BP0,
+ .lower_margin = V_FP0,
+ .vsync_len = V_PW0,
+ .pin_hsync = 1,
+ .pin_vsync = 1,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_1280x720p_50Hz
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD1,
+ .y_res = V_VD1,
+ .pixclock = OUT_CLK1,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP1,
+ .right_margin = H_FP1,
+ .hsync_len = H_PW1,
+ .upper_margin = V_BP1,
+ .lower_margin = V_FP1,
+ .vsync_len = V_PW1,
+ .pin_hsync = 1,
+ .pin_vsync = 1,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_1280x720p_60Hz
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD2,
+ .y_res = V_VD2,
+ .pixclock = OUT_CLK2,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP2,
+ .right_margin = H_FP2,
+ .hsync_len = H_PW2,
+ .upper_margin = V_BP2,
+ .lower_margin = V_FP2,
+ .vsync_len = V_PW2,
+ .pin_hsync = 0,
+ .pin_vsync = 0,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_720x576p_50Hz_4x3
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD2,
+ .y_res = V_VD2,
+ .pixclock = OUT_CLK2,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP2,
+ .right_margin = H_FP2,
+ .hsync_len = H_PW2,
+ .upper_margin = V_BP2,
+ .lower_margin = V_FP2,
+ .vsync_len = V_PW2,
+ .pin_hsync = 0,
+ .pin_vsync = 0,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_720x576p_50Hz_16x9
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD3,
+ .y_res = V_VD3,
+ .pixclock = OUT_CLK3,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP3,
+ .right_margin = H_FP3,
+ .hsync_len = H_PW3,
+ .upper_margin = V_BP3,
+ .lower_margin = V_FP3,
+ .vsync_len = V_PW3,
+ .pin_hsync = 0,
+ .pin_vsync = 0,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_720x480p_60Hz_4x3
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD3,
+ .y_res = V_VD3,
+ .pixclock = OUT_CLK3,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP3,
+ .right_margin = H_FP3,
+ .hsync_len = H_PW3,
+ .upper_margin = V_BP3,
+ .lower_margin = V_FP3,
+ .vsync_len = V_PW3,
+ .pin_hsync = 0,
+ .pin_vsync = 0,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_720x480p_60Hz_16x9
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD4,
+ .y_res = V_VD4,
+ .pixclock = OUT_CLK4,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP4,
+ .right_margin = H_FP4,
+ .hsync_len = H_PW4,
+ .upper_margin = V_BP4,
+ .lower_margin = V_FP4,
+ .vsync_len = V_PW4,
+ .pin_hsync = 0,
+ .pin_vsync = 0,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_1920x1080p_50Hz
+ {
+ .type = OUT_TYPE,
+ .face = OUT_FACE,
+ .x_res = H_VD5,
+ .y_res = V_VD5,
+ .pixclock = OUT_CLK5,
+ .lcdc_aclk = LCD_ACLK,
+ .left_margin = H_BP5,
+ .right_margin = H_FP5,
+ .hsync_len = H_PW5,
+ .upper_margin = V_BP5,
+ .lower_margin = V_FP5,
+ .vsync_len = V_PW5,
+ .pin_hsync = 0,
+ .pin_vsync = 0,
+ .pin_den = 0,
+ .pin_dclk = DCLK_POL,
+ .swap_rb = SWAP_RB,
+ .swap_rg = 0,
+ .swap_gb = 0,
+ .swap_delta = 0,
+ .swap_dumy = 0,
+ .init = anx7150_init,
+ .standby = anx7150_standby,
+ }, //HDMI_1920x1080p_60Hz
+};
+
+int hdmi_switch_fb(struct hdmi *hdmi, int type)
+{
+ int rc = 0;
+
+ switch(hdmi->resolution)
+ {
+ case HDMI_1280x720p_50Hz:
+ rc = FB_Switch_Screen(&hdmi_info[0], type);
+ break;
+ case HDMI_1280x720p_60Hz:
+ rc = FB_Switch_Screen(&hdmi_info[1], type);
+ break;
+ case HDMI_720x576p_50Hz_4x3:
+ rc = FB_Switch_Screen(&hdmi_info[2], type);
+ break;
+ case HDMI_720x576p_50Hz_16x9:
+ rc = FB_Switch_Screen(&hdmi_info[3], type);
+ break;
+ case HDMI_720x480p_60Hz_4x3:
+ rc = FB_Switch_Screen(&hdmi_info[4], type);
+ break;
+ case HDMI_720x480p_60Hz_16x9:
+ rc = FB_Switch_Screen(&hdmi_info[5], type);
+ break;
+ case HDMI_1920x1080p_50Hz:
+ rc = FB_Switch_Screen(&hdmi_info[6], type);
+ break;
+ case HDMI_1920x1080p_60Hz:
+ rc = FB_Switch_Screen(&hdmi_info[7], type);
+ break;
+ default:
+ rc = FB_Switch_Screen(&hdmi_info[0], type);
+ break;
+ }
+ if(hdmi->wait == 1) {
+ complete(&hdmi->complete);
+ hdmi->wait = 0;
+ }
+ return rc;
+}
+++ /dev/null
-#
-# Display drivers configuration
-#
-
-source "drivers/video/hdmi/hdmi-new/chips/Kconfig"
+++ /dev/null
-obj-y += hdmi-core.o hdmi-sysfs.o hdmi-fb.o hdmi-codec.o hdmi-backlight.o
-obj-y += chips/
+++ /dev/null
-choice
- prompt "HDMI chips select"
-config ANX7150_NEW
- bool "anx7150"
-config ANX9030_NEW
- bool "anx9030"
-endchoice
+++ /dev/null
-obj-$(CONFIG_ANX7150_NEW) += anx7150_hw.o anx7150.o
-
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/delay.h>\r
-#include <linux/module.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/hdmi-new.h>\r
-#include <linux/i2c.h>\r
-#include <linux/interrupt.h>\r
-#include <mach/gpio.h>\r
-#include <mach/iomux.h>\r
-\r
-\r
-\r
-#include "anx7150.h"\r
-#include "anx7150_hw.h"\r
-\r
-int anx7150_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR0;\r
- return i2c_master_reg8_recv(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-int anx7150_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR0;\r
- return i2c_master_reg8_send(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-int anx7150_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR1;\r
- return i2c_master_reg8_recv(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR1;\r
- return i2c_master_reg8_send(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-\r
-static int anx7150_param_chg(struct anx7150_pdata *anx)\r
-{\r
- int resolution_real;\r
-\r
- hdmi_set_spk(anx->hdmi->display_on);\r
- hdmi_set_backlight(!anx->hdmi->display_on);\r
- hdmi_switch_fb(anx->hdmi, anx->hdmi->display_on);\r
- resolution_real = ANX7150_Get_Optimal_resolution(anx->hdmi->resolution);\r
- HDMI_Set_Video_Format(resolution_real);\r
- HDMI_Set_Audio_Fs(anx->hdmi->audio_fs);\r
- ANX7150_API_HDCP_ONorOFF(anx->hdmi->hdcp_on);\r
- ANX7150_API_System_Config();\r
- ANX7150_Config_Video(anx->client);\r
-\r
- ANX7150_Config_Audio(anx->client);\r
- ANX7150_Config_Packet(anx->client);\r
- ANX7150_HDCP_Process(anx->client, anx->hdmi->display_on);\r
- ANX7150_PLAYBACK_Process();\r
-\r
- return 0;\r
-}\r
-\r
-static int anx7150_insert(struct hdmi *hdmi)\r
-{\r
- int tmo = 10;\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
-\r
- anx7150_plug(anx->client);\r
- if(ANX7150_Parse_EDID(anx->client,&anx->dev) < 0)\r
- {\r
- dev_info(&anx->client->dev, "parse EDID error\n");\r
- anx7150_unplug(anx->client);\r
- return -1;\r
- }\r
- \r
- while(--tmo && ANX7150_GET_SENSE_STATE(anx->client) != 1)\r
- mdelay(10);\r
- if(tmo <= 0)\r
- {\r
- anx7150_unplug(anx->client);\r
- return -1;\r
- }\r
- if(!hdmi->display_on)\r
- return 0;\r
- anx7150_param_chg(anx);\r
- return 0;\r
-}\r
-static int anx7150_remove(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
-\r
- anx7150_unplug(anx->client);\r
- hdmi_set_spk(HDMI_DISABLE);\r
- hdmi_set_backlight(HDMI_ENABLE);\r
- hdmi_switch_fb(hdmi, HDMI_DISABLE);\r
-\r
- return 0;\r
-}\r
-static int anx7150_shutdown(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
- \r
- anx7150_unplug(anx->client);\r
-\r
- return 0;\r
-}\r
-static int anx7150_display_on(struct hdmi* hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
-\r
- hdmi->display_on = HDMI_ENABLE;\r
- hdmi_dbg(hdmi->dev, "hdmi display on\n");\r
- anx7150_param_chg(anx);\r
- return 0;\r
-}\r
-static int anx7150_display_off(struct hdmi* hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
-\r
- hdmi->display_on = HDMI_DISABLE;\r
- anx->dev.hdmi_enable = HDMI_DISABLE;\r
- hdmi_dbg(hdmi->dev, "hdmi display off\n");\r
- anx7150_param_chg(anx);\r
- return 0;\r
-}\r
-static int anx7150_set_param(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
-\r
- anx7150_param_chg(anx);\r
- return 0;\r
-}\r
-\r
-static int anx7150_hdmi_precent(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_priv(hdmi);\r
-\r
- return gpio_get_value(anx->client->irq)?0:1;\r
-}\r
-static struct hdmi_ops anx7150_ops = {\r
- .display_on = anx7150_display_on,\r
- .display_off = anx7150_display_off,\r
- .set_param = anx7150_set_param,\r
- .hdmi_precent = anx7150_hdmi_precent,\r
- .insert = anx7150_insert,\r
- .remove = anx7150_remove,\r
- .shutdown = anx7150_shutdown,\r
-};\r
-static irqreturn_t anx7150_detect_irq(int irq, void *dev_id);\r
-static void anx7150_detect_work(struct work_struct *work)\r
-{\r
- int ret = 0;\r
- struct anx7150_pdata *anx = container_of(work, struct anx7150_pdata, work.work);\r
-\r
- free_irq(anx->irq, anx);\r
- ret = request_irq(anx->irq, anx7150_detect_irq,\r
- anx7150_hdmi_precent(anx->hdmi)? IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING,NULL,anx);\r
- dev_info(&anx->client->dev, "det = %d,hpd_status = %d\n", \r
- gpio_get_value(anx->client->irq), anx7150_get_hpd(anx->client));\r
- anx->is_changed = 1;\r
- if(!anx->is_early_suspend)\r
- hdmi_changed(anx->hdmi, 0);\r
-}\r
-\r
-static irqreturn_t anx7150_detect_irq(int irq, void *dev_id)\r
-{\r
-\r
- struct anx7150_pdata *anx = (struct anx7150_pdata *)dev_id;\r
-\r
- disable_irq_nosync(anx->irq);\r
- schedule_delayed_work(&anx->work, msecs_to_jiffies(200));\r
-\r
- return IRQ_HANDLED;\r
-}\r
-#ifdef CONFIG_HAS_EARLYSUSPEND\r
-static void anx7150_early_suspend(struct early_suspend *h)\r
-{\r
- struct anx7150_pdata *anx = container_of(h,\r
- struct anx7150_pdata,\r
- early_suspend);\r
- dev_info(&anx->client->dev, "anx7150 enter early suspend\n");\r
- anx->is_early_suspend = 1;\r
- flush_delayed_work(&anx->work);\r
- if(anx->hdmi->display_on)\r
- hdmi_suspend(anx->hdmi);\r
-\r
- return;\r
-}\r
-\r
-static void anx7150_early_resume(struct early_suspend *h)\r
-{\r
- int ret = 0;\r
- struct anx7150_pdata *anx = container_of(h,\r
- struct anx7150_pdata,\r
- early_suspend);\r
- dev_info(&anx->client->dev, "anx7150 exit early suspend\n");\r
- anx->is_early_suspend = 0;\r
- if(anx->hdmi->display_on)\r
- ret = hdmi_resume(anx->hdmi);\r
- return;\r
-\r
-}\r
-#endif\r
-\r
-static int anx7150_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)\r
-{\r
- int ret = 0;\r
- struct hdmi *hdmi = NULL;\r
- struct anx7150_pdata *anx = NULL;\r
-\r
- hdmi = hdmi_register(sizeof(struct anx7150_pdata), &client->dev);\r
- if (!hdmi)\r
- {\r
- dev_err(&client->dev, "fail to register hdmi\n");\r
- return -ENOMEM;\r
- }\r
- hdmi->ops = &anx7150_ops;\r
- hdmi->display_on = HDMI_ENABLE;\r
- hdmi->auto_switch = HDMI_DISABLE;\r
- hdmi->hdcp_on = HDMI_DISABLE;\r
- hdmi->audio_fs = HDMI_I2S_DEFAULT_Fs;\r
- hdmi->resolution = HDMI_DEFAULT_RESOLUTION;\r
- \r
- anx = hdmi_priv(hdmi);\r
- anx->hdmi = hdmi;\r
- i2c_set_clientdata(client, anx);\r
- anx->client = client;\r
-\r
- if((ret = gpio_request(client->irq, "hdmi gpio")) < 0)\r
- {\r
- dev_err(&client->dev, "fail to request gpio %d\n", client->irq);\r
- goto err_hdmi_unregister;\r
- }\r
- gpio_pull_updown(client->irq,0);\r
- gpio_direction_input(client->irq);\r
-\r
- anx->irq = gpio_to_irq(client->irq);\r
- INIT_DELAYED_WORK(&anx->work, anx7150_detect_work);\r
- if((ret = request_irq(anx->irq, anx7150_detect_irq,\r
- anx7150_hdmi_precent(hdmi)?IRQF_TRIGGER_RISING:IRQF_TRIGGER_FALLING, NULL, anx)) <0)\r
- {\r
- dev_err(&client->dev, "fail to request hdmi irq\n");\r
- goto err_gpio_free;\r
- }\r
- if(anx7150_detect_device(anx) < 0)\r
- {\r
- dev_err(&client->dev, "anx7150 is not exist\n");\r
- ret = -EIO;\r
- goto err_free_irq;\r
- }\r
-\r
-#ifdef CONFIG_HAS_EARLYSUSPEND\r
- anx->early_suspend.suspend = anx7150_early_suspend;\r
- anx->early_suspend.resume = anx7150_early_resume;\r
- anx->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 1;\r
- register_early_suspend(&anx->early_suspend);\r
-#endif\r
- anx->is_early_suspend = 0;\r
- anx->is_changed = 1;\r
-\r
- hdmi_changed(hdmi, 200);\r
- dev_info(&client->dev, "anx7150 i2c probe ok\n");\r
- return 0;\r
-err_free_irq:\r
- free_irq(anx->irq, anx);\r
-err_gpio_free:\r
- gpio_free(client->irq);\r
-err_hdmi_unregister:\r
- hdmi_unregister(hdmi);\r
- anx = NULL;\r
- return ret;\r
-}\r
-\r
-static int __devexit anx7150_i2c_remove(struct i2c_client *client)\r
-{\r
- struct anx7150_pdata *anx = (struct anx7150_pdata *)i2c_get_clientdata(client);\r
- struct hdmi *hdmi = anx->hdmi;\r
-\r
- free_irq(anx->irq, anx);\r
- gpio_free(client->irq);\r
- hdmi_unregister(hdmi);\r
- anx = NULL;\r
- return 0;\r
-}\r
-#if 0\r
-static int anx7150_i2c_suspend(struct i2c_client *client, pm_message_t mesg)\r
-{\r
- struct anx7150_pdata *anx = (struct anx7150_pdata *)i2c_get_clientdata(client);\r
-\r
- return hdmi_suspend(anx->hdmi);\r
-}\r
-static int anx7150_i2c_resume(struct i2c_client *client)\r
-{\r
- int ret = 0;\r
- struct anx7150_pdata *anx = (struct anx7150_pdata *)i2c_get_clientdata(client);\r
-\r
- ret = hdmi_resume(anx->hdmi);\r
- return ret;\r
-}\r
-#endif\r
-static const struct i2c_device_id anx7150_id[] = {\r
- { "anx7150", 0 },\r
- { }\r
-};\r
-\r
-static struct i2c_driver anx7150_i2c_driver = {\r
- .driver = {\r
- .name = "anx7150",\r
- .owner = THIS_MODULE,\r
- },\r
- .probe = &anx7150_i2c_probe,\r
- .remove = &anx7150_i2c_remove,\r
- //.suspend = &anx7150_i2c_suspend,\r
- //.resume = &anx7150_i2c_resume,\r
- .id_table = anx7150_id,\r
-};\r
-\r
-\r
-static int __init anx7150_init(void)\r
-{\r
- return i2c_add_driver(&anx7150_i2c_driver);\r
-}\r
-\r
-static void __exit anx7150_exit(void)\r
-{\r
- i2c_del_driver(&anx7150_i2c_driver);\r
-}\r
-\r
-//module_init(anx7150_init);\r
-fs_initcall(anx7150_init);\r
-module_exit(anx7150_exit);\r
-\r
-\r
+++ /dev/null
-#ifndef _ANX7150_H\r
-#define _ANX7150_H\r
-\r
-#include <linux/hdmi-new.h>\r
-#include <linux/earlysuspend.h>\r
-\r
-\r
-#define ANX7150_I2C_ADDR0 0X39\r
-#define ANX7150_I2C_ADDR1 0X3d\r
-\r
-#define ANX7150_SCL_RATE 100 * 1000\r
-\r
-\r
-\r
-/* HDMI auto switch */\r
-#define HDMI_AUTO_SWITCH HDMI_ENABLE\r
-\r
-/* HDMI reciver status */\r
-#define HDMI_RECIVER_INACTIVE 0\r
-#define HDMI_RECIVER_ACTIVE 1\r
-\r
-/* ANX7150 reciver HPD Status */\r
-#define HDMI_RECIVER_UNPLUG 0\r
-#define HDMI_RECIVER_PLUG 1\r
-\r
-#define LCD 0\r
-#define HDMI 1\r
-\r
-#define RK29_OUTPUT_STATUS_LCD LCD\r
-#define RK29_OUTPUT_STATUS_HDMI HDMI\r
-\r
-/* HDMI HDCP ENABLE */\r
-#define ANX7150_HDCP_EN HDMI_DISABLE\r
-\r
-/* ANX7150 state machine */\r
-enum{\r
- HDMI_INITIAL = 1,\r
- WAIT_HOTPLUG,\r
- READ_PARSE_EDID,\r
- WAIT_RX_SENSE,\r
- WAIT_HDMI_ENABLE,\r
- SYSTEM_CONFIG,\r
- CONFIG_VIDEO,\r
- CONFIG_AUDIO,\r
- CONFIG_PACKETS,\r
- HDCP_AUTHENTICATION,\r
- PLAY_BACK,\r
- RESET_LINK,\r
- UNKNOWN,\r
-};\r
-\r
-\r
-struct anx7150_dev_s{\r
- struct i2c_driver *i2c_driver;\r
- struct fasync_struct *async_queue;\r
- struct workqueue_struct *workqueue;\r
- struct delayed_work delay_work;\r
- struct miscdevice *mdev;\r
- void (*notifier_callback)(struct anx7150_dev_s *);\r
- int anx7150_detect;\r
- int resolution_set;\r
- int resolution_real;\r
- int i2s_Fs;\r
- int hdmi_enable;\r
- int hdmi_auto_switch;\r
- int reciver_status;\r
- int HPD_change_cnt;\r
- int HPD_status;\r
- int rk29_output_status;\r
- int hdcp_enable;\r
- int parameter_config;\r
- int rate;\r
- int fb_switch_state;\r
-\r
- struct hdmi *hdmi;\r
-};\r
-\r
-struct anx7150_pdata {\r
- int irq;\r
- int gpio;\r
- int init;\r
- int is_early_suspend;\r
- int is_changed;\r
- struct delayed_work work;\r
- struct hdmi *hdmi;\r
- struct i2c_client *client;\r
- struct anx7150_dev_s dev;\r
-#ifdef CONFIG_HAS_EARLYSUSPEND\r
- struct early_suspend early_suspend;
-#endif\r
-};\r
-\r
-\r
-\r
-int anx7150_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val);\r
-int anx7150_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val);\r
-int anx7150_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val);\r
-int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val);\r
-\r
-#endif\r
+++ /dev/null
-#include <linux/delay.h>\r
-#include <linux/i2c.h>\r
-#include <linux/hdmi-new.h>\r
-\r
-\r
-#include "anx7150.h"\r
-#include "anx7150_hw.h"\r
-//#ifdef ITU656\r
-struct ANX7150_video_timingtype ANX7150_video_timingtype_table =\r
-{\r
- //640x480p-60hz\r
- {0x20/*H_RES_LOW*/, 0x03/*H_RES_HIGH*/,0x80 /*ACT_PIX_LOW*/,0x02 /*ACT_PIX_HIGH*/,\r
- 0x60/*HSYNC_WIDTH_LOW*/,0x00 /*HSYNC_WIDTH_HIGH*/,0x30 /*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/,0x02 /*VSYNC_WIDTH*/, 0x21/*V_BP_LINE*/,\r
- 0x0a/*V_FP_LINE*/,0x10 /*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720x480p-60hz\r
- {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x3c/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x06/*VSYNC_WIDTH*/, 0x1e/*V_BP_LINE*/,\r
- 0x09/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720p-60hz\r
- {0x72/*H_RES_LOW*/, 0x06/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
- 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0x6e/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //1080i-60hz\r
- {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //720x480i-60hz\r
- {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x39/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x13/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol}, //update\r
- //1080p-60hz\r
- {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //576p-50hz\r
- {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x40/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x44/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0x40/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x27/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720p-50hz\r
- {0xbc/*H_RES_LOW*/, 0x07/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
- 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0xb8/*H_FP_LOW*/, 0x01/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //1080i-50hz\r
- {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //576i-50hz\r
- {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3f/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x45/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0x40/*ACT_LINE_LOW*/,0x02 /*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x13/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- \r
- //1080p-50hz\r
- {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
-};\r
-//#endif\r
-int anx7150_mass_read_need_delay = 0;\r
-\r
-u8 g_video_format = 0x00;\r
-u8 g_audio_format = 0x00;\r
-\r
-\r
-u8 timer_slot = 0;\r
-u8 ANX7150_EDID_Buf[256];\r
-u8 ANX7150_avi_data[19];//, ANX7150_avi_checksum;\r
-u8 ANX7150_system_state = HDMI_INITIAL;\r
-u8 spdif_error_cnt = 0x00;\r
-u8 misc_reset_needed;\r
-u8 ANX7150_stdaddr,ANX7150_stdreg,ANX7150_ext_block_num;\r
-u8 ANX7150_svd_length,ANX7150_sau_length;\r
-u8 ANX7150_edid_dtd[18];\r
-u32 ANX7150_edid_length;\r
-ANX7150_edid_result_4_system ANX7150_edid_result;\r
-\r
-u8 ANX7150_ddc_fifo_full;\r
-u8 ANX7150_ddc_progress;\r
-u8 ANX7150_hdcp_auth_en;\r
-//u8 ANX7150_bksv_ready; //replace by srm_checked xy 01.09\r
-u8 ANX7150_HDCP_enable;\r
-u8 ANX7150_ksv_srm_pass;\r
-u8 ANX7150_hdcp_bcaps;\r
-u8 ANX7150_hdcp_bstatus[2];\r
-u8 ANX7150_srm_checked;\r
-u8 ANX7150_hdcp_auth_pass;\r
-u8 ANX7150_avmute_enable;\r
-u8 ANX7150_send_blue_screen;\r
-u8 ANX7150_hdcp_encryption;\r
-u8 ANX7150_hdcp_init_done;\r
-u8 ANX7150_hdcp_wait_100ms_needed;\r
-u8 ANX7150_auth_fully_pass;\r
-u8 ANX7150_parse_edid_done;//060714 XY\r
-//u8 testen;\r
-//u8 ANX7150_avi_data[19], ANX7150_avi_checksum;\r
-u8 ANX7150_hdcp_auth_fail_counter ;\r
-\r
-u8 ANX7150_video_format_config;\r
-u8 ANX7150_emb_sync_mode,ANX7150_de_gen_en,ANX7150_demux_yc_en,ANX7150_ddr_bus_mode;\r
-u8 ANX7150_ddr_edge,ANX7150_ycmux_u8_sel;\r
-u8 ANX7150_system_config_done;\r
-u8 ANX7150_RGBorYCbCr; //modified by zy 060814\r
-u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
-u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
-u8 ANX7150_video_timing_id;\r
-u8 ANX7150_pix_rpt_set_by_sys;\r
-u8 ANX7150_video_timing_parameter[18];\r
-u8 switch_value_sw_backup,switch_value_pc_backup;\r
-u8 switch_value,bist_switch_value_pc;\r
-u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
-u8 ANX7150_INT_Done;\r
-\r
-audio_config_struct s_ANX7150_audio_config;\r
-config_packets s_ANX7150_packet_config;\r
-\r
-u8 FREQ_MCLK; //0X72:0X50 u82:0\r
-//000b:Fm = 128*Fs\r
-//001b:Fm = 256*Fs\r
-//010b:Fm = 384*Fs\r
-//011b:Fm = 512*Fs\r
-u8 ANX7150_audio_clock_edge;\r
-\r
-\r
-int anx7150_detect_device(struct anx7150_pdata *anx)\r
-{\r
- int i, rc = 0; \r
- char d1, d2;\r
- \r
- for (i=0; i<10; i++) \r
- { \r
- if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDL_REG, &d1)) < 0) \r
- continue;\r
- if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDH_REG, &d2)) < 0) \r
- continue;\r
- if (d1 == 0x50 && d2 == 0x71)\r
- { \r
- hdmi_dbg(&anx->client->dev, "anx7150 detected!\n");\r
- return 0;\r
- } \r
- } \r
- \r
- hdmi_dbg(&anx->client->dev, "anx7150 not detected");\r
- return -1;\r
-}\r
-u8 ANX7150_Get_System_State(void)\r
-{\r
- return ANX7150_system_state;\r
-}\r
-void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state)\r
-{\r
- ANX7150_system_state = new_state;\r
- switch (ANX7150_system_state)\r
- {\r
- case HDMI_INITIAL:\r
- hdmi_dbg(&client->dev, "INITIAL\n");\r
- break;\r
- case WAIT_HOTPLUG:\r
- hdmi_dbg(&client->dev, "WAIT_HOTPLUG\n");\r
- break;\r
- case READ_PARSE_EDID:\r
- hdmi_dbg(&client->dev, "READ_PARSE_EDID\n");\r
- break;\r
- case WAIT_RX_SENSE:\r
- hdmi_dbg(&client->dev, "WAIT_RX_SENSE\n");\r
- break;\r
- case WAIT_HDMI_ENABLE:\r
- hdmi_dbg(&client->dev, "WAIT_HDMI_ENABLE\n");\r
- break;\r
- case SYSTEM_CONFIG:\r
- hdmi_dbg(&client->dev, "SYSTEM_CONFIG\n");\r
- break;\r
- case CONFIG_VIDEO:\r
- dev_info(&client->dev, "CONFIG_VIDEO\n");\r
- break;\r
- case CONFIG_AUDIO:\r
- hdmi_dbg(&client->dev, "CONFIG_AUDIO\n");\r
- break;\r
- case CONFIG_PACKETS:\r
- hdmi_dbg(&client->dev, "CONFIG_PACKETS\n");\r
- break;\r
- case HDCP_AUTHENTICATION:\r
- hdmi_dbg(&client->dev, "HDCP_AUTHENTICATION\n");\r
- break;\r
- ////////////////////////////////////////////////\r
- // System ANX7150_RESET_LINK is kept for RX clock recovery error case, not used in normal case.\r
- case RESET_LINK:\r
- hdmi_dbg(&client->dev, "RESET_LINK\n");\r
- break;\r
- ////////////////////////////////////////////////\r
- case PLAY_BACK:\r
- dev_info(&client->dev, "PLAY_BACK\n");\r
- break;\r
- default:\r
- hdmi_dbg(&client->dev, "unknown state\n");\r
- break;\r
- }\r
-}\r
-\r
-int anx7150_get_hpd(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char sys_ctl3, intr_state, sys_state, hpd_state;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &sys_ctl3)) < 0)\r
- return rc;\r
- if(sys_ctl3 & ANX7150_SYS_CTRL3_PWON_ALL)\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &sys_state)) < 0)\r
- return rc;\r
- hpd_state = (sys_state & ANX7150_SYS_STATE_HP)? 1:0;\r
- }\r
- else\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR_STATE_REG, &intr_state)) < 0)\r
- return rc;\r
- hpd_state = (intr_state)? 1:0;\r
- }\r
- return hpd_state;\r
-}\r
-static int anx7150_get_interrupt_status(struct i2c_client *client, struct anx7150_interrupt_s *interrupt_staus)\r
-{\r
- int rc = 0;\r
- u8 int_s1;\r
- u8 int_s2;\r
- u8 int_s3;\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//power down all, 090630\r
- rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//power down all, 090630\r
- rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//power down all, 090630\r
-\r
- interrupt_staus->hotplug_change = (int_s1 & ANX7150_INTR1_STATUS_HP_CHG) ? 1 : 0;\r
- interrupt_staus->video_format_change = (int_s3 & ANX7150_INTR3_STATUS_VIDF_CHG) ? 1 : 0;\r
- interrupt_staus->auth_done = (int_s2 & ANX7150_INTR2_STATUS_AUTH_DONE) ? 1 : 0;\r
- interrupt_staus->auth_state_change = (int_s2 & ANX7150_INTR2_STATUS_AUTH_CHG) ? 1 : 0;\r
- interrupt_staus->pll_lock_change = (int_s2 & ANX7150_INTR2_STATUS_PLLLOCK_CHG) ? 1 : 0;\r
- interrupt_staus->rx_sense_change = (int_s3 & ANX7150_INTR3_STATUS_RXSEN_CHG) ? 1 : 0;\r
- interrupt_staus->HDCP_link_change = (int_s2 & ANX7150_INTR2_STATUS_HDCPLINK_CHK) ? 1 : 0;\r
- interrupt_staus->audio_clk_change = (int_s3 & ANX7150_INTR3_STATUS_AUDCLK_CHG) ? 1 : 0;\r
- interrupt_staus->audio_FIFO_overrun = (int_s1 & ANX7150_INTR1_STATUS_AFIFO_OVER) ? 1 : 0;\r
- interrupt_staus->SPDIF_error = (int_s1 & ANX7150_INTR1_STATUS_SPDIF_ERR) ? 1 : 0;\r
- interrupt_staus->SPDIF_bi_phase_error = ((int_s3 & ANX7150_INTR3_STATUS_SPDIFBI_ERR) ? 1 : 0) \r
- || ((int_s3 & ANX7150_INTR3_STATUS_SPDIF_UNSTBL) ? 1 : 0);\r
- return 0;\r
-}\r
-static void ANX7150_Variable_Initial(void)\r
-{\r
- u8 i;\r
-\r
- ANX7150_hdcp_auth_en = 0;\r
- ANX7150_ksv_srm_pass =0;\r
- ANX7150_srm_checked = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_avmute_enable = 1;\r
- ANX7150_hdcp_auth_fail_counter =0;\r
- ANX7150_hdcp_encryption = 0;\r
- ANX7150_send_blue_screen = 0;\r
- ANX7150_hdcp_init_done = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- timer_slot = 0;\r
- //********************for video config**************\r
- ANX7150_video_timing_id = 0;\r
- ANX7150_in_pix_rpt = 0;\r
- ANX7150_tx_pix_rpt = 0;\r
- ANX7150_new_csc = 0;\r
- ANX7150_new_vid_id = 0;\r
- ANX7150_new_HW_interface = 0;\r
- //********************end of video config*********\r
-\r
- //********************for edid parse***********\r
- ANX7150_edid_result.is_HDMI = 0;\r
- ANX7150_edid_result.ycbcr422_supported = 0;\r
- ANX7150_edid_result.ycbcr444_supported = 0;\r
- ANX7150_edid_result.supported_720p_60Hz = 0;\r
- ANX7150_edid_result.supported_720p_50Hz = 0;\r
- ANX7150_edid_result.supported_576p_50Hz = 0;\r
- ANX7150_edid_result.supported_576i_50Hz = 0;\r
- ANX7150_edid_result.supported_1080i_60Hz = 0;\r
- ANX7150_edid_result.supported_1080i_50Hz = 0;\r
- ANX7150_edid_result.supported_640x480p_60Hz = 0;\r
- ANX7150_edid_result.supported_720x480p_60Hz = 0;\r
- ANX7150_edid_result.supported_720x480i_60Hz = 0;\r
- ANX7150_edid_result.edid_errcode = 0;\r
- ANX7150_edid_result.SpeakerFormat = 0;\r
- for (i = 0; i < 8; i ++)\r
- {\r
- ANX7150_edid_result.AudioChannel[i] = 0;\r
- ANX7150_edid_result.AudioFormat[i] = 0;\r
- ANX7150_edid_result.AudioFs[i] = 0;\r
- ANX7150_edid_result.AudioLength[i] = 0;\r
- }\r
- //********************end of edid**************\r
-\r
- s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe\r
- s_ANX7150_packet_config.avi_info.type = 0x82;\r
- s_ANX7150_packet_config.avi_info.version = 0x02;\r
- s_ANX7150_packet_config.avi_info.length = 0x0d;\r
- s_ANX7150_packet_config.avi_info.pb_u8[1] = 0x21;//YCbCr422\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x08;\r
- s_ANX7150_packet_config.avi_info.pb_u8[3] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[4] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[5] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[6] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[7] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[8] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[9] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[10] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[11] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[12] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[13] = 0x00;\r
-\r
- // audio infoframe\r
- s_ANX7150_packet_config.audio_info.type = 0x84;\r
- s_ANX7150_packet_config.audio_info.version = 0x01;\r
- s_ANX7150_packet_config.audio_info.length = 0x0a;\r
- s_ANX7150_packet_config.audio_info.pb_u8[1] = 0x00; //zy 061123 for ATC\r
- s_ANX7150_packet_config.audio_info.pb_u8[2] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[3] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[4] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[5] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[6] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[7] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[8] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[9] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[10] = 0x00;\r
-\r
- ANX7150_INT_Done = 0;\r
-}\r
-static void ANX7150_HW_Interface_Variable_Initial(void)\r
-{\r
- u8 c;\r
-\r
- ANX7150_video_format_config = 0x00;\r
- ANX7150_RGBorYCbCr = 0x00;\r
- ANX7150_ddr_edge = ANX7150_IDCK_EDGE_DDR;\r
-\r
- c = 0;\r
- c = (ANX7150_I2S_CH0_ENABLE << 2) | (ANX7150_I2S_CH1_ENABLE << 3) |\r
- (ANX7150_I2S_CH2_ENABLE << 4) | (ANX7150_I2S_CH3_ENABLE << 5);\r
- s_ANX7150_audio_config.audio_type = ANX7150_AUD_HW_INTERFACE; // input I2S\r
- s_ANX7150_audio_config.down_sample = 0x00;\r
- s_ANX7150_audio_config.i2s_config.audio_channel = c;//0x04;\r
- s_ANX7150_audio_config.i2s_config.Channel_status1 =0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status1 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status2 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status3 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status4 = 0x00;//0x02;//48k\r
- s_ANX7150_audio_config.i2s_config.Channel_status5 = ANX7150_I2S_WORD_LENGTH;//0x0b;\r
- s_ANX7150_audio_config.audio_layout = 0x00;\r
-\r
- c = (ANX7150_I2S_SHIFT_CTRL << 3) | (ANX7150_I2S_DIR_CTRL << 2) |\r
- (ANX7150_I2S_WS_POL << 1) | ANX7150_I2S_JUST_CTRL;\r
- s_ANX7150_audio_config.i2s_config.i2s_format = c;//0x00;\r
-\r
- FREQ_MCLK = ANX7150_MCLK_Fs_RELATION;//set the relation of MCLK and WS\r
- ANX7150_audio_clock_edge = ANX7150_AUD_CLK_EDGE;\r
-\r
-\r
-}\r
-static int anx7150_hardware_initial(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c = 0;\r
- \r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- mdelay(10);\r
-\r
- c &= (~0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- \r
- //Power on I2C\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (ANX7150_SYS_CTRL3_I2C_PWON);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c= 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
-\r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xbf);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //Power on Audio capture and Video capture module clock\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
- c |= (0x06);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
-\r
- //Enable auto set clock range for video PLL\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
- c &= (0x00);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
-\r
- //Set registers value of Blue Screen when HDCP authentication failed--RGB mode,green field\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, (c | 0x80));\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
- c |= (0x08);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_TX_AMP, &c);//jack wen\r
- c |= (0x01);\r
-\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_TX_AMP, &c); //TMDS swing\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL1_REG, &c); //Added for PLL unlock issue in high temperature - Feiw\r
- //if (ANX7150_AUD_HW_INTERFACE == 0x02) //jack wen, spdif\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xef);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
-\r
- c = 0xc7;\r
- rc = anx7150_i2c_write_p0_reg(client, 0xE1, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);//power down HDCP, 090630\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xfe);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power down all, 090630\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_rst_ddcchannel(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- //Reset the DDC channel\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- c |= (ANX7150_SYS_CTRL2_DDC_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- c &= (~ANX7150_SYS_CTRL2_DDC_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//abort current operation\r
-\r
- c = 0x06;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
-\r
- //Clear FIFO\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_unplug(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- dev_info(&client->dev, "anx7150 unplug\n");\r
- \r
- //wen HDCP CTS\r
- ANX7150_Variable_Initial(); //simon\r
- ANX7150_HW_Interface_Variable_Initial(); //simon\r
- \r
- rc = anx7150_hardware_initial(client); //simon\r
- if(rc < 0)\r
- dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //simon\r
- if(rc < 0)\r
- dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
- //wen HDCP CTS\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
-\r
- // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
- ANX7150_parse_edid_done = 0;\r
-// ANX7150_system_config_done = 0;\r
- ANX7150_srm_checked = 0;\r
-\r
- return rc;\r
-}\r
-int anx7150_plug(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- dev_info(&client->dev, "anx7150 plug\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power up all, 090630\r
-\r
- //disable audio & video & hdcp & TMDS and init begin\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
-\r
- ANX7150_Variable_Initial();\r
- //disable video & audio & hdcp & TMDS and init end\r
-\r
- \r
- //Power on chip and select DVI mode\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x05);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);// cwz change 0x01 -> 0x05\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfd);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //D("ANX7150 is set to DVI mode\n");\r
- rc = anx7150_rst_ddcchannel(client);\r
- //Initial Interrupt\r
- // disable video/audio CLK,Format change and before config video. 060713 xy\r
-\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR_CTRL_REG, &c);\r
-\r
- // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
- ANX7150_parse_edid_done = 0;\r
-// ANX7150_system_config_done = 0;\r
- ANX7150_srm_checked = 0;\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_set_avmute(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- c = 0x01;\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
- return rc;\r
- \r
- if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (0x0c);\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_avmute_enable = 1;\r
-\r
- return rc;\r
-}\r
-int anx7150_clear_avmute(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- c = 0x02;\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
- return rc;\r
- \r
- if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (0x0c);\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_avmute_enable = 0;\r
-// D("@@@@@@@@@@@@@@@@@@@@ANX7150_Clear_AVMute\n");\r
- return rc;\r
-\r
-}\r
-\r
-static int anx7150_video_format_change(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c;\r
- \r
- hdmi_dbg(&client->dev, "after video format change int \n");\r
- \r
- rc = anx7150_set_avmute(client);//wen\r
- //stop HDCP and reset DDC\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- rc = anx7150_rst_ddcchannel(client);\r
- \r
- //when format change, clear this reg to avoid error in package config\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- //xy 11.06 when format change, need system config again\r
- // ANX7150_system_config_done = 0;\r
- return rc;\r
-}\r
-static int anx7150_blue_screen_disable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- c &= (0xfb);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
-\r
- ANX7150_send_blue_screen = 0;\r
- \r
- return rc;\r
-}\r
-static int anx7150_blue_screen_enable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_send_blue_screen = 1;\r
-\r
- return rc;\r
-}\r
-static int anx7150_hdcp_encryption_enable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDCP_CTRL0_ENC_EN);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_hdcp_encryption = 1;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_hdcp_encryption_disable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- c &= (0xfb);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
-\r
- ANX7150_hdcp_encryption = 0;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_auth_done(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "anx7150 auth done\n");\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c)) < 0)\r
- return rc;\r
- \r
- if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Done\n");\r
- anx7150_blue_screen_disable(client);\r
- ANX7150_hdcp_auth_pass = 1;\r
- ANX7150_hdcp_auth_fail_counter = 0;\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication failed\n");\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_auth_fail_counter ++;\r
- if (ANX7150_hdcp_auth_fail_counter >= ANX7150_HDCP_FAIL_THRESHOLD)\r
- {\r
- ANX7150_hdcp_auth_fail_counter = 0;\r
- //ANX7150_bksv_ready = 0;\r
- // TODO: Reset link;\r
- rc = anx7150_blue_screen_enable(client);\r
- rc = anx7150_hdcp_encryption_disable(client);\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
- }\r
- return rc;\r
-}\r
-\r
-static int anx7150_clean_hdcp(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- //mute TMDS link\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);//jack wen\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, c & (~ANX7150_TMDS_CLKCH_MUTE));\r
-\r
- //Disable hardware HDCP\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- //Reset HDCP logic\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c |= (ANX7150_SRST_HDCP_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c &= (~ANX7150_SRST_HDCP_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
-\r
- //Set ReAuth\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= (ANX7150_HDCP_CTRL0_RE_AUTH);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_RE_AUTH);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
- //ANX7150_bksv_ready = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_auth_fail_counter =0 ;\r
- ANX7150_hdcp_encryption = 0;\r
- ANX7150_send_blue_screen = 0;\r
- ANX7150_hdcp_init_done = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_srm_checked = 0;\r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- return rc;\r
-}\r
-static int anx7150_auth_change(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- int state = ANX7150_Get_System_State();\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
- {\r
- ANX7150_hdcp_auth_pass = 1;\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Change\n");\r
- }\r
- else\r
- {\r
- rc = anx7150_set_avmute(client); //wen\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication failed_by_Auth_change\n");\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_hdcp_init_done=0; //wen HDCP CTS\r
- ANX7150_hdcp_auth_en=0; //wen HDCP CTS\r
- rc = anx7150_hdcp_encryption_disable(client);\r
- if (state == PLAY_BACK)\r
- {\r
- ANX7150_auth_fully_pass = 0;\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- rc = anx7150_clean_hdcp(client); //wen updated for Changhong TV\r
- }\r
- }\r
- return rc;\r
-}\r
-int ANX7150_GET_RECIVER_TYPE(void)\r
-{
- return ANX7150_edid_result.is_HDMI;
-}\r
-static int anx7150_audio_clk_change(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "ANX7150: audio clock changed interrupt,disable audio.\n");\r
- // disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //xy 11.06 when format change, need system config again\r
-// ANX7150_system_config_done = 0;\r
- return rc;\r
-}\r
-\r
-static int anx7150_afifo_overrun(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- hdmi_dbg(&client->dev, "ANX7150: AFIFO overrun interrupt,disable audio.\n");\r
- // disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int anx7150_spdif_error(struct i2c_client *client, int cur_state, int SPDIF_bi_phase_err, int SPDIF_error)\r
-{\r
- int rc = 0;\r
- char c;\r
- int state = cur_state;\r
-\r
- if(SPDIF_bi_phase_err || SPDIF_error)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- if( c & ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN) \r
- {\r
- \r
- if ((state == CONFIG_AUDIO \r
- || state == CONFIG_PACKETS \r
- || state == HDCP_AUTHENTICATION \r
- || state == PLAY_BACK ))\r
- {\r
- if(SPDIF_bi_phase_err){\r
- hdmi_dbg(&client->dev, "SPDIF BI Phase or Unstable error.\n");\r
- spdif_error_cnt += 0x03;\r
- }\r
-\r
- if(SPDIF_error){\r
- hdmi_dbg(&client->dev, "SPDIF Parity error.\n");\r
- spdif_error_cnt += 0x01;\r
- }\r
-\r
- }\r
-\r
- // adjust spdif phase\r
- if (spdif_error_cnt >= spdif_error_th)\r
- {\r
- char freq_mclk,c1,c2;\r
- spdif_error_cnt = 0x00;\r
- hdmi_dbg(&client->dev, "adjust mclk phase!\n");\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
-\r
- freq_mclk = c2 & 0x07;\r
- switch (freq_mclk)\r
- {\r
- case ANX7150_mclk_128_Fs: //invert 0x50[3]\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 128*Fs!\n");\r
- if ( c2 & 0x08 ) c2 &= 0xf7;\r
- else c2 |= 0x08;\r
-\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
- break;\r
-\r
- case ANX7150_mclk_256_Fs:\r
- case ANX7150_mclk_384_Fs:\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 256*Fs or 384*Fs!\n");\r
- if ( c1 & 0x60 ) c1 &= 0x9f;\r
- else c1 |= 0x20;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
- break;\r
-\r
- case ANX7150_mclk_512_Fs:\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 512*Fs!\n");\r
- if ( c1 & 0x60 ) c1 &= 0x9f;\r
- else c1 |= 0x40;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
- break;\r
- default:\r
- break;\r
-\r
- }\r
- }\r
- }\r
- }\r
- else{\r
- if(spdif_error_cnt > 0 && state == PLAY_BACK) spdif_error_cnt --;\r
- if(spdif_error_cnt > 0 && state < CONFIG_AUDIO) spdif_error_cnt = 0x00;\r
-\r
- }\r
-\r
- return rc;\r
-}\r
-static int anx7150_plllock(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_STATUS_REG, &c);\r
- if((c&0x01) == 0)\r
- {\r
- rc = anx7150_set_avmute(client);//wen\r
- hdmi_dbg(&client->dev, "ANX7150: PLL unlock interrupt,disable audio.\n");\r
- // disable audio & video\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- //when pll change, clear this reg to avoid error in package config\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);//wen\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
-// ANX7150_system_config_done = 0;//jack wen\r
- }\r
- return rc;\r
-}\r
-static int anx7150_rx_sense_change(struct i2c_client *client, int cur_state)\r
-{\r
- int rc = 0;\r
- char c;\r
- int state = cur_state;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
- hdmi_dbg(&client->dev, "ANX7150_Rx_Sense_Interrupt, ANX7150_SYS_STATE_REG = %.2x\n", (unsigned int)c); //wen\r
-\r
- if ( c & ANX7150_SYS_STATE_RSV_DET)\r
- {\r
- //xy 11.06 Power on chip\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe wen\r
- }\r
- else\r
- {\r
- // Rx is not active\r
- if (state > WAIT_HOTPLUG)\r
- {\r
- //stop HDCP and reset DDC when lost Rx sense\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_REG);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfd);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- \r
- // mute TMDS link\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- }\r
- //Power down chip\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfe);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- }\r
- //xy 11.06 when format change, need system config again\r
-// ANX7150_system_config_done = 0;//wen HDCP CTS\r
-\r
- return rc;\r
-}\r
-int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state)\r
-{\r
- struct anx7150_interrupt_s interrupt_staus;\r
-\r
- int state;\r
- int hot_plug;\r
- int rc;\r
-\r
- state = cur_state;\r
-\r
- hot_plug = anx7150_get_hpd(anx->client);\r
-\r
- rc = anx7150_get_interrupt_status(anx->client, &interrupt_staus);\r
- if(rc < 0){\r
- goto out;\r
- } \r
-\r
- if(anx->dev.HPD_status != hot_plug){\r
- anx->dev.HPD_change_cnt++;\r
- }\r
- else{\r
- anx->dev.HPD_change_cnt = 0;\r
- }\r
-\r
- if(anx->dev.HPD_change_cnt > 1){\r
- hdmi_dbg(&anx->client->dev, "hotplug_change\n");\r
-\r
- if(hot_plug == HDMI_RECIVER_UNPLUG){\r
- anx7150_unplug(anx->client);\r
- state = HDMI_INITIAL;\r
- anx->dev.reciver_status = HDMI_RECIVER_INACTIVE;\r
- }\r
-\r
- anx->dev.HPD_change_cnt = 0;\r
- anx->dev.HPD_status = hot_plug;\r
- }\r
- return state;\r
- if(state != HDMI_INITIAL && state != WAIT_HOTPLUG){\r
- if(interrupt_staus.video_format_change){\r
- if(state > SYSTEM_CONFIG){\r
- rc = anx7150_video_format_change(anx->client);\r
- state = CONFIG_VIDEO;\r
- }\r
- }\r
-\r
- if(interrupt_staus.auth_done){\r
- rc = anx7150_auth_done(anx->client);\r
- state = CONFIG_AUDIO;\r
- }\r
-\r
- if(interrupt_staus.auth_state_change){\r
- rc = anx7150_auth_change(anx->client);\r
- if(state == PLAY_BACK){\r
- state = HDCP_AUTHENTICATION;\r
- }\r
- }\r
-\r
- if(ANX7150_GET_RECIVER_TYPE() == 1){\r
- if(interrupt_staus.audio_clk_change){\r
- if(state > CONFIG_VIDEO){\r
- rc = anx7150_audio_clk_change(anx->client);\r
- state = SYSTEM_CONFIG;\r
- }\r
- }\r
- \r
- if(interrupt_staus.audio_FIFO_overrun){\r
- if(state > CONFIG_VIDEO){\r
- rc = anx7150_afifo_overrun(anx->client);\r
- state = CONFIG_AUDIO;\r
- }\r
- }\r
-\r
- rc = anx7150_spdif_error(anx->client, state, interrupt_staus.SPDIF_bi_phase_error, interrupt_staus.SPDIF_error);\r
- }\r
-\r
- if(interrupt_staus.pll_lock_change){\r
- if(state > SYSTEM_CONFIG){\r
- rc = anx7150_plllock(anx->client);\r
- state = SYSTEM_CONFIG;\r
- }\r
- }\r
-\r
- if(interrupt_staus.rx_sense_change){\r
- anx7150_rx_sense_change(anx->client, state);\r
- if(state > WAIT_RX_SENSE) \r
- state = WAIT_RX_SENSE;\r
- }\r
- }\r
-\r
-out:\r
- return state;\r
-}\r
-\r
-int ANX7150_API_Initial(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- hdmi_dbg(&client->dev, "%s\n", __func__);\r
-\r
- ANX7150_Variable_Initial();\r
- ANX7150_HW_Interface_Variable_Initial();\r
- rc = anx7150_hardware_initial(client);\r
-\r
- return rc;\r
-}\r
-\r
-void ANX7150_Shutdown(struct i2c_client *client)\r
-{\r
- hdmi_dbg(&client->dev, "%s\n", __func__);\r
- ANX7150_API_Initial(client);\r
- ANX7150_Set_System_State(client, HDMI_INITIAL);\r
-}\r
-\r
-static int anx7150_initddc_read(struct i2c_client *client, \r
- u8 devaddr, u8 segmentpointer,\r
- u8 offset, u8 access_num_Low,u8 access_num_high)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- //Write slave device address\r
- c = devaddr;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_ADDR_REG, &c);\r
- // Write segment address\r
- c = segmentpointer;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_SEGADDR_REG, &c);\r
- //Write offset\r
- c = offset;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_OFFADDR_REG, &c);\r
- //Write number for access\r
- c = access_num_Low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM0_REG, &c);\r
- c = access_num_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM1_REG, &c);\r
- //Clear FIFO\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
- //EDDC sequential Read\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int ANX7150_GetEDIDLength(struct i2c_client *client)\r
-{\r
- u8 edid_data_length;\r
- char c;\r
- int rc = 0;\r
-\r
- anx7150_rst_ddcchannel(client);\r
-\r
- rc = anx7150_initddc_read(client, 0xa0, 0x00, 0x7e, 0x01, 0x00);\r
- /*mdelay(3);//FeiW - Analogix\r
- for(i=0;i<10;i++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- if(c!=0){\r
- break;\r
- }\r
- }*/\r
- mdelay(10);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c);\r
- edid_data_length = c;\r
-\r
- ANX7150_edid_length = edid_data_length * 128 + 128;\r
-\r
- return rc;\r
-\r
-}\r
-static int ANX7150_DDC_Mass_Read(struct i2c_client *client, u32 length, u8 segment)\r
-{\r
- int rc = 0;\r
- u32 i, j;\r
- char c, c1,ddc_empty_cnt;\r
-\r
- i = length;\r
- while (i > 0)\r
- {\r
- //check DDC FIFO statue\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
- if (c & ANX7150_DDC_CHSTATUS_DDC_OCCUPY)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150 DDC channel is accessed by an external device, break!.\n");\r
- break;\r
- }\r
- if (c & ANX7150_DDC_CHSTATUS_FIFO_FULL)\r
- ANX7150_ddc_fifo_full = 1;\r
- else\r
- ANX7150_ddc_fifo_full = 0;\r
- if (c & ANX7150_DDC_CHSTATUS_INPRO)\r
- ANX7150_ddc_progress = 1;\r
- else\r
- ANX7150_ddc_progress = 0;\r
- if (ANX7150_ddc_fifo_full)\r
- {\r
- hdmi_dbg(&client->dev, "DDC FIFO is full during edid reading");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- hdmi_dbg(&client->dev, "FIFO counter is %.2x\n", (u32) c);\r
- for (j=0; j<c; j++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
- if (segment == 0)\r
- {\r
- ANX7150_EDID_Buf[length - i + j] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j), (u32) c1);\r
- }\r
- else if (segment == 1)\r
- {\r
- ANX7150_EDID_Buf[length - i + j + 0x80] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j + 0x80), (u32) c1);\r
- }\r
-\r
- ANX7150_ddc_fifo_full = 0;\r
- if(anx7150_mass_read_need_delay)\r
- mdelay(1);\r
- }\r
- i = i - c;\r
- //D("\n");\r
- }\r
- else if (!ANX7150_ddc_progress)\r
- {\r
- //D("ANX7150 DDC FIFO access finished.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- //D("FIFO counter is %.2x\n", (u32) c);\r
- if (!c)\r
- {\r
- i =0;\r
- break;\r
- }\r
- for (j=0; j<c; j++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
- if (segment == 0)\r
- {\r
- ANX7150_EDID_Buf[length - i + j] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j), (u32) c1);\r
- }\r
- else if (segment == 1)\r
- {\r
- ANX7150_EDID_Buf[length - i + j + 0x80] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j + 0x80), (u32) c1);\r
- }\r
- }\r
- i = i - c;\r
- //D("\ni=%d\n", i);\r
- }\r
- else\r
- {\r
- ddc_empty_cnt = 0x00;\r
- for (c1=0; c1<0x0a; c1++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
- //D("DDC FIFO access is progressing.\n");\r
- //D("DDC Channel status is 0x%.2x\n",(u32)c);\r
- if (c & ANX7150_DDC_CHSTATUS_FIFO_EMPT)\r
- ddc_empty_cnt++;\r
- mdelay(1);\r
- //D("ddc_empty_cnt = 0x%.2x\n",(u32)ddc_empty_cnt);\r
- }\r
- if (ddc_empty_cnt >= 0x0a)\r
- i = 0;\r
- }\r
- }\r
- return rc;\r
-}\r
-static int ANX7150_Read_EDID(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
-\r
- u8 edid_segment,segmentpointer,k;\r
-\r
- rc = anx7150_rst_ddcchannel(client);\r
- mdelay(1);\r
-\r
- edid_segment = ANX7150_edid_length / 256;\r
- if (edid_segment==0) //update\r
- segmentpointer =0;\r
- else\r
- segmentpointer = edid_segment - 1;\r
- //segmentpointer = edid_segment - 1;\r
-\r
- for (k = 0; k <= segmentpointer; k ++)\r
- {\r
- rc =anx7150_initddc_read(client, 0xa0, k, 0x00, 0x80, 0x00);\r
- mdelay(1);\r
- rc = ANX7150_DDC_Mass_Read(client, 128, k);\r
- //mdelay(10);\r
- rc = anx7150_initddc_read(client, 0xa0, k, 0x80, 0x80, 0x00);\r
- mdelay(1);\r
- rc = ANX7150_DDC_Mass_Read(client, 128, k + 1);\r
- //mdelay(10);\r
- }\r
-\r
- if ((ANX7150_edid_length - 256 * edid_segment) == 0)\r
- hdmi_dbg(&client->dev, "Finish reading EDID\n");\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "Read one more block(128 u8s).........\n");\r
- rc = anx7150_initddc_read(client, 0xa0, segmentpointer + 1, 0x00, 0x80, 0x00);\r
- mdelay(1);\r
- rc = ANX7150_DDC_Mass_Read(client, 128, segmentpointer + 1);\r
- hdmi_dbg(&client->dev, "Finish reading EDID\n");\r
- mdelay(1);\r
- }\r
- return rc;\r
-}\r
-static u8 ANX7150_Read_EDID_u8(u8 segmentpointer,u8 offset)\r
-{
- /*u8 c;
- anx7150_initddc_read(0xa0, segmentpointer, offset, 0x01, 0x00);\r
- ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFOCNT_REG, &c);
- while(c==0)
- ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFO_ACC_REG, &c);
- return c;*/
-
- return ANX7150_EDID_Buf[offset];
-}\r
-static u8 ANX7150_Parse_EDIDHeader(void)\r
-{\r
- u8 i,temp;\r
- temp = 0;\r
- // the EDID header should begin with 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00\r
- if ((ANX7150_Read_EDID_u8(0, 0) == 0x00) && (ANX7150_Read_EDID_u8(0, 7) == 0x00))\r
- {\r
- for (i = 1; i < 7; i++)\r
- {\r
- if (ANX7150_Read_EDID_u8(0, i) != 0xff)\r
- {\r
- temp = 0x01;\r
- break;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- temp = 0x01;\r
- }\r
- if (temp == 0x01)\r
- {\r
- return 0;\r
- }\r
- else\r
- {\r
- return 1;\r
- }\r
-}\r
-static u8 ANX7150_Parse_EDIDVersion(void)\r
-{\r
-\r
- if (!((ANX7150_Read_EDID_u8(0, 0x12) == 1) && (ANX7150_Read_EDID_u8(0, 0x13) >= 3) ))\r
- {\r
- return 0;\r
- }\r
- else\r
- {\r
- return 1;\r
- }\r
-}\r
-static void ANX7150_Parse_DTD(void)\r
-{
- u32 temp;
- unsigned long temp1,temp2;
- u32 Hresolution,Vresolution,Hblanking,Vblanking;
- u32 PixelCLK,Vtotal,H_image_size,V_image_size;
- u8 Hz;
- //float Ratio;
-
- temp = ANX7150_edid_dtd[1];
- temp = temp << 8;
- PixelCLK = temp + ANX7150_edid_dtd[0];
- // D("Pixel clock is 10000 * %u\n", temp);
-
- temp = ANX7150_edid_dtd[4];
- temp = (temp << 4) & 0x0f00;
- Hresolution = temp + ANX7150_edid_dtd[2];
- //D("Horizontal Active is %u\n", Hresolution);
-
- temp = ANX7150_edid_dtd[4];
- temp = (temp << 8) & 0x0f00;
- Hblanking = temp + ANX7150_edid_dtd[3];
- //D("Horizontal Blanking is %u\n", temp);
-
- temp = ANX7150_edid_dtd[7];
- temp = (temp << 4) & 0x0f00;
- Vresolution = temp + ANX7150_edid_dtd[5];
- //D("Vertical Active is %u\n", Vresolution);
-
- temp = ANX7150_edid_dtd[7];
- temp = (temp << 8) & 0x0f00;
- Vblanking = temp + ANX7150_edid_dtd[6];
- //D("Vertical Blanking is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 2) & 0x0300;
- temp = temp + ANX7150_edid_dtd[8];
- //D("Horizontal Sync Offset is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 4) & 0x0300;
- temp = temp + ANX7150_edid_dtd[9];
- //D("Horizontal Sync Pulse is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 2) & 0x0030;
- temp = temp + (ANX7150_edid_dtd[10] >> 4);
- //D("Vertical Sync Offset is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 4) & 0x0030;
- temp = temp + (ANX7150_edid_dtd[8] & 0x0f);
- //D("Vertical Sync Pulse is %u\n", temp);
-
- temp = ANX7150_edid_dtd[14];
- temp = (temp << 4) & 0x0f00;
- H_image_size = temp + ANX7150_edid_dtd[12];
- //D("Horizontal Image size is %u\n", temp);
-
- temp = ANX7150_edid_dtd[14];
- temp = (temp << 8) & 0x0f00;
- V_image_size = temp + ANX7150_edid_dtd[13];
- //D("Vertical Image size is %u\n", temp);
-
- //D("Horizontal Border is %bu\n", ANX7150_edid_dtd[15]);
-
- //D("Vertical Border is %bu\n", ANX7150_edid_dtd[16]);
-
- temp1 = Hresolution + Hblanking;
- Vtotal = Vresolution + Vblanking;
- temp1 = temp1 * Vtotal;
- temp2 = PixelCLK;
- temp2 = temp2 * 10000;
- if (temp1 == 0) //update
- Hz=0;
- else
- Hz = temp2 / temp1;
- //Hz = temp2 / temp1;
- if ((Hz == 59) || (Hz == 60))
- {
- Hz = 60;
- //D("_______________Vertical Active is %u\n", Vresolution);
- if (Vresolution == 540)
- ANX7150_edid_result.supported_1080i_60Hz = 1;
- if (Vresolution == 1080)
- ANX7150_edid_result.supported_1080p_60Hz = 1;
- if (Vresolution == 720)
- ANX7150_edid_result.supported_720p_60Hz = 1;
- if ((Hresolution == 640) && (Vresolution == 480))
- ANX7150_edid_result.supported_640x480p_60Hz = 1;
- if ((Hresolution == 720) && (Vresolution == 480))
- ANX7150_edid_result.supported_720x480p_60Hz = 1;
- if ((Hresolution == 720) && (Vresolution == 240))
- ANX7150_edid_result.supported_720x480i_60Hz = 1;
- }
- if (Hz == 50)
- {
- //D("+++++++++++++++Vertical Active is %u\n", Vresolution);
- if (Vresolution == 540)
- ANX7150_edid_result.supported_1080i_50Hz = 1;
- if (Vresolution == 1080)
- ANX7150_edid_result.supported_1080p_50Hz = 1;
- if (Vresolution == 720)
- ANX7150_edid_result.supported_720p_50Hz = 1;
- if (Vresolution == 576)
- ANX7150_edid_result.supported_576p_50Hz = 1;
- if (Vresolution == 288)
- ANX7150_edid_result.supported_576i_50Hz = 1;
- }
- //D("Fresh rate :% bu Hz\n", Hz);
- //Ratio = H_image_size;
- //Ratio = Ratio / V_image_size;
- //D("Picture ratio : %f \n", Ratio);
-}\r
-static void ANX7150_Parse_DTDinBlockONE(void)\r
-{
- u8 i;
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x36));
- }
- //D("Parse the first DTD in Block one:\n");
- ANX7150_Parse_DTD();
-
- if ((ANX7150_Read_EDID_u8(0, 0x48) == 0)
- && (ANX7150_Read_EDID_u8(0, 0x49) == 0)
- && (ANX7150_Read_EDID_u8(0, 0x4a) == 0))
- {
- ;//D("the second DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x48));
- }
- ANX7150_Parse_DTD();
- }
-
- if ((ANX7150_Read_EDID_u8(0,0x5a) == 0)
- && (ANX7150_Read_EDID_u8(0,0x5b) == 0)
- && (ANX7150_Read_EDID_u8(0,0x5c) == 0))
- {
- ;//D("the third DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x5a));
- }
- ANX7150_Parse_DTD();
- }
-
- if ((ANX7150_Read_EDID_u8(0,0x6c) == 0)
- && (ANX7150_Read_EDID_u8(0,0x6d) == 0)
- && (ANX7150_Read_EDID_u8(0,0x6e) == 0))
- {
- ;//D("the fourth DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0,(i + 0x6c));
- }
- ANX7150_Parse_DTD();
- }
-}\r
-static void ANX7150_Parse_NativeFormat(void)\r
-{
- u8 temp;
- temp = ANX7150_Read_EDID_u8(0,0x83) & 0xf0;
- /*if(temp & 0x80)
- ;//D("DTV supports underscan.\n");
- if(temp & 0x40)
- ;//D("DTV supports BasicAudio.\n");*/
- if (temp & 0x20)
- {
- //D("DTV supports YCbCr 4:4:4.\n");
- ANX7150_edid_result.ycbcr444_supported= 1;
- }
- if (temp & 0x10)
- {
- //D("DTV supports YCbCr 4:2:2.\n");
- ANX7150_edid_result.ycbcr422_supported= 1;
- }
-}\r
-static void ANX7150_Parse_DTDinExtBlock(void)\r
-{
- u8 i,DTDbeginAddr;
- DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2, 0x82)
- + 0x80;
- while (DTDbeginAddr < (0x6c + 0x80))
- {
- if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,DTDbeginAddr) == 0)
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 1)) == 0)
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 2)) == 0))
- {
- ;//D("this DTD in Extension Block is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(i + DTDbeginAddr));
- }
- //D("Parse the DTD in Extension Block :\n");
- ANX7150_Parse_DTD();
- }
- DTDbeginAddr = DTDbeginAddr + 18;
- }
-}\r
-static void ANX7150_Parse_AudioSTD(void)\r
-{
- u8 i,AudioFormat,STDReg_tmp,STDAddr_tmp;
- STDReg_tmp = ANX7150_stdreg & 0x1f;
- STDAddr_tmp = ANX7150_stdaddr + 1;
- i = 0;
- while (i < STDReg_tmp)
- {
- AudioFormat = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp ) & 0xF8) >> 3;
- ANX7150_edid_result.AudioChannel[i/3] = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x07) + 1;
- ANX7150_edid_result.AudioFormat[i/3] = AudioFormat;
- ANX7150_edid_result.AudioFs[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 1)) & 0x7f;
-
- if (AudioFormat == 1)
- ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) & 0x07;
- else
- ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) << 3;
-
- i = i + 3;
- STDAddr_tmp = STDAddr_tmp + 3;
- }
-}\r
-static void ANX7150_Parse_VideoSTD(void)\r
-{
- u8 i,STDReg_tmp,STDAddr_tmp;
- u8 SVD_ID[34];
- STDReg_tmp = ANX7150_stdreg & 0x1f;
- STDAddr_tmp = ANX7150_stdaddr + 1;
- i = 0;
- while (i < STDReg_tmp)
- {
- SVD_ID[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x7F;
- //D("ANX7150_edid_result.SVD_ID[%.2x]=0x%.2x\n",(u32)i,(u32)ANX7150_edid_result.SVD_ID[i]);
- //if(ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x80)
- // D(" Native mode");
- if (SVD_ID[i] == 1)
- ANX7150_edid_result.supported_640x480p_60Hz = 1;
- else if (SVD_ID[i] == 4)
- ANX7150_edid_result.supported_720p_60Hz = 1;
- else if (SVD_ID[i] == 19)
- ANX7150_edid_result.supported_720p_50Hz = 1;
- else if (SVD_ID[i] == 16)
- ANX7150_edid_result.supported_1080p_60Hz = 1;
- else if (SVD_ID[i] == 31)
- ANX7150_edid_result.supported_1080p_50Hz = 1;
- else if (SVD_ID[i] == 5)
- ANX7150_edid_result.supported_1080i_60Hz = 1;
- else if (SVD_ID[i] == 20)
- ANX7150_edid_result.supported_1080i_50Hz = 1;
- else if ((SVD_ID[i] == 2) ||(SVD_ID[i] == 3))
- ANX7150_edid_result.supported_720x480p_60Hz = 1;
- else if ((SVD_ID[i] == 6) ||(SVD_ID[i] == 7))
- ANX7150_edid_result.supported_720x480i_60Hz = 1;
- else if ((SVD_ID[i] == 17) ||(SVD_ID[i] == 18))
- ANX7150_edid_result.supported_576p_50Hz = 1;
- else if ((SVD_ID[i] == 21) ||(SVD_ID[i] == 22))
- ANX7150_edid_result.supported_576i_50Hz = 1;
-
- i = i + 1;
- STDAddr_tmp = STDAddr_tmp + 1;
- }
-}\r
-static void ANX7150_Parse_SpeakerSTD(void)\r
-{
- ANX7150_edid_result.SpeakerFormat = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) ;
-}\r
-static void ANX7150_Parse_VendorSTD(void)\r
-{\r
- //u8 c;\r
- if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) == 0x03)\r
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 2)) == 0x0c)\r
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 3)) == 0x00))\r
- {\r
- ANX7150_edid_result.is_HDMI = 1;\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c |ANX7150_SYS_CTRL1_HDMI);\r
- }\r
- else\r
- {\r
- ANX7150_edid_result.is_HDMI = 0;\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c & (~ANX7150_SYS_CTRL1_HDMI));\r
- }\r
-}\r
-\r
-static void ANX7150_Parse_STD(void)\r
-{
- u8 DTDbeginAddr;
- ANX7150_stdaddr = 0x84;
- DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,0x82) + 0x80;
- // D("Video DTDbeginAddr Register :%.2x\n", (u32) DTDbeginAddr);
- while (ANX7150_stdaddr < DTDbeginAddr)
- {
- ANX7150_stdreg = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,ANX7150_stdaddr);
- switch (ANX7150_stdreg & 0xe0)
- {
- case 0x20:
- ANX7150_Parse_AudioSTD();
- ANX7150_sau_length = ANX7150_stdreg & 0x1f;
- break;
- case 0x40:
- ANX7150_Parse_VideoSTD();
- ANX7150_svd_length = ANX7150_stdreg & 0x1f;
- break;
- case 0x80:
- ANX7150_Parse_SpeakerSTD();
- break;
- case 0x60:
- ANX7150_Parse_VendorSTD();
- break;
- default:
- break;
- }
- ANX7150_stdaddr = ANX7150_stdaddr + (ANX7150_stdreg & 0x1f) + 0x01;
- }
-}\r
-static u8 ANX7150_EDID_Checksum(u8 block_number)\r
-{
- u8 i, real_checksum;
- u8 edid_block_checksum;
-
- edid_block_checksum = 0;
- for (i = 0; i < 127; i ++)
- {
- if ((block_number / 2) * 2 == block_number)
- edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i);
- else
- edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i + 0x80);
- }
- edid_block_checksum = (~edid_block_checksum) + 1;
- // D("edid_block_checksum = 0x%.2x\n",(u32)edid_block_checksum);
- if ((block_number / 2) * 2 == block_number)
- real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0x7f);
- else
- real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0xff);
- if (real_checksum == edid_block_checksum)
- return 1;
- else
- return 0;
-}\r
-static u8 ANX7150_Parse_ExtBlock(void)\r
-{
- u8 i,c;
-
- for (i = 0; i < ANX7150_Read_EDID_u8(0, 0x7e); i++) //read in blocks
- {
- c = ANX7150_Read_EDID_u8(i/2, 0x80);
- if ( c == 0x02)
- {
- ANX7150_ext_block_num = i + 1;
- ANX7150_Parse_DTDinExtBlock();
- ANX7150_Parse_STD();
- if (!(ANX7150_EDID_Checksum(ANX7150_ext_block_num)))
- {
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;
- return ANX7150_edid_result.edid_errcode;
- }
- }
- else
- {
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_ExtBlock_NotFor_861B;
- return ANX7150_edid_result.edid_errcode;
- }
- }
-
- return 0;
-}\r
-int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev)\r
-{\r
- int rc = 0, i;\r
- char c;\r
-\r
- if(dev->rk29_output_status == RK29_OUTPUT_STATUS_LCD)\r
- anx7150_mass_read_need_delay = 1;\r
- else\r
- anx7150_mass_read_need_delay = 0;\r
-\r
- /* Clear HDCP Authentication indicator */\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
-\r
- rc = ANX7150_GetEDIDLength(client);\r
-\r
- hdmi_dbg(&client->dev, "EDIDLength is %.u\n", ANX7150_edid_length);\r
-\r
- rc = ANX7150_Read_EDID(client);\r
- \r
- if(!(ANX7150_Parse_EDIDHeader()))\r
- {\r
- dev_err(&client->dev, "BAD EDID Header, Stop parsing \n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_BadHeader;\r
- goto err;\r
- }\r
-\r
- if(!(ANX7150_Parse_EDIDVersion()))\r
- {\r
- dev_err(&client->dev, "EDID does not support 861B, Stop parsing\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_861B_not_supported;\r
- goto err;\r
- }\r
-\r
-/*\r
- if(ANX7150_EDID_Checksum(0) == 0)\r
- {\r
- D("EDID Block one check sum error, Stop parsing\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;\r
- return ANX7150_edid_result.edid_errcode;\r
- }\r
-*/\r
-\r
- //ANX7150_Parse_BasicDis();\r
- ANX7150_Parse_DTDinBlockONE();\r
- /*\r
- if(ANX7150_EDID_Buf[0x7e] == 0)\r
- {\r
- D("No EDID extension blocks.\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_No_ExtBlock;\r
- return ANX7150_edid_result.edid_errcode;\r
- }*/\r
- ANX7150_Parse_NativeFormat();\r
- ANX7150_Parse_ExtBlock();\r
-\r
- if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_ExtBlock_NotFor_861B){\r
- dev_err(&client->dev,"EDID ExtBlock not support for 861B, Stop parsing\n");\r
- goto err;\r
- }\r
-\r
- if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_CheckSum_ERR){\r
- dev_err(&client->dev,"EDID Block check sum error, Stop parsing\n");\r
- goto err;\r
- }\r
-\r
- hdmi_dbg(&client->dev,"EDID parsing finished!\n");\r
-\r
- {\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.edid_errcode = 0x%.2x\n",(u32)ANX7150_edid_result.edid_errcode);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.is_HDMI = 0x%.2x\n",(u32)ANX7150_edid_result.is_HDMI);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr422_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr422_supported);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr444_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr444_supported);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_640x480p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480i_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576i_50Hz);\r
- if (!ANX7150_edid_result.edid_errcode)\r
- {\r
- for (i = 0; i < ANX7150_sau_length/3; i++)\r
- {\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioChannel = 0x%.2x\n",(u32)ANX7150_edid_result.AudioChannel[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFormat = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFormat[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFs = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFs[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioLength = 0x%.2x\n",(u32)ANX7150_edid_result.AudioLength[i]);\r
- }\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.SpeakerFormat = 0x%.2x\n",(u32)ANX7150_edid_result.SpeakerFormat);\r
- }\r
- }\r
- \r
- ANX7150_parse_edid_done = 1;\r
-\r
- return 0;\r
- \r
-err:\r
- return ANX7150_edid_result.edid_errcode;\r
-}\r
-int ANX7150_GET_SENSE_STATE(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "enter\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
-\r
- return (c & ANX7150_SYS_STATE_RSV_DET) ? 1 : 0;\r
-}\r
-int ANX7150_Get_Optimal_resolution(int resolution_set)\r
-{\r
- int resolution_real;\r
- int find_resolution = 0;\r
-\r
- switch(resolution_set){\r
- case HDMI_1280x720p_50Hz:\r
- if(ANX7150_edid_result.supported_720p_50Hz){\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- if(ANX7150_edid_result.supported_720p_60Hz){\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz_4x3:\r
- if(ANX7150_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz_4x3;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz_16x9:\r
- if(ANX7150_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz_16x9;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x480p_60Hz_4x3:\r
- if(ANX7150_edid_result.supported_720x480p_60Hz){\r
- resolution_real = HDMI_720x480p_60Hz_4x3;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x480p_60Hz_16x9:\r
- if(ANX7150_edid_result.supported_720x480p_60Hz){\r
- resolution_real = HDMI_720x480p_60Hz_16x9;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- if(ANX7150_edid_result.supported_1080p_50Hz){\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_60Hz:\r
- if(ANX7150_edid_result.supported_1080p_60Hz){\r
- resolution_real = HDMI_1920x1080p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- if(find_resolution == 0){\r
-\r
- if(ANX7150_edid_result.supported_720p_50Hz)\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- else if(ANX7150_edid_result.supported_720p_60Hz)\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- else if(ANX7150_edid_result.supported_576p_50Hz)\r
- resolution_real = HDMI_720x576p_50Hz_4x3;\r
- else if(ANX7150_edid_result.supported_720x480p_60Hz)\r
- resolution_real = HDMI_720x480p_60Hz_4x3;\r
- else if(ANX7150_edid_result.supported_1080p_50Hz)\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- else if(ANX7150_edid_result.supported_1080p_60Hz)\r
- resolution_real = HDMI_1920x1080p_60Hz;\r
- else\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- }\r
-\r
- return resolution_real;\r
-}\r
-void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF)\r
-{ \r
- ANX7150_HDCP_enable = HDCP_ONorOFF;// 1: on; 0:off\r
-}\r
-static void ANX7150_API_Video_Config(u8 video_id,u8 input_pixel_rpt_time)\r
-{
- ANX7150_video_timing_id = video_id;
- ANX7150_in_pix_rpt = input_pixel_rpt_time;
-}\r
-static void ANX7150_API_Packets_Config(u8 pkt_sel)\r
-{
- s_ANX7150_packet_config.packets_need_config = pkt_sel;
-}\r
-static void ANX7150_API_AVI_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
- u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10,u8 pb11,u8 pb12,u8 pb13)
-{
- s_ANX7150_packet_config.avi_info.pb_u8[1] = pb1;
- s_ANX7150_packet_config.avi_info.pb_u8[2] = pb2;
- s_ANX7150_packet_config.avi_info.pb_u8[3] = pb3;
- s_ANX7150_packet_config.avi_info.pb_u8[4] = pb4;
- s_ANX7150_packet_config.avi_info.pb_u8[5] = pb5;
- s_ANX7150_packet_config.avi_info.pb_u8[6] = pb6;
- s_ANX7150_packet_config.avi_info.pb_u8[7] = pb7;
- s_ANX7150_packet_config.avi_info.pb_u8[8] = pb8;
- s_ANX7150_packet_config.avi_info.pb_u8[9] = pb9;
- s_ANX7150_packet_config.avi_info.pb_u8[10] = pb10;
- s_ANX7150_packet_config.avi_info.pb_u8[11] = pb11;
- s_ANX7150_packet_config.avi_info.pb_u8[12] = pb12;
- s_ANX7150_packet_config.avi_info.pb_u8[13] = pb13;
-}\r
-static void ANX7150_API_AUD_INFO_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
- u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10)
-{
- s_ANX7150_packet_config.audio_info.pb_u8[1] = pb1;
- s_ANX7150_packet_config.audio_info.pb_u8[2] = pb2;
- s_ANX7150_packet_config.audio_info.pb_u8[3] = pb3;
- s_ANX7150_packet_config.audio_info.pb_u8[4] = pb4;
- s_ANX7150_packet_config.audio_info.pb_u8[5] = pb5;
- s_ANX7150_packet_config.audio_info.pb_u8[6] = pb6;
- s_ANX7150_packet_config.audio_info.pb_u8[7] = pb7;
- s_ANX7150_packet_config.audio_info.pb_u8[8] = pb8;
- s_ANX7150_packet_config.audio_info.pb_u8[9] = pb9;
- s_ANX7150_packet_config.audio_info.pb_u8[10] = pb10;
-}\r
-static void ANX7150_API_AUD_CHStatus_Config(u8 MODE,u8 PCM_MODE,u8 SW_CPRGT,u8 NON_PCM,\r
- u8 PROF_APP,u8 CAT_CODE,u8 CH_NUM,u8 SOURCE_NUM,u8 CLK_ACCUR,u8 Fs)
-{
- //MODE: 0x00 = PCM Audio
- //PCM_MODE: 0x00 = 2 audio channels without pre-emphasis;
- //0x01 = 2 audio channels with 50/15 usec pre-emphasis;
- //SW_CPRGT: 0x00 = copyright is asserted;
- // 0x01 = copyright is not asserted;
- //NON_PCM: 0x00 = Represents linear PCM
- //0x01 = For other purposes
- //PROF_APP: 0x00 = consumer applications;
- // 0x01 = professional applications;
-
- //CAT_CODE: Category code
- //CH_NUM: 0x00 = Do not take into account
- // 0x01 = left channel for stereo channel format
- // 0x02 = right channel for stereo channel format
- //SOURCE_NUM: source number
- // 0x00 = Do not take into account
- // 0x01 = 1; 0x02 = 2; 0x03 = 3
- //CLK_ACCUR: 0x00 = level II
- // 0x01 = level I
- // 0x02 = level III
- // else reserved;
-
- s_ANX7150_audio_config.i2s_config.Channel_status1 = (MODE << 7) | (PCM_MODE << 5) |
- (SW_CPRGT << 2) | (NON_PCM << 1) | PROF_APP;
- s_ANX7150_audio_config.i2s_config.Channel_status2 = CAT_CODE;
- s_ANX7150_audio_config.i2s_config.Channel_status3 = (CH_NUM << 7) | SOURCE_NUM;
- s_ANX7150_audio_config.i2s_config.Channel_status4 = (CLK_ACCUR << 5) | Fs;\r
-}\r
-void ANX7150_API_System_Config(void)\r
-{\r
- ANX7150_API_Video_Config(g_video_format,input_pixel_clk_1x_repeatition);\r
- ANX7150_API_Packets_Config(ANX7150_avi_sel | ANX7150_audio_sel);\r
- if (s_ANX7150_packet_config.packets_need_config & ANX7150_avi_sel)\r
- ANX7150_API_AVI_Config( 0x00,source_ratio,null,null,null,null,null,null,null,null,null,null,null);\r
- if (s_ANX7150_packet_config.packets_need_config & ANX7150_audio_sel)\r
- ANX7150_API_AUD_INFO_Config(null,null,null,null,null,null,null,null,null,null);\r
- ANX7150_API_AUD_CHStatus_Config(null,null,null,null,null,null,null,null,null,g_audio_format);\r
-\r
-// ANX7150_system_config_done = 1;\r
-}\r
-\r
-static int anx7150_blue_screen_format_config(struct i2c_client *client)\r
-{\r
- int rc = 0 ;\r
- char c;\r
- \r
- // TODO:Add ITU 601 format.(Now only ITU 709 format added)\r
- switch (ANX7150_RGBorYCbCr)\r
- {\r
- case ANX7150_RGB: //select RGB mode\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- case ANX7150_YCbCr422: //select YCbCr4:2:2 mode\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xad;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x2a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- case ANX7150_YCbCr444: //select YCbCr4:4:4 mode\r
- c = 0x1a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xad;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x2a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- default:\r
- break;\r
- }\r
- return rc;\r
-}\r
-static void ANX7150_Get_Video_Timing(void)\r
-{\r
- u8 i;\r
- \r
-//#ifdef ITU656\r
- for (i = 0; i < 18; i++)\r
- {\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V640x480p_60Hz:\r
- //D("640x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_640x480p_60Hz[i];\r
- break;\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- //D("720x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480p_60Hz[i];\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- //D("1280x720p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_60Hz[i];\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- //D("1920x1080i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_60Hz[i];\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- //D("720x480i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480i_60Hz[i];\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- //D("720x576p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576p_50Hz[i];\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- //D("1280x720p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_50Hz[i];\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- //D("1920x1080i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_50Hz[i];\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- //D("720x576i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576i_50Hz[i];\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
- }\r
- /*#else\r
- for(i = 0; i < 18; i++)\r
- {\r
- switch(ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V640x480p_60Hz:\r
- //D("640x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- //D("720x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 18 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- //D("1280x720p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 36 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- //D("1920x1080i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 54 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- //D("720x480i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 72 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- //D("720x576p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 90 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- //D("1280x720p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 108 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- //D("1920x1080i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 126 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- //D("720x576i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 144 + i);\r
- DRVDelayMs(3);\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
- }\r
- #endif*/\r
-}\r
-static void ANX7150_Parse_Video_Format(void)\r
-{\r
- switch (ANX7150_video_format_config)\r
- {\r
- case ANX7150_RGB_YCrCb444_SepSync:\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- //D("RGB_YCrCb444_SepSync mode!\n");\r
- break;\r
- case ANX7150_YCrCb422_SepSync:\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- //D("YCrCb422_SepSync mode!\n");\r
- break;\r
- case ANX7150_YCrCb422_EmbSync:\r
- //D("YCrCb422_EmbSync mode!\n");\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCMux422_SepSync_Mode1:\r
- //D("YCMux422_SepSync_Mode1 mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ycmux_u8_sel = 0;\r
- ANX7150_demux_yc_en = 1;\r
- break;\r
- case ANX7150_YCMux422_SepSync_Mode2:\r
- //D("YCMux422_SepSync_Mode2 mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ycmux_u8_sel = 1;\r
- ANX7150_demux_yc_en = 1;\r
- break;\r
- case ANX7150_YCMux422_EmbSync_Mode1:\r
- //D("YCMux422_EmbSync_Mode1 mode!\n");\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ycmux_u8_sel = 0;\r
- ANX7150_demux_yc_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCMux422_EmbSync_Mode2:\r
- //D("YCMux422_EmbSync_Mode2 mode!\n");\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ycmux_u8_sel = 1;\r
- ANX7150_demux_yc_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_RGB_YCrCb444_DDR_SepSync:\r
- //D("RGB_YCrCb444_DDR_SepSync mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ddr_bus_mode = 1;\r
- break;\r
- case ANX7150_RGB_YCrCb444_DDR_EmbSync:\r
- //D("RGB_YCrCb444_DDR_EmbSync mode!\n");\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ddr_bus_mode = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_RGB_YCrCb444_SepSync_No_DE:\r
- //D("RGB_YCrCb444_SepSync_No_DE mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCrCb422_SepSync_No_DE:\r
- //D("YCrCb422_SepSync_No_DE mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- default:\r
- break;\r
- }\r
-}\r
-static int anx7150_de_generator(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- u8 video_type,hsync_pol,vsync_pol,v_fp,v_bp,vsync_width;\r
- u8 hsync_width_low,hsync_width_high,v_active_low,v_active_high;\r
- u8 h_active_low,h_active_high,h_res_low,h_res_high,h_bp_low,h_bp_high;\r
- u32 hsync_width,h_active,h_res,h_bp;\r
-\r
- video_type = ANX7150_video_timing_parameter[15];\r
- hsync_pol = ANX7150_video_timing_parameter[16];\r
- vsync_pol = ANX7150_video_timing_parameter[17];\r
- v_fp = ANX7150_video_timing_parameter[12];\r
- v_bp = ANX7150_video_timing_parameter[11];\r
- vsync_width = ANX7150_video_timing_parameter[10];\r
- hsync_width = ANX7150_video_timing_parameter[5];\r
- hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
- v_active_high = ANX7150_video_timing_parameter[9];\r
- v_active_low = ANX7150_video_timing_parameter[8];\r
- h_active = ANX7150_video_timing_parameter[3];\r
- h_active = (h_active << 8) + ANX7150_video_timing_parameter[2];\r
- h_res = ANX7150_video_timing_parameter[1];\r
- h_res = (h_res << 8) + ANX7150_video_timing_parameter[0];\r
- h_bp = ANX7150_video_timing_parameter[7];\r
- h_bp = (h_bp << 8) + ANX7150_video_timing_parameter[6];\r
- if (ANX7150_demux_yc_en)\r
- {\r
- hsync_width = 2* hsync_width;\r
- h_active = 2 * h_active;\r
- h_res = 2 * h_res;\r
- h_bp = 2 * h_bp;\r
- }\r
- hsync_width_low = hsync_width & 0xff;\r
- hsync_width_high = (hsync_width >> 8) & 0xff;\r
- h_active_low = h_active & 0xff;\r
- h_active_high = (h_active >> 8) & 0xff;\r
- h_res_low = h_res & 0xff;\r
- h_res_high = (h_res >> 8) & 0xff;\r
- h_bp_low = h_bp & 0xff;\r
- h_bp_high = (h_bp >> 8) & 0xff;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xf7) | video_type;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xdf) | hsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xbf) | vsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = v_active_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEL_REG, &c);\r
- c = v_active_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEH_REG, &c);\r
- c = vsync_width;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
- c = v_bp;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_TAIL2VIDLINE_REG, &c);\r
- c = h_active_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXL_REG, &c);\r
- c = h_active_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXH_REG, &c);\r
- c = h_res_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESL_REG, &c);\r
- c = h_res_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESH_REG, &c);\r
- c = hsync_width_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
- c = hsync_width_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
- c = h_bp_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHL_REG, &c);\r
- c = h_bp_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHH_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= ANX7150_VID_CAPCTRL0_DEGEN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int anx7150_embed_sync_decode(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- u8 video_type,hsync_pol,vsync_pol,v_fp,vsync_width;\r
- u8 h_fp_low,h_fp_high,hsync_width_low,hsync_width_high;\r
- u32 h_fp,hsync_width;\r
- \r
- video_type = ANX7150_video_timing_parameter[15];\r
- hsync_pol = ANX7150_video_timing_parameter[16];\r
- vsync_pol = ANX7150_video_timing_parameter[17];\r
- v_fp = ANX7150_video_timing_parameter[12];\r
- vsync_width = ANX7150_video_timing_parameter[10];\r
- h_fp = ANX7150_video_timing_parameter[14];\r
- h_fp = (h_fp << 8) + ANX7150_video_timing_parameter[13];\r
- hsync_width = ANX7150_video_timing_parameter[5];\r
- hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
- if (ANX7150_demux_yc_en)\r
- {\r
- h_fp = 2 * h_fp;\r
- hsync_width = 2* hsync_width;\r
- }\r
- h_fp_low = h_fp & 0xff;\r
- h_fp_high = (h_fp >> 8) & 0xff;\r
- hsync_width_low = hsync_width & 0xff;\r
- hsync_width_high = (hsync_width >> 8) & 0xff;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xf7) | video_type;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xdf) | hsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xbf) | vsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c = c | ANX7150_VID_CAPCTRL0_EMSYNC_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- c = v_fp;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINE2VSYNC_REG, &c);\r
- c = vsync_width;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
- c = h_fp_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHL_REG, &c);\r
- c = h_fp_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHH_REG, &c);\r
- c = hsync_width_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
- c = hsync_width_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
- return rc;\r
-}\r
-int ANX7150_Blue_Screen(struct anx7150_pdata *anx)\r
-{\r
- return anx7150_blue_screen_format_config(anx->client);\r
-}\r
-//******************************Video Config***************************************\r
-int ANX7150_Config_Video(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c,TX_is_HDMI;\r
- char cspace_y2r, y2r_sel, up_sample,range_y2r;\r
-\r
- cspace_y2r = 0;\r
- y2r_sel = 0;\r
- up_sample = 0;\r
- range_y2r = 0;\r
-\r
- //ANX7150_RGBorYCbCr = 0x00; //RGB\r
- //ANX7150_RGBorYCbCr = ANX7150_INPUT_COLORSPACE; //update\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-/*\r
- if (!ANX7150_system_config_done)\r
- {\r
- D("System has not finished config!\n");\r
- return;\r
- }\r
-*/\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
- if (!(c & 0x02))\r
- {\r
- hdmi_dbg(&client->dev, "No clock detected !\n");\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL2_REG, 0x02);\r
- return -1;\r
- }\r
-\r
- rc = anx7150_clean_hdcp(client);\r
-\r
- //color space issue\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V1280x720p_50Hz:\r
- case ANX7150_V1280x720p_60Hz:\r
- case ANX7150_V1920x1080i_60Hz:\r
- case ANX7150_V1920x1080i_50Hz:\r
- case ANX7150_V1920x1080p_60Hz:\r
- case ANX7150_V1920x1080p_50Hz:\r
- y2r_sel = ANX7150_CSC_BT709;\r
- break;\r
- default:\r
- y2r_sel = ANX7150_CSC_BT601;\r
- break;\r
- }\r
- //rang[0~255]/[16~235] select\r
- if (ANX7150_video_timing_id == ANX7150_V640x480p_60Hz)\r
- range_y2r = 1;//rang[0~255]\r
- else\r
- range_y2r = 0;//rang[16~235]\r
- if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr422) && (!ANX7150_edid_result.ycbcr422_supported))\r
- {\r
- up_sample = 1;\r
- if (ANX7150_edid_result.ycbcr444_supported)\r
- cspace_y2r = 0;\r
- else\r
- cspace_y2r = 1;\r
- }\r
- if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr444) && (!ANX7150_edid_result.ycbcr444_supported))\r
- {\r
- cspace_y2r = 1;\r
- }\r
- //Config the embeded blue screen format according to output video format.\r
- rc = anx7150_blue_screen_format_config(client);\r
-\r
- ANX7150_Parse_Video_Format();\r
-\r
- if (ANX7150_de_gen_en)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_de_gen_en!\n");\r
- rc = anx7150_de_generator(client);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DEGEN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- if (ANX7150_emb_sync_mode)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Embed_Sync_Decode!\n");\r
- rc = anx7150_embed_sync_decode(client);\r
- \r
- if (ANX7150_ddr_bus_mode) //jack wen; for DDR embeded sync\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c |= (0x04);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c &= (0xfb);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_EMSYNC_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- if (ANX7150_demux_yc_en)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- \r
- if (ANX7150_ycmux_u8_sel)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D1-4\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D1-4\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
- //\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D5-8,\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D5-8\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- \r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
- //\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- //jack wen\r
-\r
- //\r
-\r
- }\r
- if (ANX7150_ddr_bus_mode)\r
- {\r
- //D("ANX7150_ddr_bus_mode!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- //jack wen\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c = (c & 0xfc) | 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- \r
- //jack wen\r
-\r
- if (ANX7150_ddr_edge)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
-\r
- //jack wen for DDR+seperate maping\r
- if (ANX7150_video_format_config == 0x07)//jack wen, DDR yc422, 601,\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_DDR_601_Maping!\n");\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL23, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL22, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL21, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL20, &c);\r
- c = 0x07;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL19, &c);\r
- c = 0x06;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL18, &c);\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL17, &c);\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL16, &c);\r
-\r
- c = 0x17;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
- c = 0x16;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
- c = 0x15;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL13, &c);\r
- c = 0x14;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
- c = 0x13;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x12;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x11;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
-\r
- c = 0x03;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
- c = 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
- c = 0x0f;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
- c = 0x0e;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL2, &c);\r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL1, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL0, &c);\r
-\r
- }\r
- else if (ANX7150_video_format_config == 0x08)//jack wen, DDR yc422, 656,\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_DDR_656_Maping!\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c &= (0xfc);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
-\r
- if (cspace_y2r)\r
- {\r
- hdmi_dbg(&client->dev, "Color space Y2R enabled********\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_CSPACE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- if (y2r_sel)\r
- {\r
- hdmi_dbg(&client->dev, "Y2R_SEL!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_Y2R_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_Y2R_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c); \r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_CSPACE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (up_sample)\r
- {\r
- hdmi_dbg(&client->dev, "UP_SAMPLE!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_UPSAMPLE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_UPSAMPLE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (range_y2r)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_RANGE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_RANGE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (!ANX7150_pix_rpt_set_by_sys)\r
- {\r
- if ((ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_16x9)\r
- || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_16x9)\r
- || (ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_4x3)\r
- || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_4x3))\r
- ANX7150_tx_pix_rpt = 1;\r
- else\r
- ANX7150_tx_pix_rpt = 0;\r
- }\r
- //set input pixel repeat times\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c = ((c & 0xfc) |ANX7150_in_pix_rpt);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- //set link pixel repeat times\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c = ((c & 0xfc) |ANX7150_tx_pix_rpt);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- if ((ANX7150_in_pix_rpt != ANX7150_in_pix_rpt_bkp)\r
- ||(ANX7150_tx_pix_rpt != ANX7150_tx_pix_rpt_bkp) )\r
- {\r
- c = 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- hdmi_dbg(&client->dev, "MISC_Reset!\n");\r
- ANX7150_in_pix_rpt_bkp = ANX7150_in_pix_rpt;\r
- ANX7150_tx_pix_rpt_bkp = ANX7150_tx_pix_rpt;\r
- }\r
- //enable video input\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //D("Video configure OK!\n");\r
- mdelay(60);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_STATUS_REG, &c);\r
- if (!(c & ANX7150_VID_STATUS_VID_STABLE))\r
- {\r
- hdmi_dbg(&client->dev,"Video not stable!\n");\r
- return -1;\r
- }\r
- if (cspace_y2r)\r
- ANX7150_RGBorYCbCr = ANX7150_RGB;\r
- //Enable video CLK,Format change after config video.\r
- // ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
- // ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, c |0x01);//3\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
- c |= (0x48);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
- c |= (0x40);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
- \r
- if (ANX7150_edid_result.is_HDMI)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x02);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- hdmi_dbg(&client->dev,"ANX7150 is set to HDMI mode\n");\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- TX_is_HDMI = c & 0x02;\r
-\r
- if (TX_is_HDMI == 0x02)\r
- {\r
- anx7150_set_avmute(client);//wen\r
- }\r
-\r
- //reset TMDS link to align 4 channels xy 061120\r
- hdmi_dbg(&client->dev,"reset TMDS link to align 4 channels\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c |= (ANX7150_TX_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c &= (~ANX7150_TX_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- \r
- //Enable TMDS clock output // just enable u87, and let the other u8s along to avoid overwriting.\r
- hdmi_dbg(&client->dev,"Enable TMDS clock output\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c |= (ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- if(ANX7150_HDCP_enable)\r
- mdelay(100); //400ms only for HDCP CTS\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_VID_MODE_REG, &c); //zy 061110\r
- return 0;\r
-}\r
-static u8 anx7150_config_i2s(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c = 0x00;\r
- u8 exe_result = 0x00;\r
- char c1 = 0x00;\r
-\r
- hdmi_dbg(&client->dev,"ANX7150: config i2s audio.\n");\r
-\r
- //select SCK as source\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_CLK_SEL;\r
- hdmi_dbg(&client->dev,"select SCK as source, c = 0x%.2x\n",(u32)c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
-\r
- //config i2s channel\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c1 = s_ANX7150_audio_config.i2s_config.audio_channel; // need u8[5:2]\r
- c1 &= 0x3c;\r
- c &= ~0x3c;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s channel, c = 0x%.2x\n",(u32)c);\r
- \r
- //config i2s format\r
- //ANX7150_i2c_read_p0_reg(ANX7150_I2S_CTRL_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.i2s_format;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s format, c = 0x%.2x\n",(u32)c);\r
-\r
- //map i2s fifo\r
-\r
- //TODO: config I2S channel map register according to system\r
-\r
-\r
- //ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_CTRL_REG, c);\r
-\r
- //swap right/left channel\r
- /*ANX7150_i2c_read_p0_reg(ANX7150_I2SCH_SWCTRL_REG, &c);\r
- c1 = 0x00;\r
- c1 &= 0xf0;\r
- c &= ~0xf0;\r
- c |= c1;\r
- ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_SWCTRL_REG, c);\r
- D("map i2s ffio, c = 0x%.2x\n",(u32)c);*/\r
-\r
- //down sample\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c1 = s_ANX7150_audio_config.down_sample;\r
- c1 &= 0x60;\r
- c &= ~0x60;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev,"down sample, c = 0x%.2x\n",(u32)c);\r
-\r
- //config i2s channel status(5 regs)\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS1_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status2;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS2_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status3;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS3_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status4;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- hdmi_dbg(&client->dev,"@@@@@@@@config i2s channel status4, c = 0x%.2x\n",(unsigned int)c);//jack wen\r
-\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status5;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS5_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s channel status, c = 0x%.2x\n",(u32)c);\r
-\r
- exe_result = ANX7150_i2s_input;\r
- //D("return = 0x%.2x\n",(u32)exe_result);\r
-\r
- // open corresponding interrupt\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, (c | 0x22) );\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0x20) );\r
-\r
-\r
- return exe_result;\r
-}\r
-\r
-static u8 anx7150_config_spdif(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- char c = 0x00;\r
- char c1 = 0x00;\r
- // u8 c2 = 0x00;\r
- // u8 freq_mclk = 0x00;\r
-\r
- hdmi_dbg(&client->dev, "ANX7150: config SPDIF audio.\n");\r
-\r
-\r
- //Select MCLK\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //D("ANX7150: enable SPDIF audio.\n");\r
- //Enable SPDIF\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //adjust MCLK phase in interrupt routine\r
-\r
- // adjust FS_FREQ //FS_FREQ\r
- c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
- c &= ANX7150_SPDIFCH_STATUS_FS_FREG;\r
- c = c >> 4;\r
-\r
- if ( c != c1)\r
- {\r
- //D("adjust FS_FREQ by system!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- c &= 0xf0;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
-\r
- //enable using FS_FREQ from 0x59\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (0x02);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- // down sample\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c1 = s_ANX7150_audio_config.down_sample;\r
- c1 &= 0x60;\r
- c &= ~0x60;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-\r
- if (s_ANX7150_audio_config.down_sample) //zy 060816\r
- {\r
- // adjust FS_FREQ by system because down sample\r
- //D("adjust FS_FREQ by system because down sample!\n");\r
-\r
- c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- \r
- c &= 0xf0;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- }\r
-\r
-\r
- // spdif is stable\r
- hdmi_dbg(&client->dev, "config SPDIF audio done");\r
- exe_result = ANX7150_spdif_input;\r
-\r
- // open corresponding interrupt\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
- c |= (0x32);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0xa1) );\r
- return exe_result;\r
-}\r
-\r
-static u8 anx7150_config_super_audio(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- u8 c = 0x00;\r
-\r
-\r
- //D("ANX7150: config one u8 audio.\n");\r
-\r
- // select sck as source\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- // Enable stream 0x60\r
- c = s_ANX7150_audio_config.super_audio_config.one_u8_ctrl;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
-\r
-\r
- // Map stream 0x61\r
- // TODO: config super audio map register according to system\r
-\r
- exe_result = ANX7150_super_audio_input;\r
- return exe_result;\r
-\r
-}\r
-\r
-u8 ANX7150_Config_Audio(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c = 0x00;\r
- u8 exe_result = 0x00;\r
- u8 audio_layout = 0x00;\r
- u8 fs = 0x00;\r
- u32 ACR_N = 0x0000;\r
-\r
- //set audio clock edge\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = ((c & 0xf7) | ANX7150_audio_clock_edge);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- \r
- //cts get select from SCK\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xef);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev, "audio_type = 0x%.2x\n",(u32)s_ANX7150_audio_config.audio_type);\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
- {\r
- hdmi_dbg(&client->dev, "Config I2s.\n");\r
- exe_result |= anx7150_config_i2s(client);\r
- }\r
- else\r
- {\r
- //disable I2S audio input\r
- hdmi_dbg(&client->dev, "Disable I2S audio input.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= 0xc3;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_spdif_input)\r
- {\r
- exe_result |= anx7150_config_spdif(client);\r
- }\r
- else\r
- {\r
- //disable SPDIF audio input\r
- hdmi_dbg(&client->dev, "Disable SPDIF audio input.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
- {\r
- exe_result |= anx7150_config_super_audio(client);\r
- }\r
- else\r
- {\r
- //disable super audio output\r
- hdmi_dbg(&client->dev, "ANX7150: disable super audio output.\n");\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
- }\r
-\r
- if ((s_ANX7150_audio_config.audio_type & 0x07) == 0x00)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150 input no audio type.\n");\r
- }\r
-\r
- //audio layout\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
- {\r
- //ANX7150_i2c_read_p0_reg(ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- audio_layout = s_ANX7150_audio_config.audio_layout;\r
-\r
- //HDMI_RX_ReadI2C_RX0(0x15, &c);\r
-#if 0\r
- if ((c & 0x08) ==0x08 ) //u8[5:3]\r
- {\r
- audio_layout = 0x80;\r
- }\r
- else\r
- {\r
- audio_layout = 0x00;\r
- }\r
-#endif\r
- }\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
- if ( c & 0xfc) //u8[5:3]\r
- {\r
- audio_layout = 0x80;\r
- }\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c &= ~0x80;\r
- c |= audio_layout;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-\r
- if ( (s_ANX7150_audio_config.audio_type & 0x07) == exe_result )\r
- {\r
- //Initial N value\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- fs = c & 0x0f;\r
- // set default value to N\r
- ACR_N = ANX7150_N_48k;\r
- switch (fs)\r
- {\r
- case(0x00)://44.1k\r
- ACR_N = ANX7150_N_44k;\r
- break;\r
- case(0x02)://48k\r
- ACR_N = ANX7150_N_48k;\r
- break;\r
- case(0x03)://32k\r
- ACR_N = ANX7150_N_32k;\r
- break;\r
- case(0x08)://88k\r
- ACR_N = ANX7150_N_88k;\r
- break;\r
- case(0x0a)://96k\r
- ACR_N = ANX7150_N_96k;\r
- break;\r
- case(0x0c)://176k\r
- ACR_N = ANX7150_N_176k;\r
- break;\r
- case(0x0e)://192k\r
- ACR_N = ANX7150_N_192k;\r
- break;\r
- default:\r
- dev_err(&client->dev, "note wrong fs.\n");\r
- break;\r
- }\r
- // write N(ACR) to corresponding regs\r
- c = ACR_N;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N1_SW_REG, &c);\r
- c = ACR_N>>8;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N2_SW_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N3_SW_REG, &c);\r
- \r
- // set the relation of MCLK and Fs xy 070117\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xf8) | FREQ_MCLK;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev, "Audio MCLK input mode is: %.2x\n",(u32)FREQ_MCLK);\r
-\r
- //Enable control of ACR\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= (ANX7150_INFO_PKTCTRL1_ACR_EN);\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- //audio enable:\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- return exe_result;\r
-\r
-}\r
-static u8 ANX7150_Checksum(infoframe_struct *p)\r
-{
- u8 checksum = 0x00;
- u8 i;
-
- checksum = p->type + p->length + p->version;
- for (i=1; i <= p->length; i++)
- {
- checksum += p->pb_u8[i];
- }
- checksum = ~checksum;
- checksum += 0x01;
-
- return checksum;
-}\r
-static u8 anx7150_load_infoframe(struct i2c_client *client, packet_type member,\r
- infoframe_struct *p)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- u8 address[8] = {0x00,0x20,0x40,0x60,0x80,0x80,0xa0,0xa0};\r
- u8 i;\r
- char c;\r
-\r
- p->pb_u8[0] = ANX7150_Checksum(p);\r
-\r
- // write infoframe to according regs\r
- c = p->type;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member], &c);\r
- c = p->version;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+1, &c);\r
- c = p->length;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+2, &c);\r
-\r
- for (i=0; i <= p->length; i++)\r
- {\r
- c = p->pb_u8[i];\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+3+i, &c);\r
- rc = anx7150_i2c_read_p1_reg(client, address[member]+3+i, &c);\r
- }\r
- return exe_result;\r
-}\r
-\r
-//*************** Config Packet ****************************\r
-u8 ANX7150_Config_Packet(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00; // There is no use in current solution\r
- u8 info_packet_sel;\r
- char c;\r
-\r
- info_packet_sel = s_ANX7150_packet_config.packets_need_config;\r
- hdmi_dbg(&client->dev, "info_packet_sel = 0x%.2x\n",(u32) info_packet_sel);\r
- // New packet?\r
- if ( info_packet_sel != 0x00)\r
- {\r
- // avi infoframe\r
- if ( info_packet_sel & ANX7150_avi_sel )\r
- {\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[1]; //color space\r
- c &= 0x9f;\r
- c |= (ANX7150_RGBorYCbCr << 5);\r
- s_ANX7150_packet_config.avi_info.pb_u8[1] = c | 0x10;\r
-\r
- switch(ANX7150_video_timing_id) {\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x59;\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xaa;\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xaa;\r
- break;\r
- default:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xaa;\r
- break;\r
- }\r
-\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[4];// vid ID\r
- c = c & 0x80;\r
- s_ANX7150_packet_config.avi_info.pb_u8[4] = c | ANX7150_video_timing_id;\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[5]; //repeat times\r
- c = c & 0xf0;\r
- c |= (ANX7150_tx_pix_rpt & 0x0f);\r
- s_ANX7150_packet_config.avi_info.pb_u8[5] = c;\r
- hdmi_dbg(&client->dev, "config avi infoframe packet.\n");\r
- // Disable repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL1_AVI_RPT;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
-\r
- // Enable?wait:go\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- if (c & ANX7150_INFO_PKTCTRL1_AVI_EN)\r
- {\r
- //D("wait disable, config avi infoframe packet.\n");\r
- return exe_result; //jack wen\r
- }\r
-\r
- // load packet data to regs\r
- rc = anx7150_load_infoframe(client, ANX7150_avi_infoframe,\r
- &(s_ANX7150_packet_config.avi_info));\r
- // Enable and repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= 0x30;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
-\r
- // complete avi packet\r
- hdmi_dbg(&client->dev, "config avi infoframe packet done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~ANX7150_avi_sel;\r
-\r
- }\r
-\r
- // audio infoframe\r
- if ( info_packet_sel & ANX7150_audio_sel )\r
- {\r
- hdmi_dbg(&client->dev, "config audio infoframe packet.\n");\r
-\r
- // Disable repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
- // Enable?wait:go\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if (c & ANX7150_INFO_PKTCTRL2_AIF_EN)\r
- {\r
- //D("wait disable, config audio infoframe packet.\n");\r
- //return exe_result;//jack wen\r
- }\r
- // config packet\r
-\r
- // load packet data to regs\r
- \r
- anx7150_load_infoframe( client, ANX7150_audio_infoframe,\r
- &(s_ANX7150_packet_config.audio_info));\r
- // Enable and repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x03;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
- // complete avi packet\r
-\r
- hdmi_dbg(&client->dev, "config audio infoframe packet done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~ANX7150_audio_sel;\r
-\r
- }\r
-\r
- // config other 4 packets\r
- /*\r
-\r
- if( info_packet_sel & 0xfc )\r
- {\r
- D("other packets.\n");\r
-\r
- //find the current type need config\r
- if(info_packet_sel & ANX7150_spd_sel) type_sel = ANX7150_spd_sel;\r
- else if(info_packet_sel & ANX7150_mpeg_sel) type_sel = ANX7150_mpeg_sel;\r
- else if(info_packet_sel & ANX7150_acp_sel) type_sel = ANX7150_acp_sel;\r
- else if(info_packet_sel & ANX7150_isrc1_sel) type_sel = ANX7150_isrc1_sel;\r
- else if(info_packet_sel & ANX7150_isrc2_sel) type_sel = ANX7150_isrc2_sel;\r
- else type_sel = ANX7150_vendor_sel;\r
-\r
-\r
- // Disable repeater\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- switch(type_sel)\r
- {\r
- case ANX7150_spd_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL1_SPD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL1_SPD_EN)\r
- {\r
- D("wait disable, config spd infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_mpeg_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_MPEG_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_MPEG_EN)\r
- {\r
- D("wait disable, config mpeg infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_acp_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
- {\r
- D("wait disable, config mpeg infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_isrc1_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
- {\r
- D("wait disable, config isrc1 packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_isrc2_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
- {\r
- D("wait disable, config isrc2 packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_vendor_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
- {\r
- D("wait disable, config vendor packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- default : break;\r
- }\r
-\r
-\r
- // config packet\r
- // TODO: config packet in top level\r
-\r
- // load packet data to regs\r
- switch(type_sel)\r
- {\r
- case ANX7150_spd_sel:\r
- ANX7150_Load_Infoframe( ANX7150_spd_infoframe,\r
- &(s_ANX7150_packet_config.spd_info));\r
- D("config spd done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
- break;\r
-\r
- case ANX7150_mpeg_sel:\r
- ANX7150_Load_Infoframe( ANX7150_mpeg_infoframe,\r
- &(s_ANX7150_packet_config.mpeg_info));\r
- D("config mpeg done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x0c;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_acp_sel:\r
- ANX7150_Load_Packet( ANX7150_acp_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config acp done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x30;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_isrc1_sel:\r
- ANX7150_Load_Packet( ANX7150_isrc1_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config isrc1 done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x30;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_isrc2_sel:\r
- ANX7150_Load_Packet( ANX7150_isrc2_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config isrc2 done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_vendor_sel:\r
- ANX7150_Load_Infoframe( ANX7150_vendor_infoframe,\r
- &(s_ANX7150_packet_config.vendor_info));\r
- D("config vendor done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- default : break;\r
- }\r
-\r
- // Enable and repeater\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x03;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- // complete config packet\r
- D("config other packets done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~type_sel;\r
-\r
- }\r
- */\r
- }\r
-\r
-\r
- if ( s_ANX7150_packet_config.packets_need_config == 0x00)\r
- {\r
- hdmi_dbg(&client->dev, "config packets done\n");\r
- //ANX7150_Set_System_State(ANX7150_HDCP_AUTHENTICATION);\r
- }\r
-\r
-\r
- return exe_result;\r
-}\r
-//******************** HDCP process ********************************\r
-static int anx7150_hardware_hdcp_auth_init(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
-\r
-// ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c); //72:07.2 hdcp on\r
-// ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, (c | ANX7150_SYS_CTRL1_HDCPMODE));\r
- // disable hw hdcp\r
-// ANX7150_i2c_read_p0_reg(ANX7150_HDCP_CTRL0_REG, &c);\r
-// ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, (c & (~ANX7150_HDCP_CTRL0_HW_AUTHEN)));\r
-\r
- //ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, 0x03); //h/w auth off, jh simplay/hdcp\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //bit 0/1 off, as from start, we don't know if Bksv/srm/KSVList valid or not. SY.\r
-\r
- // DDC reset\r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- anx7150_initddc_read(client, 0x74, 0x00, 0x40, 0x01, 0x00);\r
- mdelay(5);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bcaps);\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): ANX7150_hdcp_bcaps = 0x%.2x\n", (u32)ANX7150_hdcp_bcaps);\r
-\r
- if (ANX7150_hdcp_bcaps & 0x02)\r
- { //enable 1.1 feature\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps supports 1.1\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c |= ANX7150_HDCP_CTRL1_HDCP11_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
- else\r
- { //disable 1.1 feature and enable HDCP two special point check\r
- hdmi_dbg(&client->dev, "bcaps don't support 1.1\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
- //handle repeater bit. SY.\r
- if (ANX7150_hdcp_bcaps & 0x40)\r
- {\r
- //repeater\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a repeater\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= ANX7150_HDCP_CTRL0_RX_REP;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
- else\r
- {\r
- //receiver\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a receiver\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= ~ANX7150_HDCP_CTRL0_RX_REP;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
- anx7150_rst_ddcchannel(client);\r
- ANX7150_hdcp_auth_en = 0;\r
-\r
- return rc;\r
-}\r
-static u8 anx7150_bksv_srm(struct i2c_client *client)\r
-{
- int rc = 0;\r
-#if 1
- u8 bksv[5],i,bksv_one,c1;
- anx7150_initddc_read(client, 0x74, 0x00, 0x00, 0x05, 0x00);\r
- mdelay(15);\r
- for (i = 0; i < 5; i ++)
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &bksv[i]);\r
- }
-
- bksv_one = 0;
- for (i = 0; i < 8; i++)
- {
- c1 = 0x01 << i;
- if (bksv[0] & c1)
- bksv_one ++;
- if (bksv[1] & c1)
- bksv_one ++;
- if (bksv[2] & c1)
- bksv_one ++;
- if (bksv[3] & c1)
- bksv_one ++;
- if (bksv[4] & c1)
- bksv_one ++;
- }
- //wen HDCP CTS
- if (bksv_one != 20)
- {
- hdmi_dbg(&client->dev, "BKSV check fail\n");\r
- return 0;
- }
- else
- {
- hdmi_dbg(&client->dev, "BKSV check OK\n");\r
- return 1;
- }
-#endif
-
-#if 0 //wen HDCP CTS
- /*address by gerard.zhu*/
- u8 i,j,bksv_ones_count,bksv_data[Bksv_Data_Nums] = {0};
- ANX7150_DDC_Addr bksv_ddc_addr;
- u32 bksv_length;
- ANX7150_DDC_Type ddc_type;
-
- i = 0;
- j = 0;
- bksv_ones_count = 0;
- bksv_ddc_addr.dev_addr = HDCP_Dev_Addr;
- bksv_ddc_addr.sgmt_addr = 0;
- bksv_ddc_addr.offset_addr = HDCP_Bksv_Offset;
- bksv_length = Bksv_Data_Nums;
- ddc_type = DDC_Hdcp;
-
- if (!ANX7150_DDC_Read(bksv_ddc_addr, bksv_data, bksv_length, ddc_type))
- {
- /*Judge validity for Bksv*/
- while (i < Bksv_Data_Nums)
- {
- while (j < 8)
- {
- if (((bksv_data[i] >> j) & 0x01) == 1)
- {
- bksv_ones_count++;
- }
- j++;
- }
- i++;
- j = 0;
- }
- if (bksv_ones_count != 20)
- {
- rk29printk ("!!!!BKSV 1s ¡Ù20\n"); //update rk29printk ("!!!!BKSV 1s ¡Ù20\n");
- return 0;
- }
- }
- /*end*/
-
- D("bksv is ready.\n");
- // TODO: Compare the bskv[] value to the revocation list to decide if this value is a illegal BKSV. This is system depended.
- //If illegal, return 0; legal, return 1. Now just return 1
- return 1;
-#endif
-}\r
-\r
-static u8 anx7150_is_ksvlist_vld(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
-//wen HDCP CTS\r
-#if 1\r
- hdmi_dbg(&client->dev, "ANX7150_IS_KSVList_VLD() is called.\n");\r
- anx7150_initddc_read(client, 0x74, 0x00, 0x41, 0x02, 0x00); //Bstatus, two u8s\r
- mdelay(5);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[0]);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[1]);\r
-\r
- if ((ANX7150_hdcp_bstatus[0] & 0x80) | (ANX7150_hdcp_bstatus[1] & 0x08))\r
- {\r
- hdmi_dbg(&client->dev, "Max dev/cascade exceeded: ANX7150_hdcp_bstatus[0]: 0x%x,ANX7150_hdcp_bstatus[1]:0x%x\n", (u32)ANX7150_hdcp_bstatus[0],(u32)ANX7150_hdcp_bstatus[1]);\r
- return 0;//HDCP topology error. More than 127 RX are attached or more than seven levels of repeater are cascaded.\r
- }\r
- return 1;\r
-#endif\r
-//wen HDCP CTS\r
-\r
-}\r
-\r
-static void anx7150_show_video_parameter(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- // int h_res,h_act,v_res,v_act,h_fp,hsync_width,h_bp;\r
- char c, c1;\r
-\r
- hdmi_dbg(&client->dev, "\n\n**********************************ANX7150 Info**********************************\n");\r
-\r
- hdmi_dbg(&client->dev, " ANX7150 mode = Normal mode\n");\r
- if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = YC_MUX\n");\r
- if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = 656\n");\r
- if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = YC_MUX + 656\n");\r
- if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = Seperate Sync\n");\r
- if (ANX7150_de_gen_en)\r
- hdmi_dbg(&client->dev, " DE generator = Enable\n");\r
- else\r
- hdmi_dbg(&client->dev, " DE generator = Disable\n");\r
- if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = DDR mode\n");\r
- else if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = DDR mode + 656\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c1);\r
- c1 = (c1 & 0x02);\r
- if (c1)\r
- {\r
- hdmi_dbg(&client->dev, " Output video mode = HDMI\n");\r
- rc = anx7150_i2c_read_p0_reg(client, 0x04, &c);\r
- c = (c & 0x60) >> 5;\r
- switch (c)\r
- {\r
- case ANX7150_RGB:\r
- hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
- break;\r
- case ANX7150_YCbCr422:\r
- hdmi_dbg(&client->dev, " Output video color format = YCbCr422\n");\r
- break;\r
- case ANX7150_YCbCr444:\r
- hdmi_dbg(&client->dev, " Output video color format = YCbCr444\n");\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, " Output video mode = DVI\n");\r
- hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
- }\r
-\r
- /*for(i = 0x10; i < 0x25; i ++)\r
- {\r
- ANX7150_i2c_read_p0_reg(i, &c );\r
- D("0x%.2x = 0x%.2x\n",(unsigned int)i,(unsigned int)c);\r
- }*/\r
- /* ANX7150_i2c_read_p0_reg(ANX7150_VID_STATUS_REG, &c);\r
- if((c & ANX7150_VID_STATUS_TYPE) == 0x04)\r
- D("Video Type = Interlace");\r
- else\r
- D("Video Type = Progressive");\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESH_REG, &c);\r
- h_res = c;\r
- h_res = h_res << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESL_REG, &c);\r
- h_res = h_res + c;\r
- D("H_resolution = %u\n",h_res);\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXH_REG, &c);\r
- h_act = c;\r
- h_act = h_act << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXL_REG, &c);\r
- h_act = h_act + c;\r
- D("H_active = %u\n",h_act);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESH_REG, &c);\r
- v_res = c;\r
- v_res = v_res << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESL_REG, &c);\r
- v_res = v_res + c;\r
- D("V_resolution = %u\n",v_res);\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEH_REG, &c);\r
- v_act = c;\r
- v_act = v_act << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEL_REG, &c);\r
- v_act = v_act + c;\r
- D("V_active = %u\n",v_act);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHH_REG, &c);\r
- h_fp = c;\r
- h_fp = h_fp << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHL_REG, &c);\r
- h_fp = h_fp + c;\r
- D("H_FP = %u\n",h_fp);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHH_REG, &c);\r
- h_bp = c;\r
- h_bp = h_bp << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHL_REG, &c);\r
- h_bp = h_bp + c;\r
- D("H_BP = %u\n",h_bp);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDH_REG, &c);\r
- hsync_width = c;\r
- hsync_width = hsync_width << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDL_REG, &c);\r
- hsync_width = hsync_width + c;\r
- D("Hsync_width = %u\n",hsync_width);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTLINE2VSYNC_REG, &c);\r
- D("Vsync_FP = %bu\n",c);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG, &c);\r
- D("Vsync_BP = %bu\n",c);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCWIDLINE_REG, &c);\r
- D("Vsync_width = %bu\n",c);*/\r
- {\r
- hdmi_dbg(&client->dev, " Normal mode output video format: \n");\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x480p@60\n");\r
- if (ANX7150_edid_result.supported_720x480p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- hdmi_dbg(&client->dev, "1280x720p@60\n");\r
- if (ANX7150_edid_result.supported_720p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- hdmi_dbg(&client->dev, "1920x1080i@60\n");\r
- if (ANX7150_edid_result.supported_1080i_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080p_60Hz:\r
- hdmi_dbg(&client->dev, "1920x1080p@60\n");\r
- if (ANX7150_edid_result.supported_1080p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080p_50Hz:\r
- hdmi_dbg(&client->dev, "1920x1080p@50\n");\r
- if (ANX7150_edid_result.supported_1080p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- hdmi_dbg(&client->dev, "1280x720p@50\n");\r
- if (ANX7150_edid_result.supported_720p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- hdmi_dbg(&client->dev, "1920x1080i@50\n");\r
- if (ANX7150_edid_result.supported_1080i_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x576p@50\n");\r
- if (ANX7150_edid_result.supported_576p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x576i@50\n");\r
- if (ANX7150_edid_result.supported_576i_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x480i@60\n");\r
- if (ANX7150_edid_result.supported_720x480i_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- default:\r
- hdmi_dbg(&client->dev, "unknown(video ID is: %.2x).\n",(u32)ANX7150_video_timing_id);\r
- break;\r
- }\r
- }\r
- if (c1)//HDMI output\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = c & 0x03;\r
- hdmi_dbg(&client->dev, " MCLK Frequence = ");\r
-\r
- switch (c)\r
- {\r
- case 0x00:\r
- hdmi_dbg(&client->dev, "128 * Fs.\n");\r
- break;\r
- case 0x01:\r
- hdmi_dbg(&client->dev, "256 * Fs.\n");\r
- break;\r
- case 0x02:\r
- hdmi_dbg(&client->dev, "384 * Fs.\n");\r
- break;\r
- case 0x03:\r
- hdmi_dbg(&client->dev, "512 * Fs.\n");\r
- break;\r
- default :\r
- hdmi_dbg(&client->dev, "Wrong MCLK output.\n");\r
- break;\r
- }\r
-\r
- if ( ANX7150_AUD_HW_INTERFACE == 0x01)\r
- {\r
- hdmi_dbg(&client->dev, " Input Audio Interface = I2S.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- }\r
- else if (ANX7150_AUD_HW_INTERFACE == 0x02)\r
- {\r
- hdmi_dbg(&client->dev, " Input Audio Interface = SPDIF.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
- c=c>>4;\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- hdmi_dbg(&client->dev, " Audio Fs = ");\r
- c &= 0x0f;\r
- switch (c)\r
- {\r
- case 0x00:\r
- hdmi_dbg(&client->dev, " Audio Fs = 44.1 KHz.\n");\r
- break;\r
- case 0x02:\r
- hdmi_dbg(&client->dev, " Audio Fs = 48 KHz.\n");\r
- break;\r
- case 0x03:\r
- hdmi_dbg(&client->dev, " Audio Fs = 32 KHz.\n");\r
- break;\r
- case 0x08:\r
- hdmi_dbg(&client->dev, " Audio Fs = 88.2 KHz.\n");\r
- break;\r
- case 0x0a:\r
- hdmi_dbg(&client->dev, " Audio Fs = 96 KHz.\n\n");\r
- break;\r
- case 0x0c:\r
- hdmi_dbg(&client->dev, " Audio Fs = 176.4 KHz.\n");\r
- break;\r
- case 0x0e:\r
- hdmi_dbg(&client->dev, " Audio Fs = 192 KHz.\n");\r
- hdmi_dbg(&client->dev, "192 KHz.\n");\r
- break;\r
- default :\r
- hdmi_dbg(&client->dev, " Audio Fs = Wrong Fs output.\n");\r
- hdmi_dbg(&client->dev, "Wrong Fs output.\n");\r
- break;\r
- }\r
-\r
- if (ANX7150_HDCP_enable == 1)\r
- hdmi_dbg(&client->dev, " ANX7150_HDCP_Enable.\n");\r
- else\r
- hdmi_dbg(&client->dev, " ANX7150_HDCP_Disable.\n");\r
-\r
- }\r
- hdmi_dbg(&client->dev, "\n********************************************************************************\n\n");\r
-}\r
-void ANX7150_HDCP_Process(struct i2c_client *client, int enable)\r
-{\r
- int rc = 0;\r
- char c,i;\r
- //u8 c1;\r
- u8 Bksv_valid=0;//wen HDCP CTS\r
-\r
- if (ANX7150_HDCP_enable)\r
- { //HDCP_EN =1 means to do HDCP authentication,SWITCH4 = 0 means not to do HDCP authentication.\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c | 0x04);//power on HDCP, 090630\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR2_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR2_MASK_REG, c |0x03);\r
- mdelay(10);//let unencrypted video play a while, required by HDCP CTS. SY//wen HDCP CTS\r
- anx7150_set_avmute(client);//before auth, set_avmute//wen\r
- mdelay(10);//wen HDCP CTS\r
-\r
- if ( !ANX7150_hdcp_init_done )\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= ANX7150_SYS_CTRL1_HDCPMODE;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- if (ANX7150_edid_result.is_HDMI)\r
- rc = anx7150_hardware_hdcp_auth_init(client);\r
- else\r
- { //DVI, disable 1.1 feature and enable HDCP two special point check\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
-\r
- //wen HDCP CTS\r
- if (!anx7150_bksv_srm(client))\r
- {\r
- anx7150_blue_screen_enable(client);\r
- anx7150_clear_avmute(client);\r
- Bksv_valid=0;\r
- return;\r
- }\r
- else //SY.\r
- {\r
- Bksv_valid=1;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= 0x03;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
-\r
- ANX7150_hdcp_init_done = 1;\r
-//wen HDCP CTS\r
- }\r
-\r
-\r
-//wen HDCP CTS\r
- if ((Bksv_valid) && (!ANX7150_hdcp_auth_en))\r
- {\r
- hdmi_dbg(&client->dev, "enable hw hdcp\n");\r
- anx7150_rst_ddcchannel(client);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 1;\r
- }\r
-\r
- if ((Bksv_valid) && (ANX7150_hdcp_wait_100ms_needed))\r
- {\r
- ANX7150_hdcp_wait_100ms_needed = 0;\r
- //disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- \r
- hdmi_dbg(&client->dev, "++++++++ANX7150_hdcp_wait_100ms_needed+++++++++\n");\r
- mdelay(150); // 100 -> 150\r
- return;\r
- }\r
-//wen HDCP CTS\r
-\r
- if (ANX7150_hdcp_auth_pass) //wen HDCP CTS\r
- {\r
- //Clear the SRM_Check_Pass u8, then when reauthentication occurs, firmware can catch it.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= 0xfc;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
-\r
- //Enable HDCP Hardware encryption\r
- if (!ANX7150_hdcp_encryption)\r
- {\r
- anx7150_hdcp_encryption_enable(client);\r
- }\r
- if (ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_disable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
-\r
- i = 0;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- while((c&0x04)==0x00)//wait for encryption.\r
- {\r
- mdelay(2);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- i++;\r
- if (i > 10)\r
- break;\r
- }\r
-\r
- //enable audio SY.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- hdmi_dbg(&client->dev, "@@@@@ HDCP Auth PASSED! @@@@@\n");\r
-\r
- if (ANX7150_hdcp_bcaps & 0x40) //repeater\r
- {\r
- hdmi_dbg(&client->dev, "Find a repeater!\n");\r
- //actually it is KSVList check. we can't do SRM check due to the lack of SRM file. SY.\r
- if (!ANX7150_srm_checked)\r
- {\r
- if (!anx7150_is_ksvlist_vld(client))\r
- {\r
- hdmi_dbg(&client->dev, "ksvlist not good. disable encryption");\r
- anx7150_hdcp_encryption_disable(client);\r
- anx7150_blue_screen_enable(client);\r
- anx7150_clear_avmute(client);\r
- ANX7150_ksv_srm_pass = 0;\r
- anx7150_clean_hdcp(client);//SY.\r
- //remove below will pass 1b-05/1b-06\r
- //ANX7150_Set_System_State(ANX7150_WAIT_HOTPLUG);//SY.\r
- return;\r
- }\r
- ANX7150_srm_checked=1;\r
- ANX7150_ksv_srm_pass = 1;\r
- }\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "Find a receiver.\n");\r
- }\r
- }\r
- else //wen HDCP CTS\r
- {\r
- hdmi_dbg(&client->dev, "##### HDCP Auth FAILED! #####\n");\r
- //also need to disable HW AUTHEN\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= ~ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
- //ANX7150_hdcp_init_done = 0;\r
- //ANX7150_hdcp_wait_100ms_needed = 1; //wen, update 080703\r
-\r
- if (ANX7150_hdcp_encryption)\r
- {\r
- anx7150_hdcp_encryption_disable(client);\r
- }\r
- if (!ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_enable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- \r
- return;\r
- }\r
-\r
- }\r
- else //wen HDCP CTS\r
- {\r
- hdmi_dbg(&client->dev, "hdcp pin is off.\n");\r
- if (ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_disable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
- //enable audio SY.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
-//wen HDCP CTS\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c); //72:07.1 hdmi or dvi mode\r
- c = c & 0x02;\r
- if (c == 0x02)\r
- {\r
- hdmi_dbg(&client->dev, "end of ANX7150_HDCP_Process(): in HDMI mode.\n");\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "!end of ANX7150_HDCP_Process(): in DVI mode.\n");\r
- //To-Do: Config to DVI mode.\r
- }\r
-\r
- anx7150_show_video_parameter(client);\r
- if(!enable)\r
- anx7150_set_avmute(client);\r
-}\r
-\r
-void HDMI_Set_Video_Format(u8 video_format) //CPU set the lowpower mode\r
-{ \r
- switch (video_format)\r
- {\r
- case HDMI_1280x720p_50Hz:\r
- g_video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- g_video_format = ANX7150_V1280x720p_60Hz;\r
- break;\r
- case HDMI_720x576p_50Hz_4x3:\r
- g_video_format = ANX7150_V720x576p_50Hz_4x3;\r
- break;\r
- case HDMI_720x576p_50Hz_16x9:\r
- g_video_format = ANX7150_V720x576p_50Hz_16x9;\r
- break;\r
- case HDMI_720x480p_60Hz_4x3:\r
- g_video_format = ANX7150_V720x480p_60Hz_4x3;\r
- break;\r
- case HDMI_720x480p_60Hz_16x9:\r
- g_video_format = ANX7150_V720x480p_60Hz_16x9;\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- g_video_format = ANX7150_V1920x1080p_50Hz;\r
- break;\r
- case HDMI_1920x1080p_60Hz:\r
- g_video_format = ANX7150_V1920x1080p_60Hz;\r
- break;\r
- default:\r
- g_video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- }\r
-// ANX7150_system_config_done = 0;\r
-}\r
-void HDMI_Set_Audio_Fs( u8 audio_fs) //ANX7150 call this to check lowpower\r
-{\r
- g_audio_format = audio_fs;\r
-// ANX7150_system_config_done = 0;\r
-}\r
-int ANX7150_PLAYBACK_Process(void)\r
-{\r
-// D("enter\n");\r
-\r
- if ((s_ANX7150_packet_config.packets_need_config != 0x00) && (ANX7150_edid_result.is_HDMI == 1))\r
- {\r
- return 1;\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-\r
+++ /dev/null
-#ifndef _ANX7150_HW_H\r
-#define _ANX7150_HW_H\r
-\r
-#include <linux/hdmi-new.h>\r
-extern u8 timer_slot,misc_reset_needed;\r
-extern u8 bist_switch_value_pc,switch_value;\r
-extern u8 switch_value_sw_backup,switch_value_pc_backup;\r
-extern u8 ANX7150_system_state;\r
-extern u8 ANX7150_srm_checked;\r
-extern u8 ANX7150_HDCP_enable;\r
-extern u8 ANX7150_INT_Done;\r
-extern u8 FREQ_MCLK;\r
-//extern u8 int_s1, int_s2, int_s3;\r
-extern u8 HDMI_Mode_Auto_Manual,HDMI_Lowpower_Mode;\r
-\r
-struct anx7150_interrupt_s{\r
- int hotplug_change;\r
- int video_format_change;\r
- int auth_done;\r
- int auth_state_change;\r
- int pll_lock_change;\r
- int rx_sense_change;\r
- int HDCP_link_change;\r
- int audio_clk_change;\r
- int audio_FIFO_overrun;\r
- int SPDIF_bi_phase_error;\r
- int SPDIF_error;\r
-};\r
-typedef struct\r
-{\r
- u8 is_HDMI;\r
- u8 ycbcr444_supported;\r
- u8 ycbcr422_supported;\r
- u8 supported_1080p_60Hz;\r
- u8 supported_1080p_50Hz;\r
- u8 supported_1080i_60Hz;\r
- u8 supported_1080i_50Hz;\r
- u8 supported_720p_60Hz;\r
- u8 supported_720p_50Hz;\r
- u8 supported_576p_50Hz;\r
- u8 supported_576i_50Hz;\r
- u8 supported_640x480p_60Hz;\r
- u8 supported_720x480p_60Hz;\r
- u8 supported_720x480i_60Hz;\r
- u8 AudioFormat[10];//MAX audio STD block is 10(0x1f / 3)\r
- u8 AudioChannel[10];\r
- u8 AudioFs[10];\r
- u8 AudioLength[10];\r
- u8 SpeakerFormat;u8 edid_errcode;}ANX7150_edid_result_4_system;\r
- extern ANX7150_edid_result_4_system ANX7150_edid_result;\r
-//#define ITU656\r
-//#ifdef ITU656\r
-struct ANX7150_video_timingtype{ //CEA-861C format\r
- u8 ANX7150_640x480p_60Hz[18];//format 1\r
- u8 ANX7150_720x480p_60Hz[18];//format 2 & 3\r
- u8 ANX7150_1280x720p_60Hz[18];//format 4\r
- u8 ANX7150_1920x1080i_60Hz[18];//format 5\r
- u8 ANX7150_720x480i_60Hz[18];//format 6 & 7\r
- u8 ANX7150_1920x1080p_60Hz[18];\r
- //u8 ANX7150_720x240p_60Hz[18];//format 8 & 9\r
- //u8 ANX7150_2880x480i_60Hz[18];//format 10 & 11\r
- //u8 ANX7150_2880x240p_60Hz[18];//format 12 & 13\r
- //u8 ANX7150_1440x480p_60Hz[18];//format 14 & 15\r
- //u8 ANX7150_1920x1080p_60Hz[18];//format 16\r
- u8 ANX7150_720x576p_50Hz[18];//format 17 & 18\r
- u8 ANX7150_1280x720p_50Hz[18];//format 19\r
- u8 ANX7150_1920x1080i_50Hz[18];//format 20*/\r
- u8 ANX7150_720x576i_50Hz[18];//format 21 & 22\r
- u8 ANX7150_1920x1080p_50Hz[18];\r
- /* u8 ANX7150_720x288p_50Hz[18];//formats 23 & 24\r
- u8 ANX7150_2880x576i_50Hz[18];//formats 25 & 26\r
- u8 ANX7150_2880x288p_50Hz[18];//formats 27 & 28\r
- u8 ANX7150_1440x576p_50Hz[18];//formats 29 & 30\r
- u8 ANX7150_1920x1080p_50Hz[18];//format 31\r
- u8 ANX7150_1920x1080p_24Hz[18];//format 32\r
- u8 ANX7150_1920x1080p_25Hz[18];//format 33\r
- u8 ANX7150_1920x1080p_30Hz[18];//format 34*/\r
-};\r
-//#endif\r
-// 8 type of packets are legal, It is possible to sent 6 types in the same time;\r
-// So select 6 types below at most;\r
-// avi_infoframe and audio_infoframe have fixxed address;\r
-// config other selected types of packet to the rest 4 address with no limits.\r
-typedef enum\r
-{\r
- ANX7150_avi_infoframe,\r
- ANX7150_audio_infoframe,\r
- /*ANX7150_spd_infoframe,\r
- ANX7150_mpeg_infoframe,\r
- ANX7150_acp_packet,\r
- ANX7150_isrc1_packet,\r
- ANX7150_isrc2_packet,\r
- ANX7150_vendor_infoframe,*/\r
-}packet_type;\r
-\r
-typedef struct\r
-{\r
- u8 type;\r
- u8 version;\r
- u8 length;\r
- u8 pb_u8[28];\r
-}infoframe_struct;\r
-\r
-typedef struct\r
-{\r
- u8 packets_need_config; //which infoframe packet is need updated\r
- infoframe_struct avi_info;\r
- infoframe_struct audio_info;\r
- /* for the funture use\r
- infoframe_struct spd_info;\r
- infoframe_struct mpeg_info;\r
- infoframe_struct acp_pkt;\r
- infoframe_struct isrc1_pkt;\r
- infoframe_struct isrc2_pkt;\r
- infoframe_struct vendor_info; */\r
-\r
-} config_packets;\r
-/*\r
- u8 i2s_format;\r
-\r
- u8(s) Name Type Default Description\r
- 7 EXT_VUCP R/W 0x0\r
- Enable indicator of VUCP u8s extraction from input\r
- I2S audio stream. 0 = disable; 1 = enable.\r
- 6:5 MCLK_PHS_CTRL R/W 0x0\r
- MCLK phase control for audio SPDIF input, which value\r
- is depended on the value of MCLK frequency set and not great than it.\r
- 4 Reserved\r
- 3 SHIFT_CTRL R/W 0x0\r
- WS to SD shift first u8. 0 = fist u8 shift (Philips Spec); 1 = no shift.\r
- 2 DIR_CTRL R/W 0x0\r
- SD data Indian (MSB or LSB first) control. 0 = MSB first; 1 = LSB first.\r
- 1 WS_POL R/W 0x0\r
- Word select left/right polarity select. 0 = left polarity\r
- when works select is low; 1 = left polarity when word select is high.\r
- 0 JUST_CTRL R/W 0x0\r
- SD Justification control. 1 = data is right justified;\r
- 0 = data is left justified.\r
-\r
-*/\r
-/*\r
- u8 audio_channel\r
-u8(s) Name Type Default Description\r
-5 AUD_SD3_IN R/W 0x0 Set I2S input channel #3 enable. 0 = disable; 1 = enable.\r
-4 AUD_SD2_IN R/W 0x0 Set I2S input channel #2 enable. 0 = disable; 1 = enable.\r
-3 AUD_SD1_IN R/W 0x0 Set I2S input channel #1 enable. 0 = disable; 1 = enable.\r
-2 AUD_SD0_IN R/W 0x0 Set I2S input channel #0 enable. 0 = disable; 1 = enable.\r
-\r
-\r
-*/\r
-/*\r
- u8 i2s_map0\r
-u8(s) Name Type Default Description\r
-7:6 FIFO3_SEL R/W 0x3 I2S Channel data stream select for audio FIFO 3. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-5:4 FIFO2_SEL R/W 0x2 I2S Channel data stream select for audio FIFO 2. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-3:2 FIFO1_SEL R/W 0x1 I2S Channel data stream select for audio FIFO 1. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-1:0 FIFO0_SEL R/W 0x0 I2S Channel data stream select for audio FIFO 0. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-\r
- u8 i2s_map1\r
-u8(s) Name Type Default Description\r
-7 SW3 R/W 0x0 Swap left/right channel on I2S channel 3. 1 = swap; 0 = no swap.\r
-6 SW2 R/W 0x0 Swap left/right channel on I2S channel 2. 1 = swap; 0 = no swap.\r
-5 SW1 R/W 0x0 Swap left/right channel on I2S channel 1. 1 = swap; 0 = no swap.\r
-4 SW0 R/W 0x0 Swap left/right channel on I2S channel 0. 1 = swap; 0 = no swap.\r
-3:1 IN_WORD_LEN R/W 0x5 Input I2S audio word length (corresponding to channel status u8s [35:33]). When IN_WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when IN_WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
-0 IN_WORD_MAX R/W 0x1 Input I2S audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
-*/\r
-/*\r
- u8 Channel_status1\r
-u8(s) Name Type Default Description\r
-7:6 MODE R/W 0x0 00 = PCM Audio\r
-5:3 PCM_MODE R/W 0x0 000 = 2 audio channels without pre-emphasis;\r
- 001 = 2 audio channels with 50/15 usec pre-emphasis\r
-2 SW_CPRGT R/W 0x0 0 = software for which copyright is asserted;\r
- 1 = software for which no copyright is asserted\r
-1 NON_PCM R/W 0x0 0 = audio sample word represents linear PCM samples;\r
- 1 = audio sample word used for other purposes.\r
-0 PROF_APP R/W 0x0 0 = consumer applications; 1 = professional applications.\r
-\r
- u8 Channel_status2\r
-u8(s) Name Type Default Description\r
-7:0 CAT_CODE R/W 0x0 Category code (corresponding to channel status u8s [15:8])\r
-\r
- u8 Channel_status3\r
-u8(s) Name Type Default Description\r
-7:4 CH_NUM R/W 0x0 Channel number (corresponding to channel status u8s [23:20])\r
-3:0 SOURCE_NUM R/W 0x0 Source number (corresponding to channel status u8s [19:16])\r
-\r
- u8 Channel_status4\r
-u8(s) Name Type Default Description\r
-7:6 CHNL_u81 R/W 0x0 corresponding to channels status u8s [31:30]\r
-5:4 CLK_ACCUR R/W 0x0 Clock accuracy (corresponding to channels status u8s [29:28]). These two u8s define the sampling frequency tolerance. The u8s are set in the transmitter.\r
-3:0 FS_FREQ R/W 0x0 Sampling clock frequency (corresponding to channel status u8s [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
-\r
- u8 Channel_status5\r
-u8(s) Name Type Default Description\r
-7:4 CHNL_u82 R/W 0x0 corresponding to channels status u8s [39:36]\r
-3:1 WORD_LENGTH R/W 0x5 Audio word length (corresponding to channel status u8s [35:33]). When WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
-0 WORD_MAX R/W 0x1 Audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
-\r
-*/\r
-typedef struct\r
-{\r
- u8 audio_channel;\r
- u8 i2s_format;\r
- u8 i2s_swap;\r
- u8 Channel_status1;\r
- u8 Channel_status2;\r
- u8 Channel_status3;\r
- u8 Channel_status4;\r
- u8 Channel_status5;\r
-} i2s_config_struct;\r
-/*\r
- u8 FS_FREQ;\r
-\r
- 7:4 FS_FREQ R 0x0\r
- Sampling clock frequency (corresponding to channel status u8s [27:24]).\r
- 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz;\r
- 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
-*/\r
-\r
-typedef struct\r
-{\r
- u8 one_u8_ctrl;\r
-\r
-} super_audio_config_struct;\r
-\r
-typedef struct\r
-{\r
- u8 audio_type; // audio type\r
- // #define ANX7150_i2s_input 0x01\r
- // #define ANX7150_spdif_input 0x02\r
- // #define ANX7150_super_audio_input 0x04\r
-\r
- u8 down_sample; // 0x72:0x50\r
- // 0x00: 00 no down sample\r
- // 0x20: 01 2 to 1 down sample\r
- // 0x60: 11 4 to 1 down sample\r
- // 0x40: 10 reserved\r
- u8 audio_layout;//audio layout;\r
- //0x00, 2-channel\r
- //0x80, 8-channel\r
-\r
- i2s_config_struct i2s_config;\r
- super_audio_config_struct super_audio_config;\r
-\r
-} audio_config_struct;\r
-\r
-/*added by gerard.zhu*/\r
-/*DDC type*/\r
-typedef enum {\r
- DDC_Hdcp,\r
- DDC_Edid,\r
-}ANX7150_DDC_Type;\r
-\r
-/*Read DDC status type*/\r
-typedef enum {\r
- report,\r
- Judge,\r
-}ANX7150_DDC_Status_Check_Type;\r
-\r
-/*Define DDC address struction*/\r
-typedef struct {\r
- u8 dev_addr;\r
- u8 sgmt_addr;\r
- u8 offset_addr;\r
-}ANX7150_DDC_Addr;\r
-\r
-/*DDC status u8*/\r
-#define DDC_Error_u8 0x07\r
-#define DDC_Occup_u8 0x06\r
-#define DDC_Fifo_Full_u8 0x05\r
-#define DDC_Fifo_Empt_u8 0x04\r
-#define DDC_No_Ack_u8 0x03\r
-#define DDC_Fifo_Rd_u8 0x02\r
-#define DDC_Fifo_Wr_u8 0x01\r
-#define DDC_Progress_u8 0x00\r
-\r
-#define YCbCr422 0x20\r
-#define null 0\r
-#define source_ratio 0x08\r
-\r
-/*DDC Command*/\r
-#define Abort_Current_Operation 0x00\r
-#define Sequential_u8_Read 0x01\r
-#define Sequential_u8_Write 0x02\r
-#define Implicit_Offset_Address_Read 0x3\r
-#define Enhanced_DDC_Sequenital_Read 0x04\r
-#define Clear_DDC_Fifo 0x05\r
-#define I2c_reset 0x06\r
-\r
-/*DDC result*/\r
-#define DDC_NO_Err 0x00\r
-#define DDC_Status_Err 0x01\r
-#define DDC_Data_Addr_Err 0x02\r
-#define DDC_Length_Err 0x03\r
-\r
-/*checksum result*/\r
-#define Edid_Checksum_No_Err 0x00\r
-#define Edid_Checksum_Err 0x01\r
-\r
-/*HDCP device base address*/\r
-#define HDCP_Dev_Addr 0x74\r
-\r
-/*HDCP Bksv offset*/\r
-#define HDCP_Bksv_Offset 0x00\r
-\r
-/*HDCP Bcaps offset*/\r
-#define HDCP_Bcaps_Offset 0x40\r
-\r
-/*HDCP Bstatus offset*/\r
-#define HDCP_Bstatus_offset 0x41\r
-\r
-/*HDCP KSV Fifo offset */\r
-#define HDCP_Ksv_Fifo_Offset 0x43\r
-\r
-/*HDCP bksv data nums*/\r
-#define Bksv_Data_Nums 5\r
-\r
-/*HDCP ksvs data number by defult*/\r
-#define ksvs_data_nums 50\r
-\r
-/*DDC Max u8s*/\r
-#define DDC_Max_Length 1024\r
-\r
-/*DDC fifo depth*/\r
-#define DDC_Fifo_Depth 16\r
-\r
-/*DDC read delay ms*/\r
-#define DDC_Read_Delay 3\r
-\r
-/*DDC Write delay ms*/\r
-#define DDC_Write_Delay 3\r
-/*end*/\r
-\r
-extern u8 ANX7150_parse_edid_done;\r
-extern u8 ANX7150_system_config_done;\r
-extern u8 ANX7150_video_format_config,ANX7150_video_timing_id;\r
-extern u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
-extern u8 ANX7150_ddr_edge;\r
-extern u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
-extern u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
-extern u8 ANX7150_pix_rpt_set_by_sys;\r
-extern u8 ANX7150_RGBorYCbCr;\r
-extern audio_config_struct s_ANX7150_audio_config;\r
-extern config_packets s_ANX7150_packet_config;\r
-\r
-//********************** BIST Enable***********************************\r
-\r
-\r
-#define ddr_falling_edge 1\r
-#define ddr_rising_edge 0\r
-\r
-#define input_pixel_clk_1x_repeatition 0x00\r
-#define input_pixel_clk_2x_repeatition 0x01\r
-#define input_pixel_clk_4x_repeatition 0x03\r
-\r
-//***********************Video Config***********************************\r
-#define ANX7150_RGB_YCrCb444_SepSync 0\r
-#define ANX7150_YCrCb422_SepSync 1\r
-#define ANX7150_YCrCb422_EmbSync 2\r
-#define ANX7150_YCMux422_SepSync_Mode1 3\r
-#define ANX7150_YCMux422_SepSync_Mode2 4\r
-#define ANX7150_YCMux422_EmbSync_Mode1 5\r
-#define ANX7150_YCMux422_EmbSync_Mode2 6\r
-#define ANX7150_RGB_YCrCb444_DDR_SepSync 7\r
-#define ANX7150_RGB_YCrCb444_DDR_EmbSync 8\r
-\r
-#define ANX7150_RGB_YCrCb444_SepSync_No_DE 9\r
-#define ANX7150_YCrCb422_SepSync_No_DE 10\r
-\r
-#define ANX7150_Progressive 0\r
-#define ANX7150_Interlace 0x08\r
-#define ANX7150_Neg_Hsync_pol 0x20\r
-#define ANX7150_Pos_Hsync_pol 0\r
-#define ANX7150_Neg_Vsync_pol 0x40\r
-#define ANX7150_Pos_Vsync_pol 0\r
-\r
-#define ANX7150_V640x480p_60Hz 1\r
-#define ANX7150_V720x480p_60Hz_4x3 2\r
-#define ANX7150_V720x480p_60Hz_16x9 3\r
-#define ANX7150_V1280x720p_60Hz 4\r
-#define ANX7150_V1280x720p_50Hz 19\r
-#define ANX7150_V1920x1080i_60Hz 5\r
-#define ANX7150_V1920x1080p_60Hz 16\r
-#define ANX7150_V1920x1080p_50Hz 31\r
-#define ANX7150_V1920x1080i_50Hz 20\r
-#define ANX7150_V720x480i_60Hz_4x3 6\r
-#define ANX7150_V720x480i_60Hz_16x9 7\r
-#define ANX7150_V720x576i_50Hz_4x3 21\r
-#define ANX7150_V720x576i_50Hz_16x9 22\r
-#define ANX7150_V720x576p_50Hz_4x3 17\r
-#define ANX7150_V720x576p_50Hz_16x9 18\r
-\r
-#define ANX7150_RGB 0x00\r
-#define ANX7150_YCbCr422 0x01\r
-#define ANX7150_YCbCr444 0x02\r
-#define ANX7150_CSC_BT709 1\r
-#define ANX7150_CSC_BT601 0\r
-\r
-#define ANX7150_EMBEDED_BLUE_SCREEN_ENABLE 1\r
-#define ANX7150_HDCP_FAIL_THRESHOLD 10\r
-\r
-#define ANX7150_avi_sel 0x01\r
-#define ANX7150_audio_sel 0x02\r
-#define ANX7150_spd_sel 0x04\r
-#define ANX7150_mpeg_sel 0x08\r
-#define ANX7150_acp_sel 0x10\r
-#define ANX7150_isrc1_sel 0x20\r
-#define ANX7150_isrc2_sel 0x40\r
-#define ANX7150_vendor_sel 0x80\r
-\r
-// audio type\r
-#define ANX7150_i2s_input 0x01\r
-#define ANX7150_spdif_input 0x02\r
-#define ANX7150_super_audio_input 0x04\r
-// freq_mclk\r
-#define ANX7150_mclk_128_Fs 0x00\r
-#define ANX7150_mclk_256_Fs 0x01\r
-#define ANX7150_mclk_384_Fs 0x02\r
-#define ANX7150_mclk_512_Fs 0x03\r
-// thresholds\r
-#define ANX7150_spdif_stable_th 0x03\r
-// fs -> N(ACR)\r
-#define ANX7150_N_32k 0x1000\r
-#define ANX7150_N_44k 0x1880\r
-#define ANX7150_N_88k 0x3100\r
-#define ANX7150_N_176k 0x6200\r
-#define ANX7150_N_48k 0x1800\r
-#define ANX7150_N_96k 0x3000\r
-#define ANX7150_N_192k 0x6000\r
-\r
-#define spdif_error_th 0x0a\r
-\r
-#define Hresolution_1920 1920\r
-#define Vresolution_540 540\r
-#define Vresolution_1080 1080\r
-#define Hresolution_1280 1280\r
-#define Vresolution_720 720\r
-#define Hresolution_640 640\r
-#define Vresolution_480 480\r
-#define Hresolution_720 720\r
-#define Vresolution_240 240\r
-#define Vresolution_576 576\r
-#define Vresolution_288 288\r
-#define Hz_50 50\r
-#define Hz_60 60\r
-#define Interlace_EDID 0\r
-#define Progressive_EDID 1\r
-#define ratio_16_9 1.777778\r
-#define ratio_4_3 1.333333\r
-\r
-#define ANX7150_EDID_BadHeader 0x01\r
-#define ANX7150_EDID_861B_not_supported 0x02\r
-#define ANX7150_EDID_CheckSum_ERR 0x03\r
-#define ANX7150_EDID_No_ExtBlock 0x04\r
-#define ANX7150_EDID_ExtBlock_NotFor_861B 0x05\r
-\r
-#define ANX7150_VND_IDL_REG 0x00\r
-#define ANX7150_VND_IDH_REG 0x01\r
-#define ANX7150_DEV_IDL_REG 0x02\r
-#define ANX7150_DEV_IDH_REG 0x03\r
-#define ANX7150_DEV_REV_REG 0x04\r
-\r
-#define ANX7150_SRST_REG 0x05\r
-#define ANX7150_TX_RST 0x40\r
-#define ANX7150_SRST_VIDCAP_RST 0x20 // u8 position\r
-#define ANX7150_SRST_AFIFO_RST 0x10 // u8 position\r
-#define ANX7150_SRST_HDCP_RST 0x08 // u8 position\r
-#define ANX7150_SRST_VID_FIFO_RST 0x04 // u8 position\r
-#define ANX7150_SRST_AUD_RST 0x02 // u8 position\r
-#define ANX7150_SRST_SW_RST 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_STATE_REG 0x06\r
-#define ANX7150_SYS_STATE_AUD_CLK_DET 0x20 // u8 position\r
-#define ANX7150_SYS_STATE_AVMUTE 0x10 // u8 position\r
-#define ANX7150_SYS_STATE_HP 0x08 // u8 position\r
-#define ANX7150_SYS_STATE_VSYNC 0x04 // u8 position\r
-#define ANX7150_SYS_STATE_CLK_DET 0x02 // u8 position\r
-#define ANX7150_SYS_STATE_RSV_DET 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL1_REG 0x07\r
-#define ANX7150_SYS_CTRL1_LINKMUTE_EN 0x80 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDCPHPD_RST 0x40 // u8 position\r
-#define ANX7150_SYS_CTRL1_PDINT_SEL 0x20 // u8 position\r
-#define ANX7150_SYS_CTRL1_DDC_FAST 0x10 // u8 position\r
-#define ANX7150_SYS_CTRL1_DDC_SWCTRL 0x08 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDCPMODE 0x04 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDMI 0x02 // u8 position\r
-#define ANX7150_SYS_CTRL1_PWDN_CTRL 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL2_REG 0x08\r
-#define ANX7150_SYS_CTRL2_DDC_RST 0x08 // u8 position\r
-#define ANX7150_SYS_CTRL2_TMDSBIST_RST 0x04 // u8 position\r
-#define ANX7150_SYS_CTRL2_MISC_RST 0x02 // u8 position\r
-#define ANX7150_SYS_CTRL2_HW_RST 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL3_REG 0x09\r
-#define ANX7150_SYS_CTRL3_I2C_PWON 0x02\r
-#define ANX7150_SYS_CTRL3_PWON_ALL 0x01\r
-\r
-#define ANX7150_SYS_CTRL4_REG 0x0b\r
-\r
-#define ANX7150_VID_STATUS_REG 0x10\r
-#define ANX7150_VID_STATUS_VID_STABLE 0x20 // u8 position\r
-#define ANX7150_VID_STATUS_EMSYNC_ERR 0x10 // u8 position\r
-#define ANX7150_VID_STATUS_FLD_POL 0x08 // u8 position\r
-#define ANX7150_VID_STATUS_TYPE 0x04 // u8 position\r
-#define ANX7150_VID_STATUS_VSYNC_POL 0x02 // u8 position\r
-#define ANX7150_VID_STATUS_HSYNC_POL 0x01 // u8 position\r
-\r
-#define ANX7150_VID_MODE_REG 0x11\r
-#define ANX7150_VID_MODE_CHKSHARED_EN 0x80 // u8 position\r
-#define ANX7150_VID_MODE_LINKVID_EN 0x40 // u8 position\r
-#define ANX7150_VID_MODE_RANGE_Y2R 0x20 // u8 position\r
-#define ANX7150_VID_MODE_CSPACE_Y2R 0x10 // u8 position\r
-#define ANX7150_VID_MODE_Y2R_SEL 0x08 // u8 position\r
-#define ANX7150_VID_MODE_UPSAMPLE 0x04 // u8 position\r
-\r
-#define ANX7150_VID_CTRL_REG 0x12\r
-#define ANX7150_VID_CTRL_IN_EN 0x10 // u8 position\r
-#define ANX7150_VID_CTRL_YCu8_SEL 0x08 // u8 position\r
-#define ANX7150_VID_CTRL_u8CTRL_EN 0x04 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL0_REG 0x13\r
-#define ANX7150_VID_CAPCTRL0_DEGEN_EN 0x80 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_EMSYNC_EN 0x40 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DEMUX_EN 0x20 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_INV_IDCK 0x10 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DV_BUSMODE 0x08 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DDR_EDGE 0x04 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_VIDu8_SWAP 0x02 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_VIDBIST_EN 0x01 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL1_REG 0x14\r
-#define ANX7150_VID_CAPCTRL1_FORMAT_SEL 0x80 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_VSYNC_POL 0x40 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_HSYNC_POL 0x20 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_INV_FLDPOL 0x10 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_VID_TYPE 0x08 // u8 position\r
-\r
-#define ANX7150_H_RESL_REG 0x15\r
-#define ANX7150_H_RESH_REG 0x16\r
-#define ANX7150_VID_PIXL_REG 0x17\r
-#define ANX7150_VID_PIXH_REG 0x18\r
-#define ANX7150_H_FRONTPORCHL_REG 0x19\r
-#define ANX7150_H_FRONTPORCHH_REG 0x1A\r
-#define ANX7150_HSYNC_ACT_WIDTHL_REG 0x1B\r
-#define ANX7150_HSYNC_ACT_WIDTHH_REG 0x1C\r
-#define ANX7150_H_BACKPORCHL_REG 0x1D\r
-#define ANX7150_H_BACKPORCHH_REG 0x1E\r
-#define ANX7150_V_RESL_REG 0x1F\r
-#define ANX7150_V_RESH_REG 0x20\r
-#define ANX7150_ACT_LINEL_REG 0x21\r
-#define ANX7150_ACT_LINEH_REG 0x22\r
-#define ANX7150_ACT_LINE2VSYNC_REG 0x23\r
-#define ANX7150_VSYNC_WID_REG 0x24\r
-#define ANX7150_VSYNC_TAIL2VIDLINE_REG 0x25\r
-#define ANX7150_VIDF_HRESL_REG 0x26\r
-#define ANX7150_VIDF_HRESH_REG 0x27\r
-#define ANX7150_VIDF_PIXL_REG 0x28\r
-#define ANX7150_VIDF_PIXH_REG 0x29\r
-#define ANX7150_VIDF_HFORNTPORCHL_REG 0x2A\r
-#define ANX7150_VIDF_HFORNTPORCHH_REG 0x2B\r
-#define ANX7150_VIDF_HSYNCWIDL_REG 0x2C\r
-#define ANX7150_VIDF_HSYNCWIDH_REG 0x2D\r
-#define ANX7150_VIDF_HBACKPORCHL_REG 0x2E\r
-#define ANX7150_VIDF_HBACKPORCHH_REG 0x2F\r
-#define ANX7150_VIDF_VRESL_REG 0x30\r
-#define ANX7150_VIDF_VRESH_REG 0x31\r
-#define ANX7150_VIDF_ACTVIDLINEL_REG 0x32\r
-#define ANX7150_VIDF_ACTVIDLINEH_REG 0x33\r
-#define ANX7150_VIDF_ACTLINE2VSYNC_REG 0x34\r
-#define ANX7150_VIDF_VSYNCWIDLINE_REG 0x35\r
-#define ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG 0x36\r
-\r
-//Video input data u8 control registers\r
-\r
-#define VID_u8_CTRL0 0x37 //added\r
-#define VID_u8_CTRL1 0x38\r
-#define VID_u8_CTRL2 0x39\r
-#define VID_u8_CTRL3 0x3A\r
-#define VID_u8_CTRL4 0x3B\r
-#define VID_u8_CTRL5 0x3C\r
-#define VID_u8_CTRL6 0x3D\r
-#define VID_u8_CTRL7 0x3E\r
-#define VID_u8_CTRL8 0x3F\r
-#define VID_u8_CTRL9 0x48\r
-#define VID_u8_CTRL10 0x49\r
-#define VID_u8_CTRL11 0x4A\r
-#define VID_u8_CTRL12 0x4B\r
-#define VID_u8_CTRL13 0x4C\r
-#define VID_u8_CTRL14 0x4D\r
-#define VID_u8_CTRL15 0x4E\r
-#define VID_u8_CTRL16 0x4F\r
-#define VID_u8_CTRL17 0x89\r
-#define VID_u8_CTRL18 0x8A\r
-#define VID_u8_CTRL19 0x8B\r
-#define VID_u8_CTRL20 0x8C\r
-#define VID_u8_CTRL21 0x8D\r
-#define VID_u8_CTRL22 0x8E\r
-#define VID_u8_CTRL23 0x8F\r
-\r
-\r
-#define ANX7150_INTR_STATE_REG 0x40\r
-\r
-#define ANX7150_INTR_CTRL_REG 0x41\r
-\r
-#define ANX7150_INTR_CTRL_SOFT_INTR 0x04 // u8 position\r
-#define ANX7150_INTR_CTRL_TYPE 0x02 // u8 position\r
-#define ANX7150_INTR_CTRL_POL 0x01 // u8 position\r
-\r
-#define ANX7150_INTR1_STATUS_REG 0x42\r
-#define ANX7150_INTR1_STATUS_CTS_CHG 0x80 // u8 position\r
-#define ANX7150_INTR1_STATUS_AFIFO_UNDER 0x40 // u8 position\r
-#define ANX7150_INTR1_STATUS_AFIFO_OVER 0x20 // u8 position\r
-#define ANX7150_INTR1_STATUS_SPDIF_ERR 0x10 // u8 position\r
-#define ANX7150_INTR1_STATUS_SW_INT 0x08 // u8 position\r
-#define ANX7150_INTR1_STATUS_HP_CHG 0x04 // u8 position\r
-#define ANX7150_INTR1_STATUS_CTS_OVRWR 0x02 // u8 position\r
-#define ANX7150_INTR1_STATUS_CLK_CHG 0x01 // u8 position\r
-\r
-#define ANX7150_INTR2_STATUS_REG 0x43\r
-#define ANX7150_INTR2_STATUS_ENCEN_CHG 0x80 // u8 position\r
-#define ANX7150_INTR2_STATUS_HDCPLINK_CHK 0x40 // u8 position\r
-#define ANX7150_INTR2_STATUS_HDCPENHC_CHK 0x20 // u8 position\r
-#define ANX7150_INTR2_STATUS_BKSV_RDY 0x10 // u8 position\r
-#define ANX7150_INTR2_STATUS_PLLLOCK_CHG 0x08 // u8 position\r
-#define ANX7150_INTR2_STATUS_SHA_DONE 0x04 // u8 position\r
-#define ANX7150_INTR2_STATUS_AUTH_CHG 0x02 // u8 position\r
-#define ANX7150_INTR2_STATUS_AUTH_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_INTR3_STATUS_REG 0x44\r
-#define ANX7150_INTR3_STATUS_SPDIFBI_ERR 0x80 // u8 position\r
-#define ANX7150_INTR3_STATUS_VIDF_CHG 0x40 // u8 position\r
-#define ANX7150_INTR3_STATUS_AUDCLK_CHG 0x20 // u8 position\r
-#define ANX7150_INTR3_STATUS_DDCACC_ERR 0x10 // u8 position\r
-#define ANX7150_INTR3_STATUS_DDC_NOACK 0x08 // u8 position\r
-#define ANX7150_INTR3_STATUS_VSYNC_DET 0x04 // u8 position\r
-#define ANX7150_INTR3_STATUS_RXSEN_CHG 0x02 // u8 position\r
-#define ANX7150_INTR3_STATUS_SPDIF_UNSTBL 0x01 // u8 position\r
-\r
-#define ANX7150_INTR1_MASK_REG 0x45\r
-#define ANX7150_INTR2_MASK_REG 0x46\r
-#define ANX7150_INTR3_MASK_REG 0x47\r
-\r
-#define ANX7150_HDMI_AUDCTRL0_REG 0x50\r
-#define ANX7150_HDMI_AUDCTRL0_LAYOUT 0x80 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_DOWN_SMPL 0x60 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_CTSGEN_SC 0x10 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_INV_AUDCLK 0x08 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDCTRL1_REG 0x51\r
-#define ANX7150_HDMI_AUDCTRL1_IN_EN 0x80 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN 0x40 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD3IN_EN 0x20 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD2IN_EN 0x10 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD1IN_EN 0x08 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD0IN_EN 0x04 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SPDIFFS_OVRWR 0x02 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_CLK_SEL 0x01 // u8 position\r
-\r
-#define ANX7150_I2S_CTRL_REG 0x52\r
-#define ANX7150_I2S_CTRL_VUCP 0x80 // u8 position\r
-#define SPDIF_IN_SEL 0x10 //0-spdif, 1-multi with sd0\r
-#define ANX7150_I2S_CTRL_SHIFT_CTRL 0x08 // u8 position\r
-#define ANX7150_I2S_CTRL_DIR_CTRL 0x04 // u8 position\r
-#define ANX7150_I2S_CTRL_WS_POL 0x02 // u8 position\r
-#define ANX7150_I2S_CTRL_JUST_CTRL 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_CTRL_REG 0x53\r
-#define ANX7150_I2SCH_FIFO3_SEL 0xC0 // u8 position\r
-#define ANX7150_I2SCH_FIFO2_SEL 0x30 // u8 position\r
-#define ANX7150_I2SCH_FIFO1_SEL 0x0C // u8 position\r
-#define ANX7150_I2SCH_FIFO0_SEL 0x03 // u8 position\r
-\r
-#define ANX7150_I2SCH_SWCTRL_REG 0x54\r
-\r
-#define ANX7150_I2SCH_SWCTRL_SW3 0x80 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW2 0x40 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW1 0x20 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW0 0x10 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_INWD_LEN 0xE0 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_INWD_MAX 0x01 // u8 position\r
-\r
-#define ANX7150_SPDIFCH_STATUS_REG 0x55\r
-#define ANX7150_SPDIFCH_STATUS_FS_FREG 0xF0 // u8 position\r
-#define ANX7150_SPDIFCH_STATUS_WD_LEN 0x0E // u8 position\r
-#define ANX7150_SPDIFCH_STATUS_WD_MX 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_STATUS1_REG 0x56\r
-#define ANX7150_I2SCH_STATUS1_MODE 0xC0 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_PCM_MODE 0x38 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_SW_CPRGT 0x04 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_NON_PCM 0x02 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_PROF_APP 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_STATUS2_REG 0x57\r
-\r
-#define ANX7150_I2SCH_STATUS3_REG 0x58\r
-#define ANX7150_I2SCH_STATUS3_CH_NUM 0xF0 // u8 position\r
-#define ANX7150_I2SCH_STATUS3_SRC_NUM 0x0F // u8 position\r
-\r
-\r
-\r
-#define ANX7150_I2SCH_STATUS4_REG 0x59\r
-\r
-#define ANX7150_I2SCH_STATUS5_REG 0x5A\r
-\r
-#define ANX7150_I2SCH_STATUS5_WORD_MAX 0x01 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDSTATUS_REG 0x5B\r
-\r
-#define ANX7150_HDMI_AUDSTATUS_SPDIF_DET 0x01 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDBIST_CTRL_REG 0x5C\r
-\r
-#define ANX7150_HDMI_AUDBIST_EN3 0x08 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN2 0x04 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN1 0x02 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN0 0x01 // u8 position\r
-\r
-#define ANX7150_AUD_INCLK_CNT_REG 0x5D\r
-#define ANX7150_AUD_DEBUG_STATUS_REG 0x5E\r
-\r
-#define ANX7150_ONEu8_AUD_CTRL_REG 0x60\r
-\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN7 0x80 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN6 0x40 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN5 0x20 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN4 0x10 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN3 0x08 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN2 0x04 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN1 0x02 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN0 0x01 // u8 position\r
-\r
-#define ANX7150_ONEu8_AUD0_CTRL_REG 0x61\r
-#define ANX7150_ONEu8_AUD1_CTRL_REG 0x62\r
-#define ANX7150_ONEu8_AUD2_CTRL_REG 0x63\r
-#define ANX7150_ONEu8_AUD3_CTRL_REG 0x64\r
-\r
-#define ANX7150_ONEu8_AUDCLK_CTRL_REG 0x65\r
-\r
-#define ANX7150_ONEu8_AUDCLK_DET 0x08 // u8 position\r
-\r
-#define ANX7150_SPDIF_ERR_THRSHLD_REG 0x66\r
-#define ANX7150_SPDIF_ERR_CNT_REG 0x67\r
-\r
-#define ANX7150_HDMI_LINK_CTRL_REG 0x70\r
-\r
-#define ANX7150_HDMI_LINK_DATA_MUTEEN1 0x80 // u8 position\r
-#define ANX7150_HDMI_LINK_DATA_MUTEEN0 0x40 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN2 0x20 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN1 0x10 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN0 0x08 // u8 position\r
-#define ANX7150_HDMI_LINK_DEC_DE 0x04 // u8 position\r
-#define ANX7150_HDMI_LINK_PRMB_INC 0x02 // u8 position\r
-#define ANX7150_HDMI_LINK_AUTO_PROG 0x01 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL2_REG 0x71\r
-\r
-#define ANX7150_VID_CAPCTRL2_CHK_UPDATEEN 0x10 // u8 position\r
-\r
-#define ANX7150_LINK_MUTEEE_REG 0x72\r
-\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN2 0x20 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN1 0x10 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN0 0x08 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN2 0x04 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN1 0x02 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN0 0x01 // u8 position\r
-\r
-#define ANX7150_SERDES_TEST0_REG 0x73\r
-#define ANX7150_SERDES_TEST1_REG 0x74\r
-#define ANX7150_SERDES_TEST2_REG 0x75\r
-\r
-#define ANX7150_PLL_TX_AMP 0x76\r
-\r
-\r
-#define ANX7150_DDC_SLV_ADDR_REG 0x80\r
-#define ANX7150_DDC_SLV_SEGADDR_REG 0x81\r
-#define ANX7150_DDC_SLV_OFFADDR_REG 0x82\r
-#define ANX7150_DDC_ACC_CMD_REG 0x83\r
-#define ANX7150_DDC_ACCNUM0_REG 0x84\r
-#define ANX7150_DDC_ACCNUM1_REG 0x85\r
-\r
-#define ANX7150_DDC_CHSTATUS_REG 0x86\r
-\r
-#define ANX7150_DDC_CHSTATUS_DDCERR 0x80 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_DDC_OCCUPY 0x40 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_FULL 0x20 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_EMPT 0x10 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_NOACK 0x08 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_RD 0x04 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_WR 0x02 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_INPRO 0x01 // u8 position\r
-\r
-#define ANX7150_DDC_FIFO_ACC_REG 0x87\r
-#define ANX7150_DDC_FIFOCNT_REG 0x88\r
-\r
-#define ANX7150_SYS_PD_REG 0x90\r
-#define ANX7150_SYS_PD_PLL 0x80 // u8 position\r
-#define ANX7150_SYS_PD_TMDS 0x40 // u8 position\r
-#define ANX7150_SYS_PD_TMDS_CLK 0x20 // u8 position\r
-#define ANX7150_SYS_PD_MISC 0x10 // u8 position\r
-#define ANX7150_SYS_PD_LINK 0x08 // u8 position\r
-#define ANX7150_SYS_PD_IDCK 0x04 // u8 position\r
-#define ANX7150_SYS_PD_AUD 0x02 // u8 position\r
-#define ANX7150_SYS_PD_MACRO_ALL 0x01 // u8 position\r
-\r
-#define ANX7150_LINKFSM_DEBUG0_REG 0x91\r
-#define ANX7150_LINKFSM_DEBUG1_REG 0x92\r
-\r
-#define ANX7150_PLL_CTRL0_REG 0x93\r
-#define ANX7150_PLL_CTRL0_CPREG_BLEED 0x02 // u8 position\r
-#define ANX7150_PLL_CTRL0_TEST_EN 0x01 // u8 position\r
-\r
-#define ANX7150_PLL_CTRL1_REG 0x94\r
-#define ANX7150_PLL_CTRL1_TESTEN 0x80 // u8 position\r
-\r
-#define ANX7150_OSC_CTRL_REG 0x95\r
-#define ANX7150_OSC_CTRL_TESTEN 0x80 // u8 position\r
-#define ANX7150_OSC_CTRL_SEL_BG 0x40 // u8 position\r
-\r
-#define ANX7150_TMDS_CH0_CONFIG_REG 0x96\r
-#define ANX7150_TMDS_CH0_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH0_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CHO_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CH1_CONFIG_REG 0x97\r
-#define ANX7150_TMDS_CH1_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH1_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CH1_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CH2_CONFIG_REG 0x98\r
-#define ANX7150_TMDS_CH2_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH2_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CH2_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CLKCH_CONFIG_REG 0x99\r
-#define ANX7150_TMDS_CLKCH_MUTE 0x80 // u8 position\r
-#define ANX7150_TMDS_CLKCH_TESTEN 0x08 // u8 position\r
-#define ANX7150_TMDS_CLKCH_AMP 0x07 // u8 position\r
-\r
-#define ANX7150_CHIP_CTRL_REG 0x9A\r
-#define ANX7150_CHIP_CTRL_PRBS_GENEN 0x80 // u8 position\r
-#define ANX7150_CHIP_CTRL_LINK_DBGSEL 0x70 // u8 position\r
-#define ANX7150_CHIP_CTRL_VIDCHK_EN 0x08 // u8 position\r
-#define ANX7150_CHIP_CTRL_MISC_TIMER 0x04 // u8 position\r
-#define ANX7150_CHIP_CTRL_PLL_RNG 0x02 // u8 position\r
-#define ANX7150_CHIP_CTRL_PLL_MAN 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_STATUS_REG 0x9B\r
-#define ANX7150_CHIP_STATUS_GPIO 0x80 // u8 position\r
-#define ANX7150_CHIP_STATUS_SDA 0x40 // u8 position\r
-#define ANX7150_CHIP_STATUS_SCL 0x20 // u8 position\r
-#define ANX7150_CHIP_STATUS_PLL_HSPO 0x04 // u8 position\r
-#define ANX7150_CHIP_STATUS_PLL_LOCK 0x02 // u8 position\r
-#define ANX7150_CHIP_STATUS_MISC_LOCK 0x01 // u8 position\r
-\r
-#define ANX7150_DBG_PINGPIO_CTRL_REG 0x9C\r
-#define ANX7150_DBG_PINGPIO_VDLOW_SHAREDEN 0x04 // u8 position\r
-#define ANX7150_DBG_PINGPIO_GPIO_ADDREN 0x02 // u8 position\r
-#define ANX7150_DBG_PINGPIO_GPIO_OUT 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG0_CTRL_REG 0x9D\r
-#define ANX7150_CHIP_DEBUG0_PRBS_ERR 0xE0 // u8 position\r
-#define ANX7150_CHIP_DEBUG0_CAPST 0x1F // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG1_CTRL_REG 0x9E\r
-#define ANX7150_CHIP_DEBUG1_SDA_SW 0x80 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_SCL_SW 0x40 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_SERDES_TESTEN 0x20 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_CLK_BYPASS 0x10 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_FORCE_PLLLOCK 0x08 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_PLLLOCK_BYPASS 0x04 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_FORCE_HP 0x02 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_HP_DEGLITCH 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG2_CTRL_REG 0x9F\r
-#define ANX7150_CHIP_DEBUG2_EXEMB_SYNCEN 0x04 // u8 position\r
-#define ANX7150_CHIP_DEBUG2_VIDBIST 0x02 // u8 position\r
-\r
-#define ANX7150_VID_INCLK_REG 0x5F\r
-\r
-#define ANX7150_HDCP_STATUS_REG 0xA0\r
-#define ANX7150_HDCP_STATUS_ADV_CIPHER 0x80 // u8 position\r
-#define ANX7150_HDCP_STATUS_R0_READY 0x10 // u8 position\r
-#define ANX7150_HDCP_STATUS_AKSV_ACT 0x08 // u8 position\r
-#define ANX7150_HDCP_STATUS_ENCRYPT 0x04 // u8 position\r
-#define ANX7150_HDCP_STATUS_AUTH_PASS 0x02 // u8 position\r
-#define ANX7150_HDCP_STATUS_KEY_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_CTRL0_REG 0xA1\r
-#define ANX7150_HDCP_CTRL0_STORE_AN 0x80 // u8 position\r
-#define ANX7150_HDCP_CTRL0_RX_REP 0x40 // u8 position\r
-#define ANX7150_HDCP_CTRL0_RE_AUTH 0x20 // u8 position\r
-#define ANX7150_HDCP_CTRL0_SW_AUTHOK 0x10 // u8 position\r
-#define ANX7150_HDCP_CTRL0_HW_AUTHEN 0x08 // u8 position\r
-#define ANX7150_HDCP_CTRL0_ENC_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_CTRL0_BKSV_SRM 0x02 // u8 position\r
-#define ANX7150_HDCP_CTRL0_KSV_VLD 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_CTRL1_REG 0xA2\r
-#define ANX7150_LINK_CHK_12_EN 0x40\r
-#define ANX7150_HDCP_CTRL1_DDC_NOSTOP 0x20 // u8 position\r
-#define ANX7150_HDCP_CTRL1_DDC_NOACK 0x10 // u8 position\r
-#define ANX7150_HDCP_CTRL1_EDDC_NOACK 0x08 // u8 position\r
-#define ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_CTRL1_RCV11_EN 0x02 // u8 position\r
-#define ANX7150_HDCP_CTRL1_HDCP11_EN 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_Link_Check_FRAME_NUM_REG 0xA3\r
-#define ANX7150_HDCP_AKSV1_REG 0xA5\r
-#define ANX7150_HDCP_AKSV2_REG 0xA6\r
-#define ANX7150_HDCP_AKSV3_REG 0xA7\r
-#define ANX7150_HDCP_AKSV4_REG 0xA8\r
-#define ANX7150_HDCP_AKSV5_REG 0xA9\r
-\r
-#define ANX7150_HDCP_AN1_REG 0xAA\r
-#define ANX7150_HDCP_AN2_REG 0xAB\r
-#define ANX7150_HDCP_AN3_REG 0xAC\r
-#define ANX7150_HDCP_AN4_REG 0xAD\r
-#define ANX7150_HDCP_AN5_REG 0xAE\r
-#define ANX7150_HDCP_AN6_REG 0xAF\r
-#define ANX7150_HDCP_AN7_REG 0xB0\r
-#define ANX7150_HDCP_AN8_REG 0xB1\r
-\r
-#define ANX7150_HDCP_BKSV1_REG 0xB2\r
-#define ANX7150_HDCP_BKSV2_REG 0xB3\r
-#define ANX7150_HDCP_BKSV3_REG 0xB4\r
-#define ANX7150_HDCP_BKSV4_REG 0xB5\r
-#define ANX7150_HDCP_BKSV5_REG 0xB6\r
-\r
-#define ANX7150_HDCP_RI1_REG 0xB7\r
-#define ANX7150_HDCP_RI2_REG 0xB8\r
-\r
-#define ANX7150_HDCP_PJ_REG 0xB9\r
-#define ANX7150_HDCP_RX_CAPS_REG 0xBA\r
-#define ANX7150_HDCP_BSTATUS0_REG 0xBB\r
-#define ANX7150_HDCP_BSTATUS1_REG 0xBC\r
-\r
-#define ANX7150_HDCP_AMO0_REG 0xD0\r
-#define ANX7150_HDCP_AMO1_REG 0xD1\r
-#define ANX7150_HDCP_AMO2_REG 0xD2\r
-#define ANX7150_HDCP_AMO3_REG 0xD3\r
-#define ANX7150_HDCP_AMO4_REG 0xD4\r
-#define ANX7150_HDCP_AMO5_REG 0xD5\r
-#define ANX7150_HDCP_AMO6_REG 0xD6\r
-#define ANX7150_HDCP_AMO7_REG 0xD7\r
-\r
-#define ANX7150_HDCP_DBG_CTRL_REG 0xBD\r
-\r
-#define ANX7150_HDCP_DBG_ENC_INC 0x08 // u8 position\r
-#define ANX7150_HDCP_DBG_DDC_SPEED 0x06 // u8 position\r
-#define ANX7150_HDCP_DBG_SKIP_RPT 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_KEY_STATUS_REG 0xBE\r
-#define ANX7150_HDCP_KEY_BIST_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_KEY_BIST_ERR 0x02 // u8 position\r
-#define ANX7150_HDCP_KEY_CMD_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_KEY_CMD_REGISTER 0xBF //added\r
-\r
-#define ANX7150_HDCP_AUTHDBG_STATUS_REG 0xC7\r
-#define ANX7150_HDCP_ENCRYPTDBG_STATUS_REG 0xC8\r
-#define ANX7150_HDCP_FRAME_NUM_REG 0xC9\r
-\r
-#define ANX7150_DDC_MSTR_INTER_REG 0xCA\r
-#define ANX7150_DDC_MSTR_LINK_REG 0xCB\r
-\r
-#define ANX7150_HDCP_BLUESCREEN0_REG 0xCC\r
-#define ANX7150_HDCP_BLUESCREEN1_REG 0xCD\r
-#define ANX7150_HDCP_BLUESCREEN2_REG 0xCE\r
-// DEV_ADDR = 0x7A or 0x7E\r
-#define ANX7150_INFO_PKTCTRL1_REG 0xC0\r
-#define ANX7150_INFO_PKTCTRL1_SPD_RPT 0x80 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_SPD_EN 0x40 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_AVI_RPT 0x20 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_AVI_EN 0x10 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_GCP_RPT 0x08 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_GCP_EN 0x04 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_ACR_NEW 0x02 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_ACR_EN 0x01 // u8 position\r
-\r
-#define ANX7150_INFO_PKTCTRL2_REG 0xC1\r
-#define ANX7150_INFO_PKTCTRL2_UD1_RPT 0x80 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD1_EN 0x40 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD0_RPT 0x20 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD0_EN 0x10 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_MPEG_RPT 0x08 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_MPEG_EN 0x04 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_AIF_RPT 0x02 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_AIF_EN 0x01 // u8 position\r
-\r
-#define ANX7150_ACR_N1_SW_REG 0xC2\r
-#define ANX7150_ACR_N2_SW_REG 0xC3\r
-#define ANX7150_ACR_N3_SW_REG 0xC4\r
-\r
-#define ANX7150_ACR_CTS1_SW_REG 0xC5\r
-#define ANX7150_ACR_CTS2_SW_REG 0xC6\r
-#define ANX7150_ACR_CTS3_SW_REG 0xC7\r
-\r
-#define ANX7150_ACR_CTS1_HW_REG 0xC8\r
-#define ANX7150_ACR_CTS2_HW_REG 0xC9\r
-#define ANX7150_ACR_CTS3_HW_REG 0xCA\r
-\r
-#define ANX7150_ACR_CTS_CTRL_REG 0xCB\r
-\r
-#define ANX7150_GNRL_CTRL_PKT_REG 0xCC\r
-#define ANX7150_GNRL_CTRL_CLR_AVMUTE 0x02 // u8 position\r
-#define ANX7150_GNRL_CTRL_SET_AVMUTE 0x01 // u8 position\r
-\r
-#define ANX7150_AUD_PKT_FLATCTRL_REG 0xCD\r
-#define ANX7150_AUD_PKT_AUTOFLAT_EN 0x80 // u8 position\r
-#define ANX7150_AUD_PKT_FLAT 0x07 // u8 position\r
-\r
-\r
-//select video hardware interface\r
-#define ANX7150_VID_HW_INTERFACE 0x03//0x00:RGB and YcbCr 4:4:4 Formats with Separate Syncs (24-bpp mode)\r
- //0x01:YCbCr 4:2:2 Formats with Separate Syncs(16-bbp)\r
- //0x02:YCbCr 4:2:2 Formats with Embedded Syncs(No HS/VS/DE)\r
- //0x03:YC Mux 4:2:2 Formats with Separate Sync Mode1(u815:8 and u8 3:0 are used)\r
- //0x04:YC Mux 4:2:2 Formats with Separate Sync Mode2(u811:0 are used)\r
- //0x05:YC Mux 4:2:2 Formats with Embedded Sync Mode1(u815:8 and u8 3:0 are used)\r
- //0x06:YC Mux 4:2:2 Formats with Embedded Sync Mode2(u811:0 are used)\r
- //0x07:RGB and YcbCr 4:4:4 DDR Formats with Separate Syncs\r
- //0x08:RGB and YcbCr 4:4:4 DDR Formats with Embedded Syncs\r
- //0x09:RGB and YcbCr 4:4:4 Formats with Separate Syncs but no DE\r
- //0x0a:YCbCr 4:2:2 Formats with Separate Syncs but no DE\r
-//select input color space\r
-#define ANX7150_INPUT_COLORSPACE 0x01//0x00: input color space is RGB\r
- //0x01: input color space is YCbCr422\r
- //0x02: input color space is YCbCr444\r
-//select input pixel clock edge for DDR mode\r
-#define ANX7150_IDCK_EDGE_DDR 0x00 //0x00:use rising edge to latch even numbered pixel data//jack wen\r
- //0x01:use falling edge to latch even numbered pixel data\r
-\r
-//select audio hardware interface\r
-#define ANX7150_AUD_HW_INTERFACE 0x01//0x01:audio input comes from I2S\r
- //0x02:audio input comes from SPDIF\r
- //0x04:audio input comes from one u8 audio\r
-//select MCLK and Fs relationship if audio HW interface is I2S\r
-#define ANX7150_MCLK_Fs_RELATION 0x01//0x00:MCLK = 128 * Fs\r
- //0x01:MCLK = 256 * Fs\r
- //0x02:MCLK = 384 * Fs\r
- //0x03:MCLK = 512 * Fs //wen updated error\r
-\r
-#define ANX7150_AUD_CLK_EDGE 0x00 //0x00:use MCLK and SCK rising edge to latch audio data\r
- //0x08, revised by wen. //0x80:use MCLK and SCK falling edge to latch audio data\r
-//select I2S channel numbers if audio HW interface is I2S\r
-#define ANX7150_I2S_CH0_ENABLE 0x01 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH1_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH2_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH3_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-//select I2S word length if audio HW interface is I2S\r
-#define ANX7150_I2S_WORD_LENGTH 0x0b\r
- //0x02 = 16u8s; 0x04 = 18 u8s; 0x08 = 19 u8s; 0x0a = 20 u8s(maximal word length is 20u8s); 0x0c = 17 u8s;\r
- // 0x03 = 20u8s(maximal word length is 24u8s); 0x05 = 22 u8s; 0x09 = 23 u8s; 0x0b = 24 u8s; 0x0d = 21 u8s;\r
-\r
-//select I2S format if audio HW interface is I2S\r
-#define ANX7150_I2S_SHIFT_CTRL 0x00//0x00: fist u8 shift(philips spec)\r
- //0x01:no shift\r
-#define ANX7150_I2S_DIR_CTRL 0x00//0x00:SD data MSB first\r
- //0x01:LSB first\r
-#define ANX7150_I2S_WS_POL 0x00//0x00:left polarity when word select is low\r
- //0x01:left polarity when word select is high\r
-#define ANX7150_I2S_JUST_CTRL 0x00//0x00:data is left justified\r
- //0x01:data is right justified\r
-\r
-#define EDID_Parse_Enable 1 // cwz 0 for test, 1 normal\r
-//InfoFrame and Control Packet Registers\r
-// 0x7A or 0X7E\r
-/*\r
-#define AVI_HB0 0x00\r
-#define AVI_HB1 0x01\r
-#define AVI_HB2 0x02\r
-#define AVI_PB0 0x03\r
-#define AVI_PB1 0x04\r
-#define AVI_PB2 0x05\r
-#define AVI_PB3 0x06\r
-#define AVI_PB4 0x07\r
-#define AVI_PB5 0x08\r
-#define AVI_PB6 0x09\r
-#define AVI_PB7 0x0A\r
-#define AVI_PB8 0x0B\r
-#define AVI_PB9 0x0C\r
-#define AVI_PB10 0x0D\r
-#define AVI_PB11 0x0E\r
-#define AVI_PB12 0x0F\r
-#define AVI_PB13 0x10\r
-#define AVI_PB14 0x11\r
-#define AVI_PB15 0x12\r
-\r
-#define AUD_HBO 0x20\r
-#define AUD_HB1 0x21\r
-#define AUD_HB2 0x22\r
-#define AUD_PB0 0x23\r
-#define AUD_PB1 0x24\r
-#define AUD_PB2 0x25\r
-#define AUD_PB3 0x26\r
-#define AUD_PB4 0x27\r
-#define AUD_PB5 0x28\r
-#define AUD_PB6 0x29\r
-#define AUD_PB7 0x2A\r
-#define AUD_PB8 0x2B\r
-#define AUD_PB9 0x2C\r
-#define AUD_PB10 0x2D\r
-\r
-#define SPD_HBO 0x40\r
-#define SPD_HB1 0x41\r
-#define SPD_HB2 0x42\r
-#define SPD_PB0 0x43\r
-#define SPD_PB1 0x44\r
-#define SPD_PB2 0x45\r
-#define SPD_PB3 0x46\r
-#define SPD_PB4 0x47\r
-#define SPD_PB5 0x48\r
-#define SPD_PB6 0x49\r
-#define SPD_PB7 0x4A\r
-#define SPD_PB8 0x4B\r
-#define SPD_PB9 0x4C\r
-#define SPD_PB10 0x4D\r
-#define SPD_PB11 0x4E\r
-#define SPD_PB12 0x4F\r
-#define SPD_PB13 0x50\r
-#define SPD_PB14 0x51\r
-#define SPD_PB15 0x52\r
-#define SPD_PB16 0x53\r
-#define SPD_PB17 0x54\r
-#define SPD_PB18 0x55\r
-#define SPD_PB19 0x56\r
-#define SPD_PB20 0x57\r
-#define SPD_PB21 0x58\r
-#define SPD_PB22 0x59\r
-#define SPD_PB23 0x5A\r
-#define SPD_PB24 0x5B\r
-#define SPD_PB25 0x5C\r
-#define SPD_PB26 0x5D\r
-#define SPD_PB27 0x5E\r
-\r
-#define MPEG_HBO 0x60\r
-#define MPEG_HB1 0x61\r
-#define MPEG_HB2 0x62\r
-#define MPEG_PB0 0x63\r
-#define MPEG_PB1 0x64\r
-#define MPEG_PB2 0x65\r
-#define MPEG_PB3 0x66\r
-#define MPEG_PB4 0x67\r
-#define MPEG_PB5 0x68\r
-#define MPEG_PB6 0x69\r
-#define MPEG_PB7 0x6A\r
-#define MPEG_PB8 0x6B\r
-#define MPEG_PB9 0x6C\r
-#define MPEG_PB10 0x6D\r
-#define MPEG_PB11 0x6E\r
-#define MPEG_PB12 0x6F\r
-#define MPEG_PB13 0x70\r
-#define MPEG_PB14 0x71\r
-#define MPEG_PB15 0x72\r
-#define MPEG_PB16 0x73\r
-#define MPEG_PB17 0x74\r
-#define MPEG_PB18 0x75\r
-#define MPEG_PB19 0x76\r
-#define MPEG_PB20 0x77\r
-#define MPEG_PB21 0x78\r
-#define MPEG_PB22 0x79\r
-#define MPEG_PB23 0x7A\r
-#define MPEG_PB24 0x7B\r
-#define MPEG_PB25 0x7C\r
-#define MPEG_PB26 0x7D\r
-#define MPEG_PB27 0x7E\r
-\r
-#define USRDF0_HBO 0x80\r
-#define USRDF0_HB1 0x81\r
-#define USRDF0_HB2 0x82\r
-#define USRDF0_PB0 0x83\r
-#define USRDF0_PB1 0x84\r
-#define USRDF0_PB2 0x85\r
-#define USRDF0_PB3 0x86\r
-#define USRDF0_PB4 0x87\r
-#define USRDF0_PB5 0x88\r
-#define USRDF0_PB6 0x89\r
-#define USRDF0_PB7 0x8A\r
-#define USRDF0_PB8 0x8B\r
-#define USRDF0_PB9 0x8C\r
-#define USRDF0_PB10 0x8D\r
-#define USRDF0_PB11 0x8E\r
-#define USRDF0_PB12 0x8F\r
-#define USRDF0_PB13 0x90\r
-#define USRDF0_PB14 0x91\r
-#define USRDF0_PB15 0x92\r
-#define USRDF0_PB16 0x93\r
-#define USRDF0_PB17 0x94\r
-#define USRDF0_PB18 0x95\r
-#define USRDF0_PB19 0x96\r
-#define USRDF0_PB20 0x97\r
-#define USRDF0_PB21 0x98\r
-#define USRDF0_PB22 0x99\r
-#define USRDF0_PB23 0x9A\r
-#define USRDF0_PB24 0x9B\r
-#define USRDF0_PB25 0x9C\r
-#define USRDF0_PB26 0x9D\r
-#define USRDF0_PB27 0x9E\r
-\r
-#define USRDF1_HBO 0xA0\r
-#define USRDF1_HB1 0xA1\r
-#define USRDF1_HB2 0xA2\r
-#define USRDF1_PB0 0xA3\r
-#define USRDF1_PB1 0xA4\r
-#define USRDF1_PB2 0xA5\r
-#define USRDF1_PB3 0xA6\r
-#define USRDF1_PB4 0xA7\r
-#define USRDF1_PB5 0xA8\r
-#define USRDF1_PB6 0xA9\r
-#define USRDF1_PB7 0xAA\r
-#define USRDF1_PB8 0xAB\r
-#define USRDF1_PB9 0xAC\r
-#define USRDF1_PB10 0xAD\r
-#define USRDF1_PB11 0xAE\r
-#define USRDF1_PB12 0xAF\r
-#define USRDF1_PB13 0xB0\r
-#define USRDF1_PB14 0xB1\r
-#define USRDF1_PB15 0xB2\r
-#define USRDF1_PB16 0xB3\r
-#define USRDF1_PB17 0xB4\r
-#define USRDF1_PB18 0xB5\r
-#define USRDF1_PB19 0xB6\r
-#define USRDF1_PB20 0xB7\r
-#define USRDF1_PB21 0xB8\r
-#define USRDF1_PB22 0xB9\r
-#define USRDF1_PB23 0xBA\r
-#define USRDF1_PB24 0xBB\r
-#define USRDF1_PB25 0xBC\r
-#define USRDF1_PB26 0xBD\r
-#define USRDF1_PB27 0xBE\r
-*/\r
- int anx7150_get_hpd(struct i2c_client *client);\r
-\r
-void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF);\r
-int anx7150_detect_device(struct anx7150_pdata *anx);\r
-u8 ANX7150_Get_System_State(void);\r
-int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state);\r
-int anx7150_unplug(struct i2c_client *client);\r
-int anx7150_plug(struct i2c_client *client);\r
-int ANX7150_API_Initial(struct i2c_client *client);\r
-void ANX7150_Shutdown(struct i2c_client *client);\r
-int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev);\r
-int ANX7150_GET_SENSE_STATE(struct i2c_client *client);\r
-int ANX7150_Get_Optimal_resolution(int resolution_set);\r
-void HDMI_Set_Video_Format(u8 video_format);\r
-void HDMI_Set_Audio_Fs( u8 audio_fs);\r
-void ANX7150_API_System_Config(void);\r
-u8 ANX7150_Config_Audio(struct i2c_client *client);\r
-u8 ANX7150_Config_Packet(struct i2c_client *client);\r
-void ANX7150_HDCP_Process(struct i2c_client *client,int enable);\r
-int ANX7150_PLAYBACK_Process(void);\r
-void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state);\r
-int ANX7150_Config_Video(struct i2c_client *client);\r
-int ANX7150_GET_RECIVER_TYPE(void);\r
-void HDMI_Set_Video_Format(u8 video_format);\r
-void HDMI_Set_Audio_Fs( u8 audio_fs);\r
-int ANX7150_PLAYBACK_Process(void);\r
-int ANX7150_Blue_Screen(struct anx7150_pdata *anx);\r
-int anx7150_set_avmute(struct i2c_client *client);\r
-\r
-\r
-#endif\r
+++ /dev/null
-#include <linux/hdmi-new.h>
-
-extern void rk29_backlight_set(bool on);
-void hdmi_set_backlight(int on)
-{
- rk29_backlight_set(on);
-}
\ No newline at end of file
+++ /dev/null
-#include <linux/hdmi-new.h>
-extern void codec_set_spk(bool on);
-
-int hdmi_codec_set_audio_fs(unsigned char audio_fs)
-{
- return 0;
-}
-void hdmi_set_spk(int on)
-{
- codec_set_spk(!on);
-}
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/delay.h>\r
-#include <linux/module.h>\r
-#include <linux/err.h>\r
-\r
-#include <linux/hdmi-new.h>\r
-\r
-struct class *hdmi_class;\r
-struct hdmi_id_ref_info {\r
- struct hdmi *hdmi;\r
- int id;\r
- int ref;\r
-}ref_info[HDMI_MAX_ID];\r
-#ifdef CONFIG_SYSFS\r
-\r
-extern int hdmi_create_attrs(struct hdmi *hdmi);\r
-extern void hdmi_remove_attrs(struct hdmi *hdmi);\r
-\r
-#else\r
-\r
-static inline int hdmi_create_attrs(struct hdmi *hdmi)\r
-{ return 0; }\r
-static inline void hdmi_remove_attrs(struct hdmi *hdmi) {}\r
-\r
-#endif /* CONFIG_SYSFS */\r
-\r
-\r
-void hdmi_changed(struct hdmi *hdmi, int msec)\r
-{\r
- schedule_delayed_work(&hdmi->changed_work, msecs_to_jiffies(msec));\r
-}\r
-int hdmi_suspend(struct hdmi *hdmi)\r
-{\r
- flush_delayed_work(&hdmi->changed_work);\r
- return hdmi->ops->shutdown(hdmi);\r
-}\r
-int hdmi_resume(struct hdmi *hdmi)\r
-{\r
- hdmi_changed(hdmi, 1);\r
-\r
- return 0;\r
-}\r
-\r
-static void hdmi_changed_work(struct work_struct *work)\r
-{\r
- int precent, ret = 0;\r
- struct hdmi *hdmi = container_of(work, struct hdmi,\r
- changed_work.work);\r
-\r
- precent = hdmi->ops->hdmi_precent(hdmi);\r
- hdmi_dbg(hdmi->dev, "hdmi %s\n", (precent)?"insert" : "remove");\r
-\r
- if(precent)\r
- ret = hdmi->ops->insert(hdmi);\r
- else\r
- ret = hdmi->ops->remove(hdmi);\r
- if(ret < 0)\r
- dev_dbg(hdmi->dev, "hdmi changed error\n");\r
- kobject_uevent(&hdmi->dev->kobj, KOBJ_CHANGE);\r
-}\r
-\r
-void *hdmi_priv(struct hdmi *hdmi)\r
-{\r
- return (void *)hdmi->priv;\r
-}\r
-\r
-struct hdmi *hdmi_register(int extra, struct device *parent)\r
-{\r
- int rc = 0, i;\r
- char name[8];\r
- struct hdmi *hdmi = kzalloc(sizeof(struct hdmi)+ extra, GFP_KERNEL);\r
-\r
- if(!hdmi)\r
- return NULL;\r
- for(i = 0; i < HDMI_MAX_ID; i++) \r
- {\r
- if(ref_info[i].ref == 0)\r
- {\r
- ref_info[i].ref = 1;\r
- hdmi->id = i;\r
- break;\r
- }\r
- }\r
- if(i == HDMI_MAX_ID)\r
- {\r
- kfree(hdmi);\r
- return NULL;\r
- }\r
- sprintf(name, "hdmi-%d", hdmi->id);\r
- \r
- hdmi->dev = device_create(hdmi_class, parent, 0,\r
- "%s", name);\r
- if (IS_ERR(hdmi->dev)) {\r
- rc = PTR_ERR(hdmi->dev);\r
- goto dev_create_failed;\r
- }\r
-\r
- dev_set_drvdata(hdmi->dev, hdmi);\r
- ref_info[i].hdmi = hdmi;\r
-\r
- INIT_DELAYED_WORK(&hdmi->changed_work, hdmi_changed_work);\r
-\r
- rc = hdmi_create_attrs(hdmi);\r
- if (rc)\r
- goto create_attrs_failed;\r
-\r
- goto success;\r
-\r
-create_attrs_failed:\r
- device_unregister(hdmi->dev);\r
-dev_create_failed:\r
- hdmi_remove_attrs(hdmi);\r
- kfree(hdmi);\r
- return NULL;\r
-success:\r
- return hdmi;\r
-}\r
-void hdmi_unregister(struct hdmi *hdmi)\r
-{\r
- int id;\r
-\r
- if(!hdmi)\r
- return;\r
- id = hdmi->id;\r
- flush_scheduled_work();\r
- hdmi_remove_attrs(hdmi);\r
- device_unregister(hdmi->dev);\r
-\r
- kfree(hdmi);\r
- hdmi = NULL;\r
- ref_info[id].ref = 0;\r
- ref_info[id].hdmi = NULL;\r
-}\r
-struct hdmi *get_hdmi_struct(int nr)\r
-{\r
- if(ref_info[nr].ref == 0)\r
- return NULL;\r
- else\r
- return ref_info[nr].hdmi;\r
-}\r
-int hdmi_is_insert(void)\r
-{\r
- struct hdmi *hdmi = get_hdmi_struct(0);\r
-\r
- if(hdmi && hdmi->ops && hdmi->ops->hdmi_precent)\r
- return hdmi->ops->hdmi_precent(hdmi);\r
- else\r
- return 0;\r
-}\r
-static int __init hdmi_class_init(void)\r
-{\r
- int i;\r
- \r
- hdmi_class = class_create(THIS_MODULE, "hdmi");\r
-\r
- if (IS_ERR(hdmi_class))\r
- return PTR_ERR(hdmi_class);\r
- for(i = 0; i < HDMI_MAX_ID; i++) {\r
- ref_info[i].id = i;\r
- ref_info[i].ref = 0;\r
- ref_info[i].hdmi = NULL;\r
- }\r
- return 0;\r
-}\r
-\r
-static void __exit hdmi_class_exit(void)\r
-{\r
- class_destroy(hdmi_class);\r
-}\r
-EXPORT_SYMBOL(hdmi_changed);\r
-EXPORT_SYMBOL(hdmi_register);\r
-EXPORT_SYMBOL(hdmi_unregister);\r
-EXPORT_SYMBOL(get_hdmi_struct);\r
-\r
-subsys_initcall(hdmi_class_init);\r
-module_exit(hdmi_class_exit);\r
-\r
+++ /dev/null
-#include <linux/console.h>
-#include <linux/fb.h>
-
-#include <linux/completion.h>
-#include "../../display/screen/screen.h"
-#include <linux/hdmi-new.h>
-#include "../../rk29_fb.h"
-
-
-/* Base */
-#define LCD_ACLK 500000000// 312000000
-
-#define OUT_TYPE SCREEN_HDMI
-#define OUT_FACE OUT_P888
-#define DCLK_POL 1
-#define SWAP_RB 0
-
-
-/* 720p@50Hz Timing */
-#define OUT_CLK0 74250000
-#define H_PW0 40
-#define H_BP0 220
-#define H_VD0 1280
-#define H_FP0 440
-#define V_PW0 5
-#define V_BP0 20
-#define V_VD0 720
-#define V_FP0 5
-
-/* 720p@60Hz Timing */
-#define OUT_CLK1 74250000
-#define H_PW1 40
-#define H_BP1 220
-#define H_VD1 1280
-#define H_FP1 110
-#define V_PW1 5
-#define V_BP1 20
-#define V_VD1 720
-#define V_FP1 5
-
-/* 576p@50Hz Timing */
-#define OUT_CLK2 27000000
-#define H_PW2 64
-#define H_BP2 68
-#define H_VD2 720
-#define H_FP2 12
-#define V_PW2 5
-#define V_BP2 39
-#define V_VD2 576
-#define V_FP2 5
-
-/* 720x480p@60Hz Timing */
-#define OUT_CLK3 27000000
-#define H_PW3 62
-#define H_BP3 60
-#define H_VD3 720
-#define H_FP3 16
-#define V_PW3 5
-#define V_BP3 35
-#define V_VD3 480
-#define V_FP3 5
-
-/* 1080p@50Hz Timing */
-#define OUT_CLK5 148500000
-#define H_PW4 44
-#define H_BP4 148
-#define H_VD4 1920
-#define H_FP4 528
-#define V_PW4 5
-#define V_BP4 35
-#define V_VD4 1080
-#define V_FP4 5
-
-/* 1080p@60Hz Timing */
-#define OUT_CLK4 148500000
-#define H_PW5 44
-#define H_BP5 148
-#define H_VD5 1920
-#define H_FP5 88
-#define V_PW5 5
-#define V_BP5 35
-#define V_VD5 1080
-#define V_FP5 5
-
-
-extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable );
-
-static int anx7150_init(void)
-{
- return 0;
-}
-
-static int anx7150_standby(u8 enable)
-{
- return 0;
-}
-
-
-struct rk29fb_screen hdmi_info[] = {
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD0,
- .y_res = V_VD0,
- .pixclock = OUT_CLK0,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP0,
- .right_margin = H_FP0,
- .hsync_len = H_PW0,
- .upper_margin = V_BP0,
- .lower_margin = V_FP0,
- .vsync_len = V_PW0,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_1280x720p_50Hz
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD1,
- .y_res = V_VD1,
- .pixclock = OUT_CLK1,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP1,
- .right_margin = H_FP1,
- .hsync_len = H_PW1,
- .upper_margin = V_BP1,
- .lower_margin = V_FP1,
- .vsync_len = V_PW1,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_1280x720p_60Hz
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD2,
- .y_res = V_VD2,
- .pixclock = OUT_CLK2,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP2,
- .right_margin = H_FP2,
- .hsync_len = H_PW2,
- .upper_margin = V_BP2,
- .lower_margin = V_FP2,
- .vsync_len = V_PW2,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_720x576p_50Hz_4x3
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD2,
- .y_res = V_VD2,
- .pixclock = OUT_CLK2,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP2,
- .right_margin = H_FP2,
- .hsync_len = H_PW2,
- .upper_margin = V_BP2,
- .lower_margin = V_FP2,
- .vsync_len = V_PW2,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_720x576p_50Hz_16x9
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD3,
- .y_res = V_VD3,
- .pixclock = OUT_CLK3,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP3,
- .right_margin = H_FP3,
- .hsync_len = H_PW3,
- .upper_margin = V_BP3,
- .lower_margin = V_FP3,
- .vsync_len = V_PW3,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_720x480p_60Hz_4x3
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD3,
- .y_res = V_VD3,
- .pixclock = OUT_CLK3,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP3,
- .right_margin = H_FP3,
- .hsync_len = H_PW3,
- .upper_margin = V_BP3,
- .lower_margin = V_FP3,
- .vsync_len = V_PW3,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_720x480p_60Hz_16x9
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD4,
- .y_res = V_VD4,
- .pixclock = OUT_CLK4,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP4,
- .right_margin = H_FP4,
- .hsync_len = H_PW4,
- .upper_margin = V_BP4,
- .lower_margin = V_FP4,
- .vsync_len = V_PW4,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_1920x1080p_50Hz
- {
- .type = OUT_TYPE,
- .face = OUT_FACE,
- .x_res = H_VD5,
- .y_res = V_VD5,
- .pixclock = OUT_CLK5,
- .lcdc_aclk = LCD_ACLK,
- .left_margin = H_BP5,
- .right_margin = H_FP5,
- .hsync_len = H_PW5,
- .upper_margin = V_BP5,
- .lower_margin = V_FP5,
- .vsync_len = V_PW5,
- .pin_hsync = 0,
- .pin_vsync = 0,
- .pin_den = 0,
- .pin_dclk = DCLK_POL,
- .swap_rb = SWAP_RB,
- .swap_rg = 0,
- .swap_gb = 0,
- .swap_delta = 0,
- .swap_dumy = 0,
- .init = anx7150_init,
- .standby = anx7150_standby,
- }, //HDMI_1920x1080p_60Hz
-};
-
-int hdmi_switch_fb(struct hdmi *hdmi, int type)
-{
- int rc = 0;
-
- switch(hdmi->resolution)
- {
- case HDMI_1280x720p_50Hz:
- rc = FB_Switch_Screen(&hdmi_info[0], type);
- break;
- case HDMI_1280x720p_60Hz:
- rc = FB_Switch_Screen(&hdmi_info[1], type);
- break;
- case HDMI_720x576p_50Hz_4x3:
- rc = FB_Switch_Screen(&hdmi_info[2], type);
- break;
- case HDMI_720x576p_50Hz_16x9:
- rc = FB_Switch_Screen(&hdmi_info[3], type);
- break;
- case HDMI_720x480p_60Hz_4x3:
- rc = FB_Switch_Screen(&hdmi_info[4], type);
- break;
- case HDMI_720x480p_60Hz_16x9:
- rc = FB_Switch_Screen(&hdmi_info[5], type);
- break;
- case HDMI_1920x1080p_50Hz:
- rc = FB_Switch_Screen(&hdmi_info[6], type);
- break;
- case HDMI_1920x1080p_60Hz:
- rc = FB_Switch_Screen(&hdmi_info[7], type);
- break;
- default:
- rc = FB_Switch_Screen(&hdmi_info[0], type);
- break;
- }
- if(hdmi->wait == 1) {
- complete(&hdmi->complete);
- hdmi->wait = 0;
- }
- return rc;
-}
-int hdmi_resolution_changed(struct hdmi *hdmi, int xres, int yres, int video_on)
-{
- int ret = 0;
- if(!hdmi->display_on || !hdmi->ops->hdmi_precent(hdmi) || !hdmi->auto_switch)
- return 0;
- if(xres > 1280 && hdmi->resolution != HDMI_1920x1080p_50Hz)
- {
- hdmi->resolution = HDMI_1920x1080p_50Hz;
- hdmi->display_on = 1;
- hdmi->ops->set_param(hdmi);
- ret = 1;
- }
-
-
- else if(xres >1024 && xres <= 1280 && hdmi->resolution != HDMI_1280x720p_50Hz){
- hdmi->resolution = HDMI_1280x720p_50Hz;
- hdmi->display_on = 1;
- hdmi->ops->set_param(hdmi);
- ret = 1;
- }
- /*
- else {
- if(hdmi->display_on == 1)
- hdmi->hdmi_display_off(hdmi);
- }*/
- return ret;
-}
-
-int hdmi_get_default_resolution(void *screen)
-{
- memcpy((struct rk29fb_screen*)screen, &hdmi_info[HDMI_DEFAULT_RESOLUTION], sizeof(struct rk29fb_screen));
- return 0;
-}
-
-
-EXPORT_SYMBOL(hdmi_resolution_changed);
+++ /dev/null
-#include <linux/ctype.h>\r
-#include <linux/hdmi-new.h>\r
-#include <linux/string.h>\r
-\r
-\r
-static ssize_t hdmi_show_state_attrs(struct device *dev,\r
- struct device_attribute *attr,\r
- char *buf) \r
-{\r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
-\r
- return sprintf(buf, "display_on=%d\n"\r
- "plug=%d\n"\r
- "auto_switch=%d\n"\r
- "hdcp_on=%d\n"\r
- "audio_fs=%d\n"\r
- "resolution=%d\n"\r
- "--------------------------\n"\r
- "resolution support:\n"\r
- "HDMI_1280x720p_50Hz 0\n"\r
- "HDMI_1280x720p_60Hz 1\n"\r
- "HDMI_720x576p_50Hz_4x3 2\n"\r
- "HDMI_720x576p_50Hz_16x9 3\n"\r
- "HDMI_720x480p_60Hz_4x3 4\n"\r
- "HDMI_720x480p_60Hz_16x9 5\n"\r
- "HDMI_1920x1080p_50Hz 6\n"\r
- "HDMI_1920x1080p_60Hz 7\n"\r
- "--------------------------\n", \r
- hdmi->display_on,hdmi->ops->hdmi_precent(hdmi),\r
- hdmi->auto_switch, hdmi->hdcp_on,\r
- hdmi->audio_fs, hdmi->resolution);\r
-}\r
-static ssize_t hdmi_restore_state_attrs(struct device *dev, \r
- struct device_attribute *attr,\r
- const char *buf, size_t size)\r
-{\r
- int ret = 0;\r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
- char *p;\r
- const char *q;\r
- int auto_switch = -1, hdcp_on = -1, audio_fs = -1, resolution = -1;\r
- \r
- q = buf;\r
- do\r
- {\r
- if((p = strstr(q, "auto_switch=")) != NULL)\r
- {\r
- q = p + 12;\r
- if((sscanf(q, "%d", &auto_switch) == 1) &&\r
- (auto_switch == 0 || auto_switch == 1))\r
- hdmi->auto_switch = auto_switch;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- ret = -EINVAL;\r
- goto exit;\r
- }\r
- }\r
- else if((p = strstr(q, "hdcp_on=")) != NULL)\r
- {\r
- q = p + 8;\r
- if((sscanf(q, "%d", &hdcp_on) == 1) &&\r
- (hdcp_on == 0 || hdcp_on == 1))\r
- hdmi->hdcp_on = hdcp_on;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- ret = -EINVAL;\r
- goto exit;\r
- }\r
- }\r
- else if((p = strstr(q, "audio_fs=")) != NULL)\r
- {\r
- q = p + 9;\r
- if((sscanf(q, "%d", &audio_fs) == 1) &&\r
- (audio_fs >= 0))\r
- hdmi->audio_fs = audio_fs;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- ret = -EINVAL;\r
- goto exit;\r
- }\r
- }\r
- else if((p = strstr(q, "resolution=")) != NULL)\r
- {\r
- q = p + 11;\r
- if((sscanf(q, "%d", &resolution) == 1) &&\r
- (resolution >= 0))\r
- hdmi->resolution = resolution;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- ret = -EINVAL;\r
- goto exit;\r
- }\r
- }\r
- else\r
- break;\r
- \r
- }while(*q != 0);\r
- if(auto_switch == -1 &&\r
- hdcp_on == -1 &&\r
- audio_fs == -1 &&\r
- resolution == -1)\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- ret = -EINVAL;\r
- goto exit;\r
- }\r
- if(hdmi->ops->set_param)\r
- ret = hdmi->ops->set_param(hdmi);\r
- else\r
- {\r
- dev_err(dev, "hdmi device is not exist\n");\r
- return ret = 0;\r
- }\r
-exit:\r
- if(ret < 0)\r
- dev_err(dev, "hdmi_restore_state_attrs err\n");\r
- return size;\r
-}\r
-\r
-static ssize_t hdmi_show_switch_attrs(struct device *dev,\r
- struct device_attribute *attr,\r
- char *buf) \r
-{ \r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
-\r
- return sprintf(buf, "%d\n", hdmi->display_on);\r
-}\r
-static ssize_t hdmi_restore_switch_attrs(struct device *dev, \r
- struct device_attribute *attr,\r
- const char *buf, size_t size)\r
-{\r
- int display_on = 0, ret = 0;\r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
- \r
- sscanf(buf, "%d", &display_on);\r
-\r
- if(hdmi->display_on == HDMI_DISABLE && display_on)\r
- ret = hdmi->ops->display_on(hdmi);\r
- else if(hdmi->display_on == HDMI_ENABLE && !display_on)\r
- ret = hdmi->ops->display_off(hdmi);\r
-\r
- if(ret < 0)\r
- dev_err(dev, "hdmi_restore_switch_attrs err\n");\r
- return size;\r
-}\r
-static struct device_attribute hdmi_attrs[] = {\r
- __ATTR(state, 0664, hdmi_show_state_attrs, hdmi_restore_state_attrs),\r
- __ATTR(enable, 0664, hdmi_show_switch_attrs, hdmi_restore_switch_attrs),\r
-};\r
-\r
-int hdmi_create_attrs(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
- int i;\r
-\r
- for (i = 0; i < ARRAY_SIZE(hdmi_attrs); i++) {\r
- rc = device_create_file(hdmi->dev, &hdmi_attrs[i]);\r
- if (rc)\r
- goto create_failed;\r
- }\r
-\r
- goto succeed;\r
-\r
-create_failed:\r
- while (i--)\r
- device_remove_file(hdmi->dev, &hdmi_attrs[i]);\r
-succeed:\r
- return rc;\r
-}\r
-\r
-void hdmi_remove_attrs(struct hdmi *hdmi)\r
-{\r
- int i;\r
-\r
- for (i = 0; i < ARRAY_SIZE(hdmi_attrs); i++)\r
- device_remove_file(hdmi->dev, &hdmi_attrs[i]);\r
-}\r
-\r
-\r
+++ /dev/null
-#
-# Display drivers configuration
-#
-
-source "drivers/video/hdmi/hdmi-old/chips/Kconfig"
+++ /dev/null
-obj-y += hdmi-core.o hdmi-sysfs.o hdmi-fb.o hdmi-codec.o
-obj-y += chips/
+++ /dev/null
-choice
- prompt "HDMI chips select"
-config ANX7150
- bool "anx7150"
-config ANX9030
- bool "anx9030"
-endchoice
+++ /dev/null
-obj-$(CONFIG_ANX7150) += anx7150_hw.o anx7150.o
-
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/delay.h>\r
-#include <linux/module.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/hdmi.h>\r
-#include <linux/i2c.h>\r
-#include <linux/interrupt.h>\r
-#include <mach/gpio.h>\r
-#include <mach/iomux.h>\r
-\r
-#include "anx7150.h"\r
-#include "anx7150_hw.h"\r
-\r
-int anx7150_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR0;\r
- return i2c_master_reg8_recv(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-int anx7150_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR0;\r
- return i2c_master_reg8_send(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-int anx7150_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR1;\r
- return i2c_master_reg8_recv(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- client->addr = ANX7150_I2C_ADDR1;\r
- return i2c_master_reg8_send(client, reg, val, 1, ANX7150_SCL_RATE) > 0? 0: -EINVAL;\r
-}\r
-\r
-static int rk29_hdmi_enter(struct anx7150_dev_s *dev)\r
-{\r
- if(dev->rk29_output_status == RK29_OUTPUT_STATUS_LCD) {\r
- dev->hdmi->resolution = dev->resolution_set;\r
- if(hdmi_switch_fb(dev->hdmi, 1) < 0)\r
- return -1;\r
- dev->rk29_output_status = RK29_OUTPUT_STATUS_HDMI;\r
- }\r
- return 0;\r
-}\r
-static int rk29_hdmi_exit(struct anx7150_dev_s *dev)\r
-{\r
- if(dev->rk29_output_status == RK29_OUTPUT_STATUS_HDMI) {\r
- dev->hdmi->resolution = dev->resolution_set;\r
- if(hdmi_switch_fb(dev->hdmi, 0) < 0)\r
- return -1;\r
- dev->rk29_output_status = RK29_OUTPUT_STATUS_LCD;\r
- }\r
- return 0;\r
-}\r
-\r
-static int anx7150_display_on(struct hdmi* hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- rk29_hdmi_enter(&anx->dev);\r
- hdmi->display_on = HDMI_ENABLE;\r
- anx->dev.hdmi_enable = HDMI_ENABLE;\r
- anx->dev.parameter_config = 1;\r
- hdmi_dbg(hdmi->dev, "hdmi display on\n");\r
- return 0;\r
-}\r
-static int anx7150_display_off(struct hdmi* hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
- \r
- rk29_hdmi_exit(&anx->dev);\r
- hdmi->display_on = HDMI_DISABLE;\r
- anx->dev.hdmi_enable = HDMI_DISABLE;\r
- anx->dev.parameter_config = 1;\r
- hdmi_dbg(hdmi->dev, "hdmi display off\n");\r
- return 0;\r
-}\r
-static int anx7150_set_param(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- anx->dev.resolution_set = hdmi->resolution;\r
- anx->dev.i2s_Fs = hdmi->audio_fs;\r
- anx->dev.hdcp_enable = hdmi->hdcp_on;\r
- anx->dev.hdmi_auto_switch = hdmi->auto_switch;\r
- anx->dev.parameter_config = 1;\r
-\r
- return 0;\r
-}\r
-static int anx7150_core_init(struct hdmi *hdmi)\r
-{\r
- //struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- return 0;\r
-}\r
-static irqreturn_t anx7150_detect_irq(int irq, void *dev_id)\r
-{\r
- //struct hdmi *hdmi = (struct hdmi *)dev_id;\r
-\r
- return IRQ_HANDLED;\r
-}\r
-\r
-void anx7150_task(struct anx7150_pdata *anx)\r
-{\r
- int state;\r
- int ret;\r
- \r
- //anx->dev.anx7150_detect = anx7150_detect_device(anx);\r
- if(anx->dev.anx7150_detect == 0)\r
- goto out;\r
- \r
- state = ANX7150_Get_System_State();\r
-\r
- if(anx->dev.parameter_config){\r
- if(state > WAIT_HDMI_ENABLE)\r
- state = WAIT_HDMI_ENABLE;\r
- anx->dev.parameter_config = 0;\r
- anx->dev.fb_switch_state = 1;\r
- }\r
- if(anx->dev.hdmi_enable == HDMI_DISABLE && anx->dev.hdmi_auto_switch == HDMI_DISABLE){\r
- //if(state > WAIT_HDMI_ENABLE)\r
- state = HDMI_INITIAL;\r
- }\r
-\r
- state = ANX7150_Interrupt_Process(anx, state);\r
-\r
- switch(state){\r
- case HDMI_INITIAL:\r
- if(anx->dev.hdmi_auto_switch)\r
- rk29_hdmi_exit(&anx->dev);\r
- ANX7150_API_Initial(anx->client);\r
- state = WAIT_HOTPLUG;\r
- if(anx->dev.hdmi_auto_switch)\r
- anx->dev.rate = 1;\r
- else\r
- anx->dev.rate = 100;\r
- break;\r
- \r
- case WAIT_HOTPLUG:\r
- if(anx->dev.hdmi_auto_switch)\r
- rk29_hdmi_exit(&anx->dev);\r
- if(anx->dev.HPD_status){\r
- anx7150_plug(anx->client);\r
- hdmi_changed(anx->dev.hdmi, 1);\r
- state = READ_PARSE_EDID;\r
- }\r
- if(anx->dev.hdmi_auto_switch)\r
- anx->dev.rate = 50;\r
- else\r
- anx->dev.rate = 100;\r
- break;\r
- \r
- case READ_PARSE_EDID:\r
- ret = ANX7150_Parse_EDID(anx->client,&anx->dev);\r
- if(ret != 0){\r
- dev_err(&anx->client->dev, "Parse_EDID err, ret=%d\n", ret);\r
- }\r
-\r
- state = WAIT_RX_SENSE;\r
- if(anx->dev.hdmi_auto_switch)\r
- anx->dev.rate = 50;\r
- else\r
- anx->dev.rate = 100;\r
-\r
- break;\r
- \r
- case WAIT_RX_SENSE:\r
- if(ANX7150_GET_SENSE_STATE(anx->client) == 1){\r
- hdmi_dbg(&anx->client->dev, "reciver active\n");\r
- state = WAIT_HDMI_ENABLE;\r
- anx->dev.reciver_status = HDMI_RECIVER_ACTIVE;\r
- hdmi_changed(anx->dev.hdmi, 1);\r
- }\r
-\r
- if(anx->dev.hdmi_auto_switch)\r
- anx->dev.rate = 50;\r
- else\r
- anx->dev.rate = 100;\r
-\r
- break;\r
-\r
- case WAIT_HDMI_ENABLE:\r
- if(!anx->dev.hdmi_enable && anx->dev.hdmi_auto_switch)\r
- rk29_hdmi_exit(&anx->dev);\r
- if(anx->dev.hdmi_enable && \r
- (anx->dev.hdmi_auto_switch || anx->init ||anx->dev.parameter_config)) {\r
- rk29_hdmi_enter(&anx->dev);\r
- anx->init = 0;\r
- }\r
- \r
- /*\r
- if(1 || anx->dev.rk29_output_status == RK29_OUTPUT_STATUS_HDMI){\r
- state = SYSTEM_CONFIG;\r
- anx->dev.rate = 1;\r
- }\r
- */\r
- state = SYSTEM_CONFIG;\r
- if(anx->dev.hdmi_auto_switch)\r
- anx->dev.rate = 50;\r
- else\r
- anx->dev.rate = 100;\r
-\r
- break;\r
- \r
- case SYSTEM_CONFIG:\r
- anx->dev.resolution_real = ANX7150_Get_Optimal_resolution(anx->dev.resolution_set);\r
- HDMI_Set_Video_Format(anx->dev.resolution_real);\r
- HDMI_Set_Audio_Fs(anx->dev.i2s_Fs);\r
- ANX7150_API_HDCP_ONorOFF(anx->dev.hdcp_enable);\r
- ANX7150_API_System_Config();\r
- state = CONFIG_VIDEO;\r
-\r
- anx->dev.rate = 1;\r
- if(anx->dev.fb_switch_state && anx->dev.rk29_output_status == RK29_OUTPUT_STATUS_HDMI) {\r
- anx->dev.rk29_output_status = RK29_OUTPUT_STATUS_LCD;\r
- rk29_hdmi_enter(&anx->dev);\r
- anx->dev.fb_switch_state = 0;\r
- }\r
- break;\r
- \r
- case CONFIG_VIDEO:\r
- if(ANX7150_Config_Video(anx->client) == 0){\r
- if(ANX7150_GET_RECIVER_TYPE() == 1)\r
- state = CONFIG_AUDIO;\r
- else\r
- state = HDCP_AUTHENTICATION;\r
-\r
- anx->dev.rate = 50;\r
- }\r
-\r
- anx->dev.rate = 10;\r
- break;\r
- \r
- case CONFIG_AUDIO:\r
- ANX7150_Config_Audio(anx->client);\r
- state = CONFIG_PACKETS;\r
- anx->dev.rate = 1;\r
- break;\r
- \r
- case CONFIG_PACKETS:\r
- ANX7150_Config_Packet(anx->client);\r
- state = HDCP_AUTHENTICATION;\r
- anx->dev.rate = 1;\r
- break;\r
- \r
- case HDCP_AUTHENTICATION:\r
- ANX7150_HDCP_Process(anx->client);\r
- state = PLAY_BACK;\r
- anx->dev.rate = 100;\r
- break;\r
- \r
- case PLAY_BACK:\r
- ret = ANX7150_PLAYBACK_Process();\r
- if(ret == 1){\r
- state = CONFIG_PACKETS;\r
- anx->dev.rate = 1;\r
- }\r
-\r
- anx->dev.rate = 100;\r
- break;\r
- \r
- default:\r
- state = HDMI_INITIAL;\r
- anx->dev.rate = 100;\r
- break;\r
- }\r
-\r
- if(state != ANX7150_Get_System_State()){\r
- ANX7150_Set_System_State(anx->client, state);\r
- }\r
-\r
-out:\r
- return;\r
-}\r
-\r
-static void anx7150_work_func(struct work_struct * work)\r
-{\r
- struct anx7150_dev_s *dev = container_of((void *)work, struct anx7150_dev_s, delay_work);\r
- struct hdmi *hdmi = dev->hdmi;\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- anx7150_task(anx);\r
-/*\r
- if(dev->hdmi_auto_switch)\r
- {\r
- if(dev->HPD_status == HDMI_RECIVER_PLUG)\r
- {\r
- rk29_hdmi_enter(dev);\r
- }\r
- else\r
- {\r
- rk29_hdmi_exit(dev);\r
- }\r
- }\r
- else\r
- {\r
- if(dev->hdmi_enable)\r
- {\r
- rk29_hdmi_enter(dev);\r
- }\r
- else\r
- {\r
- rk29_hdmi_exit(dev);\r
- }\r
- }\r
-*/\r
- if(dev->anx7150_detect)\r
- {\r
- queue_delayed_work(dev->workqueue, &dev->delay_work, dev->rate);\r
- }\r
- else\r
- {\r
- hdmi_dbg(hdmi->dev, "ANX7150 not exist!\n");\r
- rk29_hdmi_exit(dev);\r
- }\r
- return;\r
-}\r
-static int anx7150_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)\r
-{\r
- int rc = 0;\r
- struct hdmi *hdmi = NULL;\r
- struct anx7150_pdata *anx = NULL;\r
-\r
- hdmi = kzalloc(sizeof(struct hdmi), GFP_KERNEL);\r
- if (!hdmi)\r
- {\r
- dev_err(&client->dev, "no memory for state\n");\r
- return -ENOMEM;\r
- }\r
- anx = kzalloc(sizeof(struct anx7150_pdata), GFP_KERNEL);\r
- if(!anx)\r
- {\r
- dev_err(&client->dev, "no memory for state\n");\r
- goto err_kzalloc_anx;\r
- }\r
- anx->client = client;\r
- anx->dev.anx7150_detect = 0;\r
- anx->dev.resolution_set = HDMI_DEFAULT_RESOLUTION;\r
- anx->dev.i2s_Fs = HDMI_I2S_DEFAULT_Fs;\r
- anx->dev.hdmi_enable = HDMI_ENABLE;\r
- anx->dev.hdmi_auto_switch = HDMI_AUTO_SWITCH;\r
- anx->dev.reciver_status = HDMI_RECIVER_INACTIVE;\r
- anx->dev.HPD_status = HDMI_RECIVER_UNPLUG;\r
- anx->dev.HPD_change_cnt = 0;\r
- anx->dev.rk29_output_status = RK29_OUTPUT_STATUS_LCD;\r
- anx->dev.hdcp_enable = ANX7150_HDCP_EN;\r
- anx->dev.rate = 100;\r
-\r
- anx->init = 1;\r
-\r
- anx->dev.workqueue = create_singlethread_workqueue("ANX7150_WORKQUEUE");\r
- INIT_DELAYED_WORK(&anx->dev.delay_work, anx7150_work_func);\r
- \r
- hdmi->display_on = anx->dev.hdmi_enable;\r
- hdmi->auto_switch = anx->dev.hdmi_auto_switch;\r
- hdmi->hdcp_on = anx->dev.hdcp_enable;\r
- hdmi->audio_fs = anx->dev.i2s_Fs;\r
- hdmi->resolution = anx->dev.resolution_set;\r
- hdmi->dev = &client->dev;\r
- hdmi->hdmi_display_on = anx7150_display_on;\r
- hdmi->hdmi_display_off = anx7150_display_off;\r
- hdmi->hdmi_set_param = anx7150_set_param;\r
- hdmi->hdmi_core_init = anx7150_core_init;\r
- \r
- if((rc = hdmi_register(&client->dev, hdmi)) < 0)\r
- {\r
- dev_err(&client->dev, "fail to register hdmi\n");\r
- goto err_hdmi_register;\r
- }\r
-\r
- if((rc = gpio_request(client->irq, "hdmi gpio")) < 0)\r
- {\r
- dev_err(&client->dev, "fail to request gpio %d\n", client->irq);\r
- goto err_request_gpio;\r
- }\r
-\r
- anx->irq = gpio_to_irq(client->irq);\r
- anx->gpio = client->irq;\r
-\r
- anx->dev.hdmi = hdmi;\r
- hdmi_set_privdata(hdmi, anx);\r
-\r
- i2c_set_clientdata(client, anx);\r
- gpio_pull_updown(client->irq,GPIOPullUp);\r
- \r
- if((rc = request_irq(anx->irq, anx7150_detect_irq,IRQF_TRIGGER_FALLING,NULL,hdmi)) <0)\r
- {\r
- dev_err(&client->dev, "fail to request hdmi irq\n");\r
- goto err_request_irq;\r
- }\r
- anx->dev.anx7150_detect = anx7150_detect_device(anx);\r
- if(anx->dev.anx7150_detect) {\r
- ANX7150_API_Initial(client);\r
- queue_delayed_work(anx->dev.workqueue, &anx->dev.delay_work, 200);\r
- }\r
- dev_info(&client->dev, "anx7150 i2c probe ok\n");\r
- return 0;\r
- \r
-err_request_irq:\r
- gpio_free(client->irq);\r
-err_request_gpio:\r
- hdmi_unregister(hdmi);\r
-err_hdmi_register:\r
- destroy_workqueue(anx->dev.workqueue);\r
- kfree(anx);\r
- anx = NULL;\r
-err_kzalloc_anx:\r
- kfree(hdmi);\r
- hdmi = NULL;\r
- return rc;\r
-\r
-}\r
-\r
-static int __devexit anx7150_i2c_remove(struct i2c_client *client)\r
-{\r
- struct anx7150_pdata *anx = (struct anx7150_pdata *)i2c_get_clientdata(client);\r
- struct hdmi *hdmi = anx->dev.hdmi;\r
-\r
- free_irq(anx->irq, NULL);\r
- gpio_free(client->irq);\r
- hdmi_unregister(hdmi);\r
- destroy_workqueue(anx->dev.workqueue);\r
- kfree(anx);\r
- anx = NULL;\r
- kfree(hdmi);\r
- hdmi = NULL;\r
- \r
- hdmi_dbg(hdmi->dev, "%s\n", __func__);\r
- return 0;\r
-}\r
-\r
-static const struct i2c_device_id anx7150_id[] = {\r
- { "anx7150", 0 },\r
- { }\r
-};\r
-\r
-static struct i2c_driver anx7150_i2c_driver = {\r
- .driver = {\r
- .name = "anx7150",\r
- .owner = THIS_MODULE,\r
- },\r
- .probe = &anx7150_i2c_probe,\r
- .remove = &anx7150_i2c_remove,\r
- .id_table = anx7150_id,\r
-};\r
-\r
-\r
-static int __init anx7150_init(void)\r
-{\r
- return i2c_add_driver(&anx7150_i2c_driver);\r
-}\r
-\r
-static void __exit anx7150_exit(void)\r
-{\r
- i2c_del_driver(&anx7150_i2c_driver);\r
-}\r
-\r
-//module_init(anx7150_init);\r
-fs_initcall(anx7150_init);\r
-module_exit(anx7150_exit);\r
-\r
-\r
+++ /dev/null
-#ifndef _ANX7150_H\r
-#define _ANX7150_H\r
-\r
-#include <linux/hdmi.h>\r
-\r
-#define ANX7150_I2C_ADDR0 0X39\r
-#define ANX7150_I2C_ADDR1 0X3d\r
-\r
-#define ANX7150_SCL_RATE 100 * 1000\r
-\r
-/* HDMI STATUS */\r
-#define HDMI_DISABLE 0\r
-#define HDMI_ENABLE 1\r
-\r
-/* HDMI auto switch */\r
-#define HDMI_AUTO_SWITCH HDMI_ENABLE\r
-\r
-/* HDMI reciver status */\r
-#define HDMI_RECIVER_INACTIVE 0\r
-#define HDMI_RECIVER_ACTIVE 1\r
-\r
-/* ANX7150 reciver HPD Status */\r
-#define HDMI_RECIVER_UNPLUG 0\r
-#define HDMI_RECIVER_PLUG 1\r
-\r
-#define LCD 0\r
-#define HDMI 1\r
-\r
-#define RK29_OUTPUT_STATUS_LCD LCD\r
-#define RK29_OUTPUT_STATUS_HDMI HDMI\r
-\r
-/* HDMI HDCP ENABLE */\r
-#define ANX7150_HDCP_EN HDMI_DISABLE\r
-\r
-/* ANX7150 state machine */\r
-enum{\r
- HDMI_INITIAL = 1,\r
- WAIT_HOTPLUG,\r
- READ_PARSE_EDID,\r
- WAIT_RX_SENSE,\r
- WAIT_HDMI_ENABLE,\r
- SYSTEM_CONFIG,\r
- CONFIG_VIDEO,\r
- CONFIG_AUDIO,\r
- CONFIG_PACKETS,\r
- HDCP_AUTHENTICATION,\r
- PLAY_BACK,\r
- RESET_LINK,\r
- UNKNOWN,\r
-};\r
-\r
-\r
-struct anx7150_dev_s{\r
- struct i2c_driver *i2c_driver;\r
- struct fasync_struct *async_queue;\r
- struct workqueue_struct *workqueue;\r
- struct delayed_work delay_work;\r
- struct miscdevice *mdev;\r
- void (*notifier_callback)(struct anx7150_dev_s *);\r
- int anx7150_detect;\r
- int resolution_set;\r
- int resolution_real;\r
- int i2s_Fs;\r
- int hdmi_enable;\r
- int hdmi_auto_switch;\r
- int reciver_status;\r
- int HPD_change_cnt;\r
- int HPD_status;\r
- int rk29_output_status;\r
- int hdcp_enable;\r
- int parameter_config;\r
- int rate;\r
- int fb_switch_state;\r
-\r
- struct hdmi *hdmi;\r
-};\r
-\r
-struct anx7150_pdata {\r
- int irq;\r
- int gpio;\r
- int init;\r
- struct i2c_client *client;\r
- struct anx7150_dev_s dev;\r
-};\r
-\r
-\r
-\r
-int anx7150_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val);\r
-int anx7150_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val);\r
-int anx7150_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val);\r
-int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val);\r
-\r
-#endif\r
+++ /dev/null
-#include <linux/delay.h>\r
-#include <linux/i2c.h>\r
-#include <linux/hdmi.h>\r
-\r
-\r
-#include "anx7150.h"\r
-#include "anx7150_hw.h"\r
-//#ifdef ITU656\r
-struct ANX7150_video_timingtype ANX7150_video_timingtype_table =\r
-{\r
- //640x480p-60hz\r
- {0x20/*H_RES_LOW*/, 0x03/*H_RES_HIGH*/,0x80 /*ACT_PIX_LOW*/,0x02 /*ACT_PIX_HIGH*/,\r
- 0x60/*HSYNC_WIDTH_LOW*/,0x00 /*HSYNC_WIDTH_HIGH*/,0x30 /*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/,0x02 /*VSYNC_WIDTH*/, 0x21/*V_BP_LINE*/,\r
- 0x0a/*V_FP_LINE*/,0x10 /*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720x480p-60hz\r
- {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x3c/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x06/*VSYNC_WIDTH*/, 0x1e/*V_BP_LINE*/,\r
- 0x09/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720p-60hz\r
- {0x72/*H_RES_LOW*/, 0x06/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
- 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0x6e/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //1080i-60hz\r
- {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //720x480i-60hz\r
- {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x39/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x13/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol}, //update\r
- //1080p-60hz\r
- {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //576p-50hz\r
- {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x40/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x44/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0x40/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x27/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720p-50hz\r
- {0xbc/*H_RES_LOW*/, 0x07/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
- 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0xb8/*H_FP_LOW*/, 0x01/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //1080i-50hz\r
- {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //576i-50hz\r
- {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3f/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x45/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0x40/*ACT_LINE_LOW*/,0x02 /*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x13/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- \r
- //1080p-50hz\r
- {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
-};\r
-//#endif\r
-int anx7150_mass_read_need_delay = 0;\r
-\r
-u8 g_video_format = 0x00;\r
-u8 g_audio_format = 0x00;\r
-\r
-\r
-u8 timer_slot = 0;\r
-u8 ANX7150_EDID_Buf[256];\r
-u8 ANX7150_avi_data[19];//, ANX7150_avi_checksum;\r
-u8 ANX7150_system_state = HDMI_INITIAL;\r
-u8 spdif_error_cnt = 0x00;\r
-u8 misc_reset_needed;\r
-u8 ANX7150_stdaddr,ANX7150_stdreg,ANX7150_ext_block_num;\r
-u8 ANX7150_svd_length,ANX7150_sau_length;\r
-u8 ANX7150_edid_dtd[18];\r
-u32 ANX7150_edid_length;\r
-ANX7150_edid_result_4_system ANX7150_edid_result;\r
-\r
-u8 ANX7150_ddc_fifo_full;\r
-u8 ANX7150_ddc_progress;\r
-u8 ANX7150_hdcp_auth_en;\r
-//u8 ANX7150_bksv_ready; //replace by srm_checked xy 01.09\r
-u8 ANX7150_HDCP_enable;\r
-u8 ANX7150_ksv_srm_pass;\r
-u8 ANX7150_hdcp_bcaps;\r
-u8 ANX7150_hdcp_bstatus[2];\r
-u8 ANX7150_srm_checked;\r
-u8 ANX7150_hdcp_auth_pass;\r
-u8 ANX7150_avmute_enable;\r
-u8 ANX7150_send_blue_screen;\r
-u8 ANX7150_hdcp_encryption;\r
-u8 ANX7150_hdcp_init_done;\r
-u8 ANX7150_hdcp_wait_100ms_needed;\r
-u8 ANX7150_auth_fully_pass;\r
-u8 ANX7150_parse_edid_done;//060714 XY\r
-//u8 testen;\r
-//u8 ANX7150_avi_data[19], ANX7150_avi_checksum;\r
-u8 ANX7150_hdcp_auth_fail_counter ;\r
-\r
-u8 ANX7150_video_format_config;\r
-u8 ANX7150_emb_sync_mode,ANX7150_de_gen_en,ANX7150_demux_yc_en,ANX7150_ddr_bus_mode;\r
-u8 ANX7150_ddr_edge,ANX7150_ycmux_u8_sel;\r
-u8 ANX7150_system_config_done;\r
-u8 ANX7150_RGBorYCbCr; //modified by zy 060814\r
-u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
-u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
-u8 ANX7150_video_timing_id;\r
-u8 ANX7150_pix_rpt_set_by_sys;\r
-u8 ANX7150_video_timing_parameter[18];\r
-u8 switch_value_sw_backup,switch_value_pc_backup;\r
-u8 switch_value,bist_switch_value_pc;\r
-u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
-u8 ANX7150_INT_Done;\r
-\r
-audio_config_struct s_ANX7150_audio_config;\r
-config_packets s_ANX7150_packet_config;\r
-\r
-u8 FREQ_MCLK; //0X72:0X50 u82:0\r
-//000b:Fm = 128*Fs\r
-//001b:Fm = 256*Fs\r
-//010b:Fm = 384*Fs\r
-//011b:Fm = 512*Fs\r
-u8 ANX7150_audio_clock_edge;\r
-\r
-\r
-int anx7150_detect_device(struct anx7150_pdata *anx)\r
-{\r
- int i, rc = 0; \r
- char d1, d2;\r
- \r
- for (i=0; i<10; i++) \r
- { \r
- if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDL_REG, &d1)) < 0) \r
- continue;\r
- if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDH_REG, &d2)) < 0) \r
- continue;\r
- if (d1 == 0x50 && d2 == 0x71)\r
- { \r
- hdmi_dbg(&anx->client->dev, "anx7150 detected!\n");\r
- return 1;\r
- } \r
- } \r
- \r
- hdmi_dbg(&anx->client->dev, "anx7150 not detected");\r
- return 0;\r
-}\r
-u8 ANX7150_Get_System_State(void)\r
-{\r
- return ANX7150_system_state;\r
-}\r
-void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state)\r
-{\r
- ANX7150_system_state = new_state;\r
- switch (ANX7150_system_state)\r
- {\r
- case HDMI_INITIAL:\r
- hdmi_dbg(&client->dev, "INITIAL\n");\r
- break;\r
- case WAIT_HOTPLUG:\r
- hdmi_dbg(&client->dev, "WAIT_HOTPLUG\n");\r
- break;\r
- case READ_PARSE_EDID:\r
- hdmi_dbg(&client->dev, "READ_PARSE_EDID\n");\r
- break;\r
- case WAIT_RX_SENSE:\r
- hdmi_dbg(&client->dev, "WAIT_RX_SENSE\n");\r
- break;\r
- case WAIT_HDMI_ENABLE:\r
- hdmi_dbg(&client->dev, "WAIT_HDMI_ENABLE\n");\r
- break;\r
- case SYSTEM_CONFIG:\r
- hdmi_dbg(&client->dev, "SYSTEM_CONFIG\n");\r
- break;\r
- case CONFIG_VIDEO:\r
- dev_info(&client->dev, "CONFIG_VIDEO\n");\r
- break;\r
- case CONFIG_AUDIO:\r
- hdmi_dbg(&client->dev, "CONFIG_AUDIO\n");\r
- break;\r
- case CONFIG_PACKETS:\r
- hdmi_dbg(&client->dev, "CONFIG_PACKETS\n");\r
- break;\r
- case HDCP_AUTHENTICATION:\r
- hdmi_dbg(&client->dev, "HDCP_AUTHENTICATION\n");\r
- break;\r
- ////////////////////////////////////////////////\r
- // System ANX7150_RESET_LINK is kept for RX clock recovery error case, not used in normal case.\r
- case RESET_LINK:\r
- hdmi_dbg(&client->dev, "RESET_LINK\n");\r
- break;\r
- ////////////////////////////////////////////////\r
- case PLAY_BACK:\r
- dev_info(&client->dev, "PLAY_BACK\n");\r
- break;\r
- default:\r
- hdmi_dbg(&client->dev, "unknown state\n");\r
- break;\r
- }\r
-}\r
-\r
-static int anx7150_get_hpd(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char sys_ctl3, intr_state, sys_state, hpd_state;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &sys_ctl3)) < 0)\r
- return rc;\r
- if(sys_ctl3 & ANX7150_SYS_CTRL3_PWON_ALL)\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &sys_state)) < 0)\r
- return rc;\r
- hpd_state = (sys_state & ANX7150_SYS_STATE_HP)? 1:0;\r
- }\r
- else\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR_STATE_REG, &intr_state)) < 0)\r
- return rc;\r
- hpd_state = (intr_state)? 1:0;\r
- }\r
- return hpd_state;\r
-}\r
-static int anx7150_get_interrupt_status(struct i2c_client *client, struct anx7150_interrupt_s *interrupt_staus)\r
-{\r
- int rc = 0;\r
- u8 int_s1;\r
- u8 int_s2;\r
- u8 int_s3;\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//power down all, 090630\r
- rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//power down all, 090630\r
- rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//power down all, 090630\r
-\r
- interrupt_staus->hotplug_change = (int_s1 & ANX7150_INTR1_STATUS_HP_CHG) ? 1 : 0;\r
- interrupt_staus->video_format_change = (int_s3 & ANX7150_INTR3_STATUS_VIDF_CHG) ? 1 : 0;\r
- interrupt_staus->auth_done = (int_s2 & ANX7150_INTR2_STATUS_AUTH_DONE) ? 1 : 0;\r
- interrupt_staus->auth_state_change = (int_s2 & ANX7150_INTR2_STATUS_AUTH_CHG) ? 1 : 0;\r
- interrupt_staus->pll_lock_change = (int_s2 & ANX7150_INTR2_STATUS_PLLLOCK_CHG) ? 1 : 0;\r
- interrupt_staus->rx_sense_change = (int_s3 & ANX7150_INTR3_STATUS_RXSEN_CHG) ? 1 : 0;\r
- interrupt_staus->HDCP_link_change = (int_s2 & ANX7150_INTR2_STATUS_HDCPLINK_CHK) ? 1 : 0;\r
- interrupt_staus->audio_clk_change = (int_s3 & ANX7150_INTR3_STATUS_AUDCLK_CHG) ? 1 : 0;\r
- interrupt_staus->audio_FIFO_overrun = (int_s1 & ANX7150_INTR1_STATUS_AFIFO_OVER) ? 1 : 0;\r
- interrupt_staus->SPDIF_error = (int_s1 & ANX7150_INTR1_STATUS_SPDIF_ERR) ? 1 : 0;\r
- interrupt_staus->SPDIF_bi_phase_error = ((int_s3 & ANX7150_INTR3_STATUS_SPDIFBI_ERR) ? 1 : 0) \r
- || ((int_s3 & ANX7150_INTR3_STATUS_SPDIF_UNSTBL) ? 1 : 0);\r
- return 0;\r
-}\r
-static void ANX7150_Variable_Initial(void)\r
-{\r
- u8 i;\r
-\r
- ANX7150_hdcp_auth_en = 0;\r
- ANX7150_ksv_srm_pass =0;\r
- ANX7150_srm_checked = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_avmute_enable = 1;\r
- ANX7150_hdcp_auth_fail_counter =0;\r
- ANX7150_hdcp_encryption = 0;\r
- ANX7150_send_blue_screen = 0;\r
- ANX7150_hdcp_init_done = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- timer_slot = 0;\r
- //********************for video config**************\r
- ANX7150_video_timing_id = 0;\r
- ANX7150_in_pix_rpt = 0;\r
- ANX7150_tx_pix_rpt = 0;\r
- ANX7150_new_csc = 0;\r
- ANX7150_new_vid_id = 0;\r
- ANX7150_new_HW_interface = 0;\r
- //********************end of video config*********\r
-\r
- //********************for edid parse***********\r
- ANX7150_edid_result.is_HDMI = 0;\r
- ANX7150_edid_result.ycbcr422_supported = 0;\r
- ANX7150_edid_result.ycbcr444_supported = 0;\r
- ANX7150_edid_result.supported_720p_60Hz = 0;\r
- ANX7150_edid_result.supported_720p_50Hz = 0;\r
- ANX7150_edid_result.supported_576p_50Hz = 0;\r
- ANX7150_edid_result.supported_576i_50Hz = 0;\r
- ANX7150_edid_result.supported_1080i_60Hz = 0;\r
- ANX7150_edid_result.supported_1080i_50Hz = 0;\r
- ANX7150_edid_result.supported_640x480p_60Hz = 0;\r
- ANX7150_edid_result.supported_720x480p_60Hz = 0;\r
- ANX7150_edid_result.supported_720x480i_60Hz = 0;\r
- ANX7150_edid_result.edid_errcode = 0;\r
- ANX7150_edid_result.SpeakerFormat = 0;\r
- for (i = 0; i < 8; i ++)\r
- {\r
- ANX7150_edid_result.AudioChannel[i] = 0;\r
- ANX7150_edid_result.AudioFormat[i] = 0;\r
- ANX7150_edid_result.AudioFs[i] = 0;\r
- ANX7150_edid_result.AudioLength[i] = 0;\r
- }\r
- //********************end of edid**************\r
-\r
- s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe\r
- s_ANX7150_packet_config.avi_info.type = 0x82;\r
- s_ANX7150_packet_config.avi_info.version = 0x02;\r
- s_ANX7150_packet_config.avi_info.length = 0x0d;\r
- s_ANX7150_packet_config.avi_info.pb_u8[1] = 0x21;//YCbCr422\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x08;\r
- s_ANX7150_packet_config.avi_info.pb_u8[3] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[4] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[5] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[6] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[7] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[8] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[9] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[10] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[11] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[12] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[13] = 0x00;\r
-\r
- // audio infoframe\r
- s_ANX7150_packet_config.audio_info.type = 0x84;\r
- s_ANX7150_packet_config.audio_info.version = 0x01;\r
- s_ANX7150_packet_config.audio_info.length = 0x0a;\r
- s_ANX7150_packet_config.audio_info.pb_u8[1] = 0x00; //zy 061123 for ATC\r
- s_ANX7150_packet_config.audio_info.pb_u8[2] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[3] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[4] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[5] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[6] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[7] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[8] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[9] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[10] = 0x00;\r
-\r
- ANX7150_INT_Done = 0;\r
-}\r
-static void ANX7150_HW_Interface_Variable_Initial(void)\r
-{\r
- u8 c;\r
-\r
- ANX7150_video_format_config = 0x00;\r
- ANX7150_RGBorYCbCr = 0x00;\r
- ANX7150_ddr_edge = ANX7150_IDCK_EDGE_DDR;\r
-\r
- c = 0;\r
- c = (ANX7150_I2S_CH0_ENABLE << 2) | (ANX7150_I2S_CH1_ENABLE << 3) |\r
- (ANX7150_I2S_CH2_ENABLE << 4) | (ANX7150_I2S_CH3_ENABLE << 5);\r
- s_ANX7150_audio_config.audio_type = ANX7150_AUD_HW_INTERFACE; // input I2S\r
- s_ANX7150_audio_config.down_sample = 0x00;\r
- s_ANX7150_audio_config.i2s_config.audio_channel = c;//0x04;\r
- s_ANX7150_audio_config.i2s_config.Channel_status1 =0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status1 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status2 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status3 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status4 = 0x00;//0x02;//48k\r
- s_ANX7150_audio_config.i2s_config.Channel_status5 = ANX7150_I2S_WORD_LENGTH;//0x0b;\r
- s_ANX7150_audio_config.audio_layout = 0x00;\r
-\r
- c = (ANX7150_I2S_SHIFT_CTRL << 3) | (ANX7150_I2S_DIR_CTRL << 2) |\r
- (ANX7150_I2S_WS_POL << 1) | ANX7150_I2S_JUST_CTRL;\r
- s_ANX7150_audio_config.i2s_config.i2s_format = c;//0x00;\r
-\r
- FREQ_MCLK = ANX7150_MCLK_Fs_RELATION;//set the relation of MCLK and WS\r
- ANX7150_audio_clock_edge = ANX7150_AUD_CLK_EDGE;\r
-\r
-\r
-}\r
-static int anx7150_hardware_initial(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c = 0;\r
- \r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- mdelay(10);\r
-\r
- c &= (~0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- \r
- //Power on I2C\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (ANX7150_SYS_CTRL3_I2C_PWON);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c= 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
-\r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xbf);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //Power on Audio capture and Video capture module clock\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
- c |= (0x06);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
-\r
- //Enable auto set clock range for video PLL\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
- c &= (0x00);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
-\r
- //Set registers value of Blue Screen when HDCP authentication failed--RGB mode,green field\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, (c | 0x80));\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
- c |= (0x08);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_TX_AMP, &c);//jack wen\r
- c |= (0x01);\r
-\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_TX_AMP, &c); //TMDS swing\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL1_REG, &c); //Added for PLL unlock issue in high temperature - Feiw\r
- //if (ANX7150_AUD_HW_INTERFACE == 0x02) //jack wen, spdif\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xef);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
-\r
- c = 0xc7;\r
- rc = anx7150_i2c_write_p0_reg(client, 0xE1, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);//power down HDCP, 090630\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xfe);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power down all, 090630\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_rst_ddcchannel(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- //Reset the DDC channel\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- c |= (ANX7150_SYS_CTRL2_DDC_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- c &= (~ANX7150_SYS_CTRL2_DDC_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//abort current operation\r
-\r
- c = 0x06;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
-\r
- //Clear FIFO\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_unplug(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- dev_info(&client->dev, "anx7150 unplug\n");\r
- \r
- //wen HDCP CTS\r
- ANX7150_Variable_Initial(); //simon\r
- ANX7150_HW_Interface_Variable_Initial(); //simon\r
- \r
- rc = anx7150_hardware_initial(client); //simon\r
- if(rc < 0)\r
- dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //simon\r
- if(rc < 0)\r
- dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
- //wen HDCP CTS\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
-\r
- // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
- ANX7150_parse_edid_done = 0;\r
-// ANX7150_system_config_done = 0;\r
- ANX7150_srm_checked = 0;\r
-\r
- return rc;\r
-}\r
-int anx7150_plug(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- dev_info(&client->dev, "anx7150 plug\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power up all, 090630\r
-\r
- //disable audio & video & hdcp & TMDS and init begin\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
-\r
- ANX7150_Variable_Initial();\r
- //disable video & audio & hdcp & TMDS and init end\r
-\r
- \r
- //Power on chip and select DVI mode\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x05);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);// cwz change 0x01 -> 0x05\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfd);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //D("ANX7150 is set to DVI mode\n");\r
- rc = anx7150_rst_ddcchannel(client);\r
- //Initial Interrupt\r
- // disable video/audio CLK,Format change and before config video. 060713 xy\r
-\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR_CTRL_REG, &c);\r
-\r
- // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
- ANX7150_parse_edid_done = 0;\r
-// ANX7150_system_config_done = 0;\r
- ANX7150_srm_checked = 0;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_set_avmute(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- c = 0x01;\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
- return rc;\r
- \r
- if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (0x0c);\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_avmute_enable = 1;\r
-\r
- return rc;\r
-}\r
-static int anx7150_clear_avmute(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- c = 0x02;\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
- return rc;\r
- \r
- if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (0x0c);\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_avmute_enable = 0;\r
-// D("@@@@@@@@@@@@@@@@@@@@ANX7150_Clear_AVMute\n");\r
- return rc;\r
-\r
-}\r
-\r
-static int anx7150_video_format_change(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c;\r
- \r
- hdmi_dbg(&client->dev, "after video format change int \n");\r
- \r
- rc = anx7150_set_avmute(client);//wen\r
- //stop HDCP and reset DDC\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- rc = anx7150_rst_ddcchannel(client);\r
- \r
- //when format change, clear this reg to avoid error in package config\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- //xy 11.06 when format change, need system config again\r
- // ANX7150_system_config_done = 0;\r
- return rc;\r
-}\r
-static int anx7150_blue_screen_disable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- c &= (0xfb);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
-\r
- ANX7150_send_blue_screen = 0;\r
- \r
- return rc;\r
-}\r
-static int anx7150_blue_screen_enable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_send_blue_screen = 1;\r
-\r
- return rc;\r
-}\r
-static int anx7150_hdcp_encryption_enable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDCP_CTRL0_ENC_EN);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_hdcp_encryption = 1;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_hdcp_encryption_disable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- c &= (0xfb);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
-\r
- ANX7150_hdcp_encryption = 0;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_auth_done(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "anx7150 auth done\n");\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c)) < 0)\r
- return rc;\r
- \r
- if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Done\n");\r
- anx7150_blue_screen_disable(client);\r
- ANX7150_hdcp_auth_pass = 1;\r
- ANX7150_hdcp_auth_fail_counter = 0;\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication failed\n");\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_auth_fail_counter ++;\r
- if (ANX7150_hdcp_auth_fail_counter >= ANX7150_HDCP_FAIL_THRESHOLD)\r
- {\r
- ANX7150_hdcp_auth_fail_counter = 0;\r
- //ANX7150_bksv_ready = 0;\r
- // TODO: Reset link;\r
- rc = anx7150_blue_screen_enable(client);\r
- rc = anx7150_hdcp_encryption_disable(client);\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
- }\r
- return rc;\r
-}\r
-\r
-static int anx7150_clean_hdcp(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- //mute TMDS link\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);//jack wen\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, c & (~ANX7150_TMDS_CLKCH_MUTE));\r
-\r
- //Disable hardware HDCP\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- //Reset HDCP logic\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c |= (ANX7150_SRST_HDCP_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c &= (~ANX7150_SRST_HDCP_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
-\r
- //Set ReAuth\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= (ANX7150_HDCP_CTRL0_RE_AUTH);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_RE_AUTH);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
- //ANX7150_bksv_ready = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_auth_fail_counter =0 ;\r
- ANX7150_hdcp_encryption = 0;\r
- ANX7150_send_blue_screen = 0;\r
- ANX7150_hdcp_init_done = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_srm_checked = 0;\r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- return rc;\r
-}\r
-static int anx7150_auth_change(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- int state = ANX7150_Get_System_State();\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
- {\r
- ANX7150_hdcp_auth_pass = 1;\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Change\n");\r
- }\r
- else\r
- {\r
- rc = anx7150_set_avmute(client); //wen\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication failed_by_Auth_change\n");\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_hdcp_init_done=0; //wen HDCP CTS\r
- ANX7150_hdcp_auth_en=0; //wen HDCP CTS\r
- rc = anx7150_hdcp_encryption_disable(client);\r
- if (state == PLAY_BACK)\r
- {\r
- ANX7150_auth_fully_pass = 0;\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- rc = anx7150_clean_hdcp(client); //wen updated for Changhong TV\r
- }\r
- }\r
- return rc;\r
-}\r
-int ANX7150_GET_RECIVER_TYPE(void)\r
-{
- return ANX7150_edid_result.is_HDMI;
-}\r
-static int anx7150_audio_clk_change(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "ANX7150: audio clock changed interrupt,disable audio.\n");\r
- // disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //xy 11.06 when format change, need system config again\r
-// ANX7150_system_config_done = 0;\r
- return rc;\r
-}\r
-\r
-static int anx7150_afifo_overrun(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- hdmi_dbg(&client->dev, "ANX7150: AFIFO overrun interrupt,disable audio.\n");\r
- // disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int anx7150_spdif_error(struct i2c_client *client, int cur_state, int SPDIF_bi_phase_err, int SPDIF_error)\r
-{\r
- int rc = 0;\r
- char c;\r
- int state = cur_state;\r
-\r
- if(SPDIF_bi_phase_err || SPDIF_error)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- if( c & ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN) \r
- {\r
- \r
- if ((state == CONFIG_AUDIO \r
- || state == CONFIG_PACKETS \r
- || state == HDCP_AUTHENTICATION \r
- || state == PLAY_BACK ))\r
- {\r
- if(SPDIF_bi_phase_err){\r
- hdmi_dbg(&client->dev, "SPDIF BI Phase or Unstable error.\n");\r
- spdif_error_cnt += 0x03;\r
- }\r
-\r
- if(SPDIF_error){\r
- hdmi_dbg(&client->dev, "SPDIF Parity error.\n");\r
- spdif_error_cnt += 0x01;\r
- }\r
-\r
- }\r
-\r
- // adjust spdif phase\r
- if (spdif_error_cnt >= spdif_error_th)\r
- {\r
- char freq_mclk,c1,c2;\r
- spdif_error_cnt = 0x00;\r
- hdmi_dbg(&client->dev, "adjust mclk phase!\n");\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
-\r
- freq_mclk = c2 & 0x07;\r
- switch (freq_mclk)\r
- {\r
- case ANX7150_mclk_128_Fs: //invert 0x50[3]\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 128*Fs!\n");\r
- if ( c2 & 0x08 ) c2 &= 0xf7;\r
- else c2 |= 0x08;\r
-\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
- break;\r
-\r
- case ANX7150_mclk_256_Fs:\r
- case ANX7150_mclk_384_Fs:\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 256*Fs or 384*Fs!\n");\r
- if ( c1 & 0x60 ) c1 &= 0x9f;\r
- else c1 |= 0x20;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
- break;\r
-\r
- case ANX7150_mclk_512_Fs:\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 512*Fs!\n");\r
- if ( c1 & 0x60 ) c1 &= 0x9f;\r
- else c1 |= 0x40;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
- break;\r
- default:\r
- break;\r
-\r
- }\r
- }\r
- }\r
- }\r
- else{\r
- if(spdif_error_cnt > 0 && state == PLAY_BACK) spdif_error_cnt --;\r
- if(spdif_error_cnt > 0 && state < CONFIG_AUDIO) spdif_error_cnt = 0x00;\r
-\r
- }\r
-\r
- return rc;\r
-}\r
-static int anx7150_plllock(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_STATUS_REG, &c);\r
- if((c&0x01) == 0)\r
- {\r
- rc = anx7150_set_avmute(client);//wen\r
- hdmi_dbg(&client->dev, "ANX7150: PLL unlock interrupt,disable audio.\n");\r
- // disable audio & video\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- //when pll change, clear this reg to avoid error in package config\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);//wen\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
-// ANX7150_system_config_done = 0;//jack wen\r
- }\r
- return rc;\r
-}\r
-static int anx7150_rx_sense_change(struct i2c_client *client, int cur_state)\r
-{\r
- int rc = 0;\r
- char c;\r
- int state = cur_state;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
- hdmi_dbg(&client->dev, "ANX7150_Rx_Sense_Interrupt, ANX7150_SYS_STATE_REG = %.2x\n", (unsigned int)c); //wen\r
-\r
- if ( c & ANX7150_SYS_STATE_RSV_DET)\r
- {\r
- //xy 11.06 Power on chip\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe wen\r
- }\r
- else\r
- {\r
- // Rx is not active\r
- if (state > WAIT_HOTPLUG)\r
- {\r
- //stop HDCP and reset DDC when lost Rx sense\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_REG);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfd);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- \r
- // mute TMDS link\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- }\r
- //Power down chip\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfe);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- }\r
- //xy 11.06 when format change, need system config again\r
-// ANX7150_system_config_done = 0;//wen HDCP CTS\r
-\r
- return rc;\r
-}\r
-int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state)\r
-{\r
- struct anx7150_interrupt_s interrupt_staus;\r
- struct hdmi *hdmi = anx->dev.hdmi;\r
- int state;\r
- int hot_plug;\r
- int rc;\r
-\r
- state = cur_state;\r
-\r
- hot_plug = anx7150_get_hpd(anx->client);\r
-\r
- rc = anx7150_get_interrupt_status(anx->client, &interrupt_staus);\r
- if(rc < 0){\r
- goto out;\r
- } \r
-\r
- if(anx->dev.HPD_status != hot_plug){\r
- anx->dev.HPD_change_cnt++;\r
- }\r
- else{\r
- anx->dev.HPD_change_cnt = 0;\r
- }\r
-\r
- if(anx->dev.HPD_change_cnt > 1){\r
- hdmi_dbg(&anx->client->dev, "hotplug_change\n");\r
-\r
- if(hot_plug == HDMI_RECIVER_UNPLUG){\r
- anx7150_unplug(anx->client);\r
- state = HDMI_INITIAL;\r
- anx->dev.reciver_status = HDMI_RECIVER_INACTIVE;\r
- hdmi_changed(hdmi, 0);\r
- }\r
-\r
- anx->dev.HPD_change_cnt = 0;\r
- anx->dev.HPD_status = hot_plug;\r
- }\r
- return state;\r
- if(state != HDMI_INITIAL && state != WAIT_HOTPLUG){\r
- if(interrupt_staus.video_format_change){\r
- if(state > SYSTEM_CONFIG){\r
- rc = anx7150_video_format_change(anx->client);\r
- state = CONFIG_VIDEO;\r
- }\r
- }\r
-\r
- if(interrupt_staus.auth_done){\r
- rc = anx7150_auth_done(anx->client);\r
- state = CONFIG_AUDIO;\r
- }\r
-\r
- if(interrupt_staus.auth_state_change){\r
- rc = anx7150_auth_change(anx->client);\r
- if(state == PLAY_BACK){\r
- state = HDCP_AUTHENTICATION;\r
- }\r
- }\r
-\r
- if(ANX7150_GET_RECIVER_TYPE() == 1){\r
- if(interrupt_staus.audio_clk_change){\r
- if(state > CONFIG_VIDEO){\r
- rc = anx7150_audio_clk_change(anx->client);\r
- state = SYSTEM_CONFIG;\r
- }\r
- }\r
- \r
- if(interrupt_staus.audio_FIFO_overrun){\r
- if(state > CONFIG_VIDEO){\r
- rc = anx7150_afifo_overrun(anx->client);\r
- state = CONFIG_AUDIO;\r
- }\r
- }\r
-\r
- rc = anx7150_spdif_error(anx->client, state, interrupt_staus.SPDIF_bi_phase_error, interrupt_staus.SPDIF_error);\r
- }\r
-\r
- if(interrupt_staus.pll_lock_change){\r
- if(state > SYSTEM_CONFIG){\r
- rc = anx7150_plllock(anx->client);\r
- state = SYSTEM_CONFIG;\r
- }\r
- }\r
-\r
- if(interrupt_staus.rx_sense_change){\r
- anx7150_rx_sense_change(anx->client, state);\r
- if(state > WAIT_RX_SENSE) \r
- state = WAIT_RX_SENSE;\r
- }\r
- }\r
-\r
-out:\r
- return state;\r
-}\r
-\r
-int ANX7150_API_Initial(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- hdmi_dbg(&client->dev, "%s\n", __func__);\r
-\r
- ANX7150_Variable_Initial();\r
- ANX7150_HW_Interface_Variable_Initial();\r
- rc = anx7150_hardware_initial(client);\r
-\r
- return rc;\r
-}\r
-\r
-void ANX7150_Shutdown(struct i2c_client *client)\r
-{\r
- hdmi_dbg(&client->dev, "%s\n", __func__);\r
- ANX7150_API_Initial(client);\r
- ANX7150_Set_System_State(client, HDMI_INITIAL);\r
-}\r
-\r
-static int anx7150_initddc_read(struct i2c_client *client, \r
- u8 devaddr, u8 segmentpointer,\r
- u8 offset, u8 access_num_Low,u8 access_num_high)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- //Write slave device address\r
- c = devaddr;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_ADDR_REG, &c);\r
- // Write segment address\r
- c = segmentpointer;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_SEGADDR_REG, &c);\r
- //Write offset\r
- c = offset;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_OFFADDR_REG, &c);\r
- //Write number for access\r
- c = access_num_Low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM0_REG, &c);\r
- c = access_num_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM1_REG, &c);\r
- //Clear FIFO\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
- //EDDC sequential Read\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int ANX7150_GetEDIDLength(struct i2c_client *client)\r
-{\r
- u8 edid_data_length;\r
- char c;\r
- int rc = 0;\r
-\r
- anx7150_rst_ddcchannel(client);\r
-\r
- rc = anx7150_initddc_read(client, 0xa0, 0x00, 0x7e, 0x01, 0x00);\r
- /*msleep(3);//FeiW - Analogix\r
- for(i=0;i<10;i++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- if(c!=0){\r
- break;\r
- }\r
- }\r
- */\r
- msleep(10);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c);\r
- edid_data_length = c;\r
-\r
- ANX7150_edid_length = edid_data_length * 128 + 128;\r
-\r
- return rc;\r
-\r
-}\r
-static int ANX7150_DDC_Mass_Read(struct i2c_client *client, u32 length, u8 segment)\r
-{\r
- int rc = 0;\r
- u32 i, j;\r
- char c, c1,ddc_empty_cnt;\r
-\r
- i = length;\r
- while (i > 0)\r
- {\r
- //check DDC FIFO statue\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
- if (c & ANX7150_DDC_CHSTATUS_DDC_OCCUPY)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150 DDC channel is accessed by an external device, break!.\n");\r
- break;\r
- }\r
- if (c & ANX7150_DDC_CHSTATUS_FIFO_FULL)\r
- ANX7150_ddc_fifo_full = 1;\r
- else\r
- ANX7150_ddc_fifo_full = 0;\r
- if (c & ANX7150_DDC_CHSTATUS_INPRO)\r
- ANX7150_ddc_progress = 1;\r
- else\r
- ANX7150_ddc_progress = 0;\r
- if (ANX7150_ddc_fifo_full)\r
- {\r
- hdmi_dbg(&client->dev, "DDC FIFO is full during edid reading");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- hdmi_dbg(&client->dev, "FIFO counter is %.2x\n", (u32) c);\r
- for (j=0; j<c; j++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
- if (segment == 0)\r
- {\r
- ANX7150_EDID_Buf[length - i + j] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j), (u32) c1);\r
- }\r
- else if (segment == 1)\r
- {\r
- ANX7150_EDID_Buf[length - i + j + 0x80] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j + 0x80), (u32) c1);\r
- }\r
-\r
- ANX7150_ddc_fifo_full = 0;\r
- if(anx7150_mass_read_need_delay)\r
- msleep(2);\r
- }\r
- i = i - c;\r
- //D("\n");\r
- }\r
- else if (!ANX7150_ddc_progress)\r
- {\r
- //D("ANX7150 DDC FIFO access finished.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- //D("FIFO counter is %.2x\n", (u32) c);\r
- if (!c)\r
- {\r
- i =0;\r
- break;\r
- }\r
- for (j=0; j<c; j++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
- if (segment == 0)\r
- {\r
- ANX7150_EDID_Buf[length - i + j] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j), (u32) c1);\r
- }\r
- else if (segment == 1)\r
- {\r
- ANX7150_EDID_Buf[length - i + j + 0x80] = c1;\r
- //D("EDID[0x%.2x]=0x%.2x ", (u32)(length - i + j + 0x80), (u32) c1);\r
- }\r
- }\r
- i = i - c;\r
- //D("\ni=%d\n", i);\r
- }\r
- else\r
- {\r
- ddc_empty_cnt = 0x00;\r
- for (c1=0; c1<0x0a; c1++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
- //D("DDC FIFO access is progressing.\n");\r
- //D("DDC Channel status is 0x%.2x\n",(u32)c);\r
- if (c & ANX7150_DDC_CHSTATUS_FIFO_EMPT)\r
- ddc_empty_cnt++;\r
- msleep(5);\r
- //D("ddc_empty_cnt = 0x%.2x\n",(u32)ddc_empty_cnt);\r
- }\r
- if (ddc_empty_cnt >= 0x0a)\r
- i = 0;\r
- }\r
- }\r
- return rc;\r
-}\r
-static int ANX7150_Read_EDID(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
-\r
- u8 edid_segment,segmentpointer,k;\r
-\r
- rc = anx7150_rst_ddcchannel(client);\r
- msleep(5);\r
-\r
- edid_segment = ANX7150_edid_length / 256;\r
- if (edid_segment==0) //update\r
- segmentpointer =0;\r
- else\r
- segmentpointer = edid_segment - 1;\r
- //segmentpointer = edid_segment - 1;\r
-\r
- for (k = 0; k <= segmentpointer; k ++)\r
- {\r
- rc =anx7150_initddc_read(client, 0xa0, k, 0x00, 0x80, 0x00);\r
- msleep(10);\r
- rc = ANX7150_DDC_Mass_Read(client, 128, k);\r
- //msleep(10);\r
- rc = anx7150_initddc_read(client, 0xa0, k, 0x80, 0x80, 0x00);\r
- msleep(10);\r
- rc = ANX7150_DDC_Mass_Read(client, 128, k + 1);\r
- //msleep(10);\r
- }\r
-\r
- if ((ANX7150_edid_length - 256 * edid_segment) == 0)\r
- hdmi_dbg(&client->dev, "Finish reading EDID\n");\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "Read one more block(128 u8s).........\n");\r
- rc = anx7150_initddc_read(client, 0xa0, segmentpointer + 1, 0x00, 0x80, 0x00);\r
- msleep(5);\r
- rc = ANX7150_DDC_Mass_Read(client, 128, segmentpointer + 1);\r
- hdmi_dbg(&client->dev, "Finish reading EDID\n");\r
- msleep(5);\r
- }\r
- return rc;\r
-}\r
-static u8 ANX7150_Read_EDID_u8(u8 segmentpointer,u8 offset)\r
-{
- /*u8 c;
- anx7150_initddc_read(0xa0, segmentpointer, offset, 0x01, 0x00);\r
- ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFOCNT_REG, &c);
- while(c==0)
- ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFO_ACC_REG, &c);
- return c;*/
-
- return ANX7150_EDID_Buf[offset];
-}\r
-static u8 ANX7150_Parse_EDIDHeader(void)\r
-{\r
- u8 i,temp;\r
- temp = 0;\r
- // the EDID header should begin with 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00\r
- if ((ANX7150_Read_EDID_u8(0, 0) == 0x00) && (ANX7150_Read_EDID_u8(0, 7) == 0x00))\r
- {\r
- for (i = 1; i < 7; i++)\r
- {\r
- if (ANX7150_Read_EDID_u8(0, i) != 0xff)\r
- {\r
- temp = 0x01;\r
- break;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- temp = 0x01;\r
- }\r
- if (temp == 0x01)\r
- {\r
- return 0;\r
- }\r
- else\r
- {\r
- return 1;\r
- }\r
-}\r
-static u8 ANX7150_Parse_EDIDVersion(void)\r
-{\r
-\r
- if (!((ANX7150_Read_EDID_u8(0, 0x12) == 1) && (ANX7150_Read_EDID_u8(0, 0x13) >= 3) ))\r
- {\r
- return 0;\r
- }\r
- else\r
- {\r
- return 1;\r
- }\r
-}\r
-static void ANX7150_Parse_DTD(void)\r
-{
- u32 temp;
- unsigned long temp1,temp2;
- u32 Hresolution,Vresolution,Hblanking,Vblanking;
- u32 PixelCLK,Vtotal,H_image_size,V_image_size;
- u8 Hz;
- //float Ratio;
-
- temp = ANX7150_edid_dtd[1];
- temp = temp << 8;
- PixelCLK = temp + ANX7150_edid_dtd[0];
- // D("Pixel clock is 10000 * %u\n", temp);
-
- temp = ANX7150_edid_dtd[4];
- temp = (temp << 4) & 0x0f00;
- Hresolution = temp + ANX7150_edid_dtd[2];
- //D("Horizontal Active is %u\n", Hresolution);
-
- temp = ANX7150_edid_dtd[4];
- temp = (temp << 8) & 0x0f00;
- Hblanking = temp + ANX7150_edid_dtd[3];
- //D("Horizontal Blanking is %u\n", temp);
-
- temp = ANX7150_edid_dtd[7];
- temp = (temp << 4) & 0x0f00;
- Vresolution = temp + ANX7150_edid_dtd[5];
- //D("Vertical Active is %u\n", Vresolution);
-
- temp = ANX7150_edid_dtd[7];
- temp = (temp << 8) & 0x0f00;
- Vblanking = temp + ANX7150_edid_dtd[6];
- //D("Vertical Blanking is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 2) & 0x0300;
- temp = temp + ANX7150_edid_dtd[8];
- //D("Horizontal Sync Offset is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 4) & 0x0300;
- temp = temp + ANX7150_edid_dtd[9];
- //D("Horizontal Sync Pulse is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 2) & 0x0030;
- temp = temp + (ANX7150_edid_dtd[10] >> 4);
- //D("Vertical Sync Offset is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 4) & 0x0030;
- temp = temp + (ANX7150_edid_dtd[8] & 0x0f);
- //D("Vertical Sync Pulse is %u\n", temp);
-
- temp = ANX7150_edid_dtd[14];
- temp = (temp << 4) & 0x0f00;
- H_image_size = temp + ANX7150_edid_dtd[12];
- //D("Horizontal Image size is %u\n", temp);
-
- temp = ANX7150_edid_dtd[14];
- temp = (temp << 8) & 0x0f00;
- V_image_size = temp + ANX7150_edid_dtd[13];
- //D("Vertical Image size is %u\n", temp);
-
- //D("Horizontal Border is %bu\n", ANX7150_edid_dtd[15]);
-
- //D("Vertical Border is %bu\n", ANX7150_edid_dtd[16]);
-
- temp1 = Hresolution + Hblanking;
- Vtotal = Vresolution + Vblanking;
- temp1 = temp1 * Vtotal;
- temp2 = PixelCLK;
- temp2 = temp2 * 10000;
- if (temp1 == 0) //update
- Hz=0;
- else
- Hz = temp2 / temp1;
- //Hz = temp2 / temp1;
- if ((Hz == 59) || (Hz == 60))
- {
- Hz = 60;
- //D("_______________Vertical Active is %u\n", Vresolution);
- if (Vresolution == 540)
- ANX7150_edid_result.supported_1080i_60Hz = 1;
- if (Vresolution == 1080)
- ANX7150_edid_result.supported_1080p_60Hz = 1;
- if (Vresolution == 720)
- ANX7150_edid_result.supported_720p_60Hz = 1;
- if ((Hresolution == 640) && (Vresolution == 480))
- ANX7150_edid_result.supported_640x480p_60Hz = 1;
- if ((Hresolution == 720) && (Vresolution == 480))
- ANX7150_edid_result.supported_720x480p_60Hz = 1;
- if ((Hresolution == 720) && (Vresolution == 240))
- ANX7150_edid_result.supported_720x480i_60Hz = 1;
- }
- if (Hz == 50)
- {
- //D("+++++++++++++++Vertical Active is %u\n", Vresolution);
- if (Vresolution == 540)
- ANX7150_edid_result.supported_1080i_50Hz = 1;
- if (Vresolution == 1080)
- ANX7150_edid_result.supported_1080p_50Hz = 1;
- if (Vresolution == 720)
- ANX7150_edid_result.supported_720p_50Hz = 1;
- if (Vresolution == 576)
- ANX7150_edid_result.supported_576p_50Hz = 1;
- if (Vresolution == 288)
- ANX7150_edid_result.supported_576i_50Hz = 1;
- }
- //D("Fresh rate :% bu Hz\n", Hz);
- //Ratio = H_image_size;
- //Ratio = Ratio / V_image_size;
- //D("Picture ratio : %f \n", Ratio);
-}\r
-static void ANX7150_Parse_DTDinBlockONE(void)\r
-{
- u8 i;
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x36));
- }
- //D("Parse the first DTD in Block one:\n");
- ANX7150_Parse_DTD();
-
- if ((ANX7150_Read_EDID_u8(0, 0x48) == 0)
- && (ANX7150_Read_EDID_u8(0, 0x49) == 0)
- && (ANX7150_Read_EDID_u8(0, 0x4a) == 0))
- {
- ;//D("the second DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x48));
- }
- ANX7150_Parse_DTD();
- }
-
- if ((ANX7150_Read_EDID_u8(0,0x5a) == 0)
- && (ANX7150_Read_EDID_u8(0,0x5b) == 0)
- && (ANX7150_Read_EDID_u8(0,0x5c) == 0))
- {
- ;//D("the third DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x5a));
- }
- ANX7150_Parse_DTD();
- }
-
- if ((ANX7150_Read_EDID_u8(0,0x6c) == 0)
- && (ANX7150_Read_EDID_u8(0,0x6d) == 0)
- && (ANX7150_Read_EDID_u8(0,0x6e) == 0))
- {
- ;//D("the fourth DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0,(i + 0x6c));
- }
- ANX7150_Parse_DTD();
- }
-}\r
-static void ANX7150_Parse_NativeFormat(void)\r
-{
- u8 temp;
- temp = ANX7150_Read_EDID_u8(0,0x83) & 0xf0;
- /*if(temp & 0x80)
- ;//D("DTV supports underscan.\n");
- if(temp & 0x40)
- ;//D("DTV supports BasicAudio.\n");*/
- if (temp & 0x20)
- {
- //D("DTV supports YCbCr 4:4:4.\n");
- ANX7150_edid_result.ycbcr444_supported= 1;
- }
- if (temp & 0x10)
- {
- //D("DTV supports YCbCr 4:2:2.\n");
- ANX7150_edid_result.ycbcr422_supported= 1;
- }
-}\r
-static void ANX7150_Parse_DTDinExtBlock(void)\r
-{
- u8 i,DTDbeginAddr;
- DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2, 0x82)
- + 0x80;
- while (DTDbeginAddr < (0x6c + 0x80))
- {
- if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,DTDbeginAddr) == 0)
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 1)) == 0)
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 2)) == 0))
- {
- ;//D("this DTD in Extension Block is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(i + DTDbeginAddr));
- }
- //D("Parse the DTD in Extension Block :\n");
- ANX7150_Parse_DTD();
- }
- DTDbeginAddr = DTDbeginAddr + 18;
- }
-}\r
-static void ANX7150_Parse_AudioSTD(void)\r
-{
- u8 i,AudioFormat,STDReg_tmp,STDAddr_tmp;
- STDReg_tmp = ANX7150_stdreg & 0x1f;
- STDAddr_tmp = ANX7150_stdaddr + 1;
- i = 0;
- while (i < STDReg_tmp)
- {
- AudioFormat = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp ) & 0xF8) >> 3;
- ANX7150_edid_result.AudioChannel[i/3] = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x07) + 1;
- ANX7150_edid_result.AudioFormat[i/3] = AudioFormat;
- ANX7150_edid_result.AudioFs[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 1)) & 0x7f;
-
- if (AudioFormat == 1)
- ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) & 0x07;
- else
- ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) << 3;
-
- i = i + 3;
- STDAddr_tmp = STDAddr_tmp + 3;
- }
-}\r
-static void ANX7150_Parse_VideoSTD(void)\r
-{
- u8 i,STDReg_tmp,STDAddr_tmp;
- u8 SVD_ID[34];
- STDReg_tmp = ANX7150_stdreg & 0x1f;
- STDAddr_tmp = ANX7150_stdaddr + 1;
- i = 0;
- while (i < STDReg_tmp)
- {
- SVD_ID[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x7F;
- //D("ANX7150_edid_result.SVD_ID[%.2x]=0x%.2x\n",(u32)i,(u32)ANX7150_edid_result.SVD_ID[i]);
- //if(ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x80)
- // D(" Native mode");
- if (SVD_ID[i] == 1)
- ANX7150_edid_result.supported_640x480p_60Hz = 1;
- else if (SVD_ID[i] == 4)
- ANX7150_edid_result.supported_720p_60Hz = 1;
- else if (SVD_ID[i] == 19)
- ANX7150_edid_result.supported_720p_50Hz = 1;
- else if (SVD_ID[i] == 16)
- ANX7150_edid_result.supported_1080p_60Hz = 1;
- else if (SVD_ID[i] == 31)
- ANX7150_edid_result.supported_1080p_50Hz = 1;
- else if (SVD_ID[i] == 5)
- ANX7150_edid_result.supported_1080i_60Hz = 1;
- else if (SVD_ID[i] == 20)
- ANX7150_edid_result.supported_1080i_50Hz = 1;
- else if ((SVD_ID[i] == 2) ||(SVD_ID[i] == 3))
- ANX7150_edid_result.supported_720x480p_60Hz = 1;
- else if ((SVD_ID[i] == 6) ||(SVD_ID[i] == 7))
- ANX7150_edid_result.supported_720x480i_60Hz = 1;
- else if ((SVD_ID[i] == 17) ||(SVD_ID[i] == 18))
- ANX7150_edid_result.supported_576p_50Hz = 1;
- else if ((SVD_ID[i] == 21) ||(SVD_ID[i] == 22))
- ANX7150_edid_result.supported_576i_50Hz = 1;
-
- i = i + 1;
- STDAddr_tmp = STDAddr_tmp + 1;
- }
-}\r
-static void ANX7150_Parse_SpeakerSTD(void)\r
-{
- ANX7150_edid_result.SpeakerFormat = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) ;
-}\r
-static void ANX7150_Parse_VendorSTD(void)\r
-{\r
- //u8 c;\r
- if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) == 0x03)\r
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 2)) == 0x0c)\r
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 3)) == 0x00))\r
- {\r
- ANX7150_edid_result.is_HDMI = 1;\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c |ANX7150_SYS_CTRL1_HDMI);\r
- }\r
- else\r
- {\r
- ANX7150_edid_result.is_HDMI = 0;\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c & (~ANX7150_SYS_CTRL1_HDMI));\r
- }\r
-}\r
-\r
-static void ANX7150_Parse_STD(void)\r
-{
- u8 DTDbeginAddr;
- ANX7150_stdaddr = 0x84;
- DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,0x82) + 0x80;
- // D("Video DTDbeginAddr Register :%.2x\n", (u32) DTDbeginAddr);
- while (ANX7150_stdaddr < DTDbeginAddr)
- {
- ANX7150_stdreg = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,ANX7150_stdaddr);
- switch (ANX7150_stdreg & 0xe0)
- {
- case 0x20:
- ANX7150_Parse_AudioSTD();
- ANX7150_sau_length = ANX7150_stdreg & 0x1f;
- break;
- case 0x40:
- ANX7150_Parse_VideoSTD();
- ANX7150_svd_length = ANX7150_stdreg & 0x1f;
- break;
- case 0x80:
- ANX7150_Parse_SpeakerSTD();
- break;
- case 0x60:
- ANX7150_Parse_VendorSTD();
- break;
- default:
- break;
- }
- ANX7150_stdaddr = ANX7150_stdaddr + (ANX7150_stdreg & 0x1f) + 0x01;
- }
-}\r
-static u8 ANX7150_EDID_Checksum(u8 block_number)\r
-{
- u8 i, real_checksum;
- u8 edid_block_checksum;
-
- edid_block_checksum = 0;
- for (i = 0; i < 127; i ++)
- {
- if ((block_number / 2) * 2 == block_number)
- edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i);
- else
- edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i + 0x80);
- }
- edid_block_checksum = (~edid_block_checksum) + 1;
- // D("edid_block_checksum = 0x%.2x\n",(u32)edid_block_checksum);
- if ((block_number / 2) * 2 == block_number)
- real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0x7f);
- else
- real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0xff);
- if (real_checksum == edid_block_checksum)
- return 1;
- else
- return 0;
-}\r
-static u8 ANX7150_Parse_ExtBlock(void)\r
-{
- u8 i,c;
-
- for (i = 0; i < ANX7150_Read_EDID_u8(0, 0x7e); i++) //read in blocks
- {
- c = ANX7150_Read_EDID_u8(i/2, 0x80);
- if ( c == 0x02)
- {
- ANX7150_ext_block_num = i + 1;
- ANX7150_Parse_DTDinExtBlock();
- ANX7150_Parse_STD();
- if (!(ANX7150_EDID_Checksum(ANX7150_ext_block_num)))
- {
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;
- return ANX7150_edid_result.edid_errcode;
- }
- }
- else
- {
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_ExtBlock_NotFor_861B;
- return ANX7150_edid_result.edid_errcode;
- }
- }
-
- return 0;
-}\r
-int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev)\r
-{\r
- int rc = 0, i;\r
- char c;\r
-\r
- if(dev->rk29_output_status == RK29_OUTPUT_STATUS_LCD)\r
- anx7150_mass_read_need_delay = 1;\r
- else\r
- anx7150_mass_read_need_delay = 0;\r
-\r
- /* Clear HDCP Authentication indicator */\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
-\r
- rc = ANX7150_GetEDIDLength(client);\r
-\r
- hdmi_dbg(&client->dev, "EDIDLength is %.u\n", ANX7150_edid_length);\r
-\r
- rc = ANX7150_Read_EDID(client);\r
- \r
- if(!(ANX7150_Parse_EDIDHeader()))\r
- {\r
- dev_err(&client->dev, "BAD EDID Header, Stop parsing \n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_BadHeader;\r
- goto err;\r
- }\r
-\r
- if(!(ANX7150_Parse_EDIDVersion()))\r
- {\r
- dev_err(&client->dev, "EDID does not support 861B, Stop parsing\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_861B_not_supported;\r
- goto err;\r
- }\r
-\r
-/*\r
- if(ANX7150_EDID_Checksum(0) == 0)\r
- {\r
- D("EDID Block one check sum error, Stop parsing\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;\r
- return ANX7150_edid_result.edid_errcode;\r
- }\r
-*/\r
-\r
- //ANX7150_Parse_BasicDis();\r
- ANX7150_Parse_DTDinBlockONE();\r
- /*\r
- if(ANX7150_EDID_Buf[0x7e] == 0)\r
- {\r
- D("No EDID extension blocks.\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_No_ExtBlock;\r
- return ANX7150_edid_result.edid_errcode;\r
- }*/\r
- ANX7150_Parse_NativeFormat();\r
- ANX7150_Parse_ExtBlock();\r
-\r
- if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_ExtBlock_NotFor_861B){\r
- dev_err(&client->dev,"EDID ExtBlock not support for 861B, Stop parsing\n");\r
- goto err;\r
- }\r
-\r
- if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_CheckSum_ERR){\r
- dev_err(&client->dev,"EDID Block check sum error, Stop parsing\n");\r
- goto err;\r
- }\r
-\r
- hdmi_dbg(&client->dev,"EDID parsing finished!\n");\r
-\r
- {\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.edid_errcode = 0x%.2x\n",(u32)ANX7150_edid_result.edid_errcode);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.is_HDMI = 0x%.2x\n",(u32)ANX7150_edid_result.is_HDMI);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr422_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr422_supported);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr444_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr444_supported);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_640x480p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480i_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576i_50Hz);\r
- if (!ANX7150_edid_result.edid_errcode)\r
- {\r
- for (i = 0; i < ANX7150_sau_length/3; i++)\r
- {\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioChannel = 0x%.2x\n",(u32)ANX7150_edid_result.AudioChannel[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFormat = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFormat[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFs = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFs[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioLength = 0x%.2x\n",(u32)ANX7150_edid_result.AudioLength[i]);\r
- }\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.SpeakerFormat = 0x%.2x\n",(u32)ANX7150_edid_result.SpeakerFormat);\r
- }\r
- }\r
- \r
- ANX7150_parse_edid_done = 1;\r
-\r
- return 0;\r
- \r
-err:\r
- return ANX7150_edid_result.edid_errcode;\r
-}\r
-int ANX7150_GET_SENSE_STATE(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "enter\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
-\r
- return (c & ANX7150_SYS_STATE_RSV_DET) ? 1 : 0;\r
-}\r
-int ANX7150_Get_Optimal_resolution(int resolution_set)\r
-{\r
- int resolution_real;\r
- int find_resolution = 0;\r
-\r
- switch(resolution_set){\r
- case HDMI_1280x720p_50Hz:\r
- if(ANX7150_edid_result.supported_720p_50Hz){\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- if(ANX7150_edid_result.supported_720p_60Hz){\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz:\r
- if(ANX7150_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- if(ANX7150_edid_result.supported_1080p_50Hz){\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- if(find_resolution == 0){\r
-\r
- if(ANX7150_edid_result.supported_720p_50Hz)\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- else if(ANX7150_edid_result.supported_720p_60Hz)\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- else if(ANX7150_edid_result.supported_576p_50Hz)\r
- resolution_real = HDMI_720x576p_50Hz;\r
- else if(ANX7150_edid_result.supported_1080p_50Hz)\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- else\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- }\r
-\r
- return resolution_real;\r
-}\r
-void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF)\r
-{ \r
- ANX7150_HDCP_enable = HDCP_ONorOFF;// 1: on; 0:off\r
-}\r
-static void ANX7150_API_Video_Config(u8 video_id,u8 input_pixel_rpt_time)\r
-{
- ANX7150_video_timing_id = video_id;
- ANX7150_in_pix_rpt = input_pixel_rpt_time;
-}\r
-static void ANX7150_API_Packets_Config(u8 pkt_sel)\r
-{
- s_ANX7150_packet_config.packets_need_config = pkt_sel;
-}\r
-static void ANX7150_API_AVI_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
- u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10,u8 pb11,u8 pb12,u8 pb13)
-{
- s_ANX7150_packet_config.avi_info.pb_u8[1] = pb1;
- s_ANX7150_packet_config.avi_info.pb_u8[2] = pb2;
- s_ANX7150_packet_config.avi_info.pb_u8[3] = pb3;
- s_ANX7150_packet_config.avi_info.pb_u8[4] = pb4;
- s_ANX7150_packet_config.avi_info.pb_u8[5] = pb5;
- s_ANX7150_packet_config.avi_info.pb_u8[6] = pb6;
- s_ANX7150_packet_config.avi_info.pb_u8[7] = pb7;
- s_ANX7150_packet_config.avi_info.pb_u8[8] = pb8;
- s_ANX7150_packet_config.avi_info.pb_u8[9] = pb9;
- s_ANX7150_packet_config.avi_info.pb_u8[10] = pb10;
- s_ANX7150_packet_config.avi_info.pb_u8[11] = pb11;
- s_ANX7150_packet_config.avi_info.pb_u8[12] = pb12;
- s_ANX7150_packet_config.avi_info.pb_u8[13] = pb13;
-}\r
-static void ANX7150_API_AUD_INFO_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
- u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10)
-{
- s_ANX7150_packet_config.audio_info.pb_u8[1] = pb1;
- s_ANX7150_packet_config.audio_info.pb_u8[2] = pb2;
- s_ANX7150_packet_config.audio_info.pb_u8[3] = pb3;
- s_ANX7150_packet_config.audio_info.pb_u8[4] = pb4;
- s_ANX7150_packet_config.audio_info.pb_u8[5] = pb5;
- s_ANX7150_packet_config.audio_info.pb_u8[6] = pb6;
- s_ANX7150_packet_config.audio_info.pb_u8[7] = pb7;
- s_ANX7150_packet_config.audio_info.pb_u8[8] = pb8;
- s_ANX7150_packet_config.audio_info.pb_u8[9] = pb9;
- s_ANX7150_packet_config.audio_info.pb_u8[10] = pb10;
-}\r
-static void ANX7150_API_AUD_CHStatus_Config(u8 MODE,u8 PCM_MODE,u8 SW_CPRGT,u8 NON_PCM,\r
- u8 PROF_APP,u8 CAT_CODE,u8 CH_NUM,u8 SOURCE_NUM,u8 CLK_ACCUR,u8 Fs)
-{
- //MODE: 0x00 = PCM Audio
- //PCM_MODE: 0x00 = 2 audio channels without pre-emphasis;
- //0x01 = 2 audio channels with 50/15 usec pre-emphasis;
- //SW_CPRGT: 0x00 = copyright is asserted;
- // 0x01 = copyright is not asserted;
- //NON_PCM: 0x00 = Represents linear PCM
- //0x01 = For other purposes
- //PROF_APP: 0x00 = consumer applications;
- // 0x01 = professional applications;
-
- //CAT_CODE: Category code
- //CH_NUM: 0x00 = Do not take into account
- // 0x01 = left channel for stereo channel format
- // 0x02 = right channel for stereo channel format
- //SOURCE_NUM: source number
- // 0x00 = Do not take into account
- // 0x01 = 1; 0x02 = 2; 0x03 = 3
- //CLK_ACCUR: 0x00 = level II
- // 0x01 = level I
- // 0x02 = level III
- // else reserved;
-
- s_ANX7150_audio_config.i2s_config.Channel_status1 = (MODE << 7) | (PCM_MODE << 5) |
- (SW_CPRGT << 2) | (NON_PCM << 1) | PROF_APP;
- s_ANX7150_audio_config.i2s_config.Channel_status2 = CAT_CODE;
- s_ANX7150_audio_config.i2s_config.Channel_status3 = (CH_NUM << 7) | SOURCE_NUM;
- s_ANX7150_audio_config.i2s_config.Channel_status4 = (CLK_ACCUR << 5) | Fs;\r
-}\r
-void ANX7150_API_System_Config(void)\r
-{\r
- ANX7150_API_Video_Config(g_video_format,input_pixel_clk_1x_repeatition);\r
- ANX7150_API_Packets_Config(ANX7150_avi_sel | ANX7150_audio_sel);\r
- if (s_ANX7150_packet_config.packets_need_config & ANX7150_avi_sel)\r
- ANX7150_API_AVI_Config( 0x00,source_ratio,null,null,null,null,null,null,null,null,null,null,null);\r
- if (s_ANX7150_packet_config.packets_need_config & ANX7150_audio_sel)\r
- ANX7150_API_AUD_INFO_Config(null,null,null,null,null,null,null,null,null,null);\r
- ANX7150_API_AUD_CHStatus_Config(null,null,null,null,null,null,null,null,null,g_audio_format);\r
-\r
-// ANX7150_system_config_done = 1;\r
-}\r
-\r
-static int anx7150_blue_screen_format_config(struct i2c_client *client)\r
-{\r
- int rc = 0 ;\r
- char c;\r
- \r
- // TODO:Add ITU 601 format.(Now only ITU 709 format added)\r
- switch (ANX7150_RGBorYCbCr)\r
- {\r
- case ANX7150_RGB: //select RGB mode\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- case ANX7150_YCbCr422: //select YCbCr4:2:2 mode\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xad;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x2a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- case ANX7150_YCbCr444: //select YCbCr4:4:4 mode\r
- c = 0x1a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xad;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x2a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- default:\r
- break;\r
- }\r
- return rc;\r
-}\r
-static void ANX7150_Get_Video_Timing(void)\r
-{\r
- u8 i;\r
- \r
-//#ifdef ITU656\r
- for (i = 0; i < 18; i++)\r
- {\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V640x480p_60Hz:\r
- //D("640x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_640x480p_60Hz[i];\r
- break;\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- //D("720x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480p_60Hz[i];\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- //D("1280x720p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_60Hz[i];\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- //D("1920x1080i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_60Hz[i];\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- //D("720x480i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480i_60Hz[i];\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- //D("720x576p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576p_50Hz[i];\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- //D("1280x720p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_50Hz[i];\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- //D("1920x1080i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_50Hz[i];\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- //D("720x576i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576i_50Hz[i];\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
- }\r
- /*#else\r
- for(i = 0; i < 18; i++)\r
- {\r
- switch(ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V640x480p_60Hz:\r
- //D("640x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- //D("720x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 18 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- //D("1280x720p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 36 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- //D("1920x1080i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 54 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- //D("720x480i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 72 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- //D("720x576p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 90 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- //D("1280x720p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 108 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- //D("1920x1080i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 126 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- //D("720x576i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 144 + i);\r
- DRVDelayMs(3);\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
- }\r
- #endif*/\r
-}\r
-static void ANX7150_Parse_Video_Format(void)\r
-{\r
- switch (ANX7150_video_format_config)\r
- {\r
- case ANX7150_RGB_YCrCb444_SepSync:\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- //D("RGB_YCrCb444_SepSync mode!\n");\r
- break;\r
- case ANX7150_YCrCb422_SepSync:\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- //D("YCrCb422_SepSync mode!\n");\r
- break;\r
- case ANX7150_YCrCb422_EmbSync:\r
- //D("YCrCb422_EmbSync mode!\n");\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCMux422_SepSync_Mode1:\r
- //D("YCMux422_SepSync_Mode1 mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ycmux_u8_sel = 0;\r
- ANX7150_demux_yc_en = 1;\r
- break;\r
- case ANX7150_YCMux422_SepSync_Mode2:\r
- //D("YCMux422_SepSync_Mode2 mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ycmux_u8_sel = 1;\r
- ANX7150_demux_yc_en = 1;\r
- break;\r
- case ANX7150_YCMux422_EmbSync_Mode1:\r
- //D("YCMux422_EmbSync_Mode1 mode!\n");\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ycmux_u8_sel = 0;\r
- ANX7150_demux_yc_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCMux422_EmbSync_Mode2:\r
- //D("YCMux422_EmbSync_Mode2 mode!\n");\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ycmux_u8_sel = 1;\r
- ANX7150_demux_yc_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_RGB_YCrCb444_DDR_SepSync:\r
- //D("RGB_YCrCb444_DDR_SepSync mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ddr_bus_mode = 1;\r
- break;\r
- case ANX7150_RGB_YCrCb444_DDR_EmbSync:\r
- //D("RGB_YCrCb444_DDR_EmbSync mode!\n");\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ddr_bus_mode = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_RGB_YCrCb444_SepSync_No_DE:\r
- //D("RGB_YCrCb444_SepSync_No_DE mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCrCb422_SepSync_No_DE:\r
- //D("YCrCb422_SepSync_No_DE mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- default:\r
- break;\r
- }\r
-}\r
-static int anx7150_de_generator(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- u8 video_type,hsync_pol,vsync_pol,v_fp,v_bp,vsync_width;\r
- u8 hsync_width_low,hsync_width_high,v_active_low,v_active_high;\r
- u8 h_active_low,h_active_high,h_res_low,h_res_high,h_bp_low,h_bp_high;\r
- u32 hsync_width,h_active,h_res,h_bp;\r
-\r
- video_type = ANX7150_video_timing_parameter[15];\r
- hsync_pol = ANX7150_video_timing_parameter[16];\r
- vsync_pol = ANX7150_video_timing_parameter[17];\r
- v_fp = ANX7150_video_timing_parameter[12];\r
- v_bp = ANX7150_video_timing_parameter[11];\r
- vsync_width = ANX7150_video_timing_parameter[10];\r
- hsync_width = ANX7150_video_timing_parameter[5];\r
- hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
- v_active_high = ANX7150_video_timing_parameter[9];\r
- v_active_low = ANX7150_video_timing_parameter[8];\r
- h_active = ANX7150_video_timing_parameter[3];\r
- h_active = (h_active << 8) + ANX7150_video_timing_parameter[2];\r
- h_res = ANX7150_video_timing_parameter[1];\r
- h_res = (h_res << 8) + ANX7150_video_timing_parameter[0];\r
- h_bp = ANX7150_video_timing_parameter[7];\r
- h_bp = (h_bp << 8) + ANX7150_video_timing_parameter[6];\r
- if (ANX7150_demux_yc_en)\r
- {\r
- hsync_width = 2* hsync_width;\r
- h_active = 2 * h_active;\r
- h_res = 2 * h_res;\r
- h_bp = 2 * h_bp;\r
- }\r
- hsync_width_low = hsync_width & 0xff;\r
- hsync_width_high = (hsync_width >> 8) & 0xff;\r
- h_active_low = h_active & 0xff;\r
- h_active_high = (h_active >> 8) & 0xff;\r
- h_res_low = h_res & 0xff;\r
- h_res_high = (h_res >> 8) & 0xff;\r
- h_bp_low = h_bp & 0xff;\r
- h_bp_high = (h_bp >> 8) & 0xff;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xf7) | video_type;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xdf) | hsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xbf) | vsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = v_active_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEL_REG, &c);\r
- c = v_active_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEH_REG, &c);\r
- c = vsync_width;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
- c = v_bp;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_TAIL2VIDLINE_REG, &c);\r
- c = h_active_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXL_REG, &c);\r
- c = h_active_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXH_REG, &c);\r
- c = h_res_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESL_REG, &c);\r
- c = h_res_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESH_REG, &c);\r
- c = hsync_width_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
- c = hsync_width_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
- c = h_bp_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHL_REG, &c);\r
- c = h_bp_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHH_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= ANX7150_VID_CAPCTRL0_DEGEN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int anx7150_embed_sync_decode(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- u8 video_type,hsync_pol,vsync_pol,v_fp,vsync_width;\r
- u8 h_fp_low,h_fp_high,hsync_width_low,hsync_width_high;\r
- u32 h_fp,hsync_width;\r
- \r
- video_type = ANX7150_video_timing_parameter[15];\r
- hsync_pol = ANX7150_video_timing_parameter[16];\r
- vsync_pol = ANX7150_video_timing_parameter[17];\r
- v_fp = ANX7150_video_timing_parameter[12];\r
- vsync_width = ANX7150_video_timing_parameter[10];\r
- h_fp = ANX7150_video_timing_parameter[14];\r
- h_fp = (h_fp << 8) + ANX7150_video_timing_parameter[13];\r
- hsync_width = ANX7150_video_timing_parameter[5];\r
- hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
- if (ANX7150_demux_yc_en)\r
- {\r
- h_fp = 2 * h_fp;\r
- hsync_width = 2* hsync_width;\r
- }\r
- h_fp_low = h_fp & 0xff;\r
- h_fp_high = (h_fp >> 8) & 0xff;\r
- hsync_width_low = hsync_width & 0xff;\r
- hsync_width_high = (hsync_width >> 8) & 0xff;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xf7) | video_type;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xdf) | hsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xbf) | vsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c = c | ANX7150_VID_CAPCTRL0_EMSYNC_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- c = v_fp;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINE2VSYNC_REG, &c);\r
- c = vsync_width;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
- c = h_fp_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHL_REG, &c);\r
- c = h_fp_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHH_REG, &c);\r
- c = hsync_width_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
- c = hsync_width_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
- return rc;\r
-}\r
-int ANX7150_Blue_Screen(struct anx7150_pdata *anx)\r
-{\r
- return anx7150_blue_screen_format_config(anx->client);\r
-}\r
-//******************************Video Config***************************************\r
-int ANX7150_Config_Video(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c,TX_is_HDMI;\r
- char cspace_y2r, y2r_sel, up_sample,range_y2r;\r
-\r
- cspace_y2r = 0;\r
- y2r_sel = 0;\r
- up_sample = 0;\r
- range_y2r = 0;\r
-\r
- //ANX7150_RGBorYCbCr = 0x00; //RGB\r
- //ANX7150_RGBorYCbCr = ANX7150_INPUT_COLORSPACE; //update\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-/*\r
- if (!ANX7150_system_config_done)\r
- {\r
- D("System has not finished config!\n");\r
- return;\r
- }\r
-*/\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
- if (!(c & 0x02))\r
- {\r
- hdmi_dbg(&client->dev, "No clock detected !\n");\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL2_REG, 0x02);\r
- return -1;\r
- }\r
-\r
- rc = anx7150_clean_hdcp(client);\r
-\r
- //color space issue\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V1280x720p_50Hz:\r
- case ANX7150_V1280x720p_60Hz:\r
- case ANX7150_V1920x1080i_60Hz:\r
- case ANX7150_V1920x1080i_50Hz:\r
- case ANX7150_V1920x1080p_60Hz:\r
- case ANX7150_V1920x1080p_50Hz:\r
- y2r_sel = ANX7150_CSC_BT709;\r
- break;\r
- default:\r
- y2r_sel = ANX7150_CSC_BT601;\r
- break;\r
- }\r
- //rang[0~255]/[16~235] select\r
- if (ANX7150_video_timing_id == ANX7150_V640x480p_60Hz)\r
- range_y2r = 1;//rang[0~255]\r
- else\r
- range_y2r = 0;//rang[16~235]\r
- if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr422) && (!ANX7150_edid_result.ycbcr422_supported))\r
- {\r
- up_sample = 1;\r
- if (ANX7150_edid_result.ycbcr444_supported)\r
- cspace_y2r = 0;\r
- else\r
- cspace_y2r = 1;\r
- }\r
- if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr444) && (!ANX7150_edid_result.ycbcr444_supported))\r
- {\r
- cspace_y2r = 1;\r
- }\r
- //Config the embeded blue screen format according to output video format.\r
- rc = anx7150_blue_screen_format_config(client);\r
-\r
- ANX7150_Parse_Video_Format();\r
-\r
- if (ANX7150_de_gen_en)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_de_gen_en!\n");\r
- rc = anx7150_de_generator(client);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DEGEN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- if (ANX7150_emb_sync_mode)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Embed_Sync_Decode!\n");\r
- rc = anx7150_embed_sync_decode(client);\r
- \r
- if (ANX7150_ddr_bus_mode) //jack wen; for DDR embeded sync\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c |= (0x04);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c &= (0xfb);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_EMSYNC_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- if (ANX7150_demux_yc_en)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- \r
- if (ANX7150_ycmux_u8_sel)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D1-4\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D1-4\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
- //\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D5-8,\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D5-8\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- \r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
- //\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- //jack wen\r
-\r
- //\r
-\r
- }\r
- if (ANX7150_ddr_bus_mode)\r
- {\r
- //D("ANX7150_ddr_bus_mode!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- //jack wen\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c = (c & 0xfc) | 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- \r
- //jack wen\r
-\r
- if (ANX7150_ddr_edge)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
-\r
- //jack wen for DDR+seperate maping\r
- if (ANX7150_video_format_config == 0x07)//jack wen, DDR yc422, 601,\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_DDR_601_Maping!\n");\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL23, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL22, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL21, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL20, &c);\r
- c = 0x07;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL19, &c);\r
- c = 0x06;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL18, &c);\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL17, &c);\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL16, &c);\r
-\r
- c = 0x17;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
- c = 0x16;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
- c = 0x15;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL13, &c);\r
- c = 0x14;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
- c = 0x13;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x12;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x11;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
-\r
- c = 0x03;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
- c = 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
- c = 0x0f;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
- c = 0x0e;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL2, &c);\r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL1, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL0, &c);\r
-\r
- }\r
- else if (ANX7150_video_format_config == 0x08)//jack wen, DDR yc422, 656,\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_DDR_656_Maping!\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c &= (0xfc);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
-\r
- if (cspace_y2r)\r
- {\r
- hdmi_dbg(&client->dev, "Color space Y2R enabled********\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_CSPACE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- if (y2r_sel)\r
- {\r
- hdmi_dbg(&client->dev, "Y2R_SEL!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_Y2R_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_Y2R_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c); \r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_CSPACE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (up_sample)\r
- {\r
- hdmi_dbg(&client->dev, "UP_SAMPLE!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_UPSAMPLE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_UPSAMPLE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (range_y2r)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_RANGE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_RANGE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (!ANX7150_pix_rpt_set_by_sys)\r
- {\r
- if ((ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_16x9)\r
- || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_16x9)\r
- || (ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_4x3)\r
- || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_4x3))\r
- ANX7150_tx_pix_rpt = 1;\r
- else\r
- ANX7150_tx_pix_rpt = 0;\r
- }\r
- //set input pixel repeat times\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c = ((c & 0xfc) |ANX7150_in_pix_rpt);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- //set link pixel repeat times\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c = ((c & 0xfc) |ANX7150_tx_pix_rpt);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- if ((ANX7150_in_pix_rpt != ANX7150_in_pix_rpt_bkp)\r
- ||(ANX7150_tx_pix_rpt != ANX7150_tx_pix_rpt_bkp) )\r
- {\r
- c = 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- hdmi_dbg(&client->dev, "MISC_Reset!\n");\r
- ANX7150_in_pix_rpt_bkp = ANX7150_in_pix_rpt;\r
- ANX7150_tx_pix_rpt_bkp = ANX7150_tx_pix_rpt;\r
- }\r
- //enable video input\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //D("Video configure OK!\n");\r
- msleep(60);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_STATUS_REG, &c);\r
- if (!(c & ANX7150_VID_STATUS_VID_STABLE))\r
- {\r
- hdmi_dbg(&client->dev,"Video not stable!\n");\r
- return -1;\r
- }\r
- if (cspace_y2r)\r
- ANX7150_RGBorYCbCr = ANX7150_RGB;\r
- //Enable video CLK,Format change after config video.\r
- // ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
- // ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, c |0x01);//3\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
- c |= (0x48);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
- c |= (0x40);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
- \r
- if (ANX7150_edid_result.is_HDMI)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x02);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- hdmi_dbg(&client->dev,"ANX7150 is set to HDMI mode\n");\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- TX_is_HDMI = c & 0x02;\r
-\r
- if (TX_is_HDMI == 0x02)\r
- {\r
- anx7150_set_avmute(client);//wen\r
- }\r
-\r
- //reset TMDS link to align 4 channels xy 061120\r
- hdmi_dbg(&client->dev,"reset TMDS link to align 4 channels\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c |= (ANX7150_TX_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c &= (~ANX7150_TX_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- \r
- //Enable TMDS clock output // just enable u87, and let the other u8s along to avoid overwriting.\r
- hdmi_dbg(&client->dev,"Enable TMDS clock output\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c |= (ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- if(ANX7150_HDCP_enable)\r
- msleep(400); //400ms only for HDCP CTS\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_VID_MODE_REG, &c); //zy 061110\r
- return 0;\r
-}\r
-static u8 anx7150_config_i2s(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c = 0x00;\r
- u8 exe_result = 0x00;\r
- char c1 = 0x00;\r
-\r
- hdmi_dbg(&client->dev,"ANX7150: config i2s audio.\n");\r
-\r
- //select SCK as source\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_CLK_SEL;\r
- hdmi_dbg(&client->dev,"select SCK as source, c = 0x%.2x\n",(u32)c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
-\r
- //config i2s channel\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c1 = s_ANX7150_audio_config.i2s_config.audio_channel; // need u8[5:2]\r
- c1 &= 0x3c;\r
- c &= ~0x3c;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s channel, c = 0x%.2x\n",(u32)c);\r
- \r
- //config i2s format\r
- //ANX7150_i2c_read_p0_reg(ANX7150_I2S_CTRL_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.i2s_format;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s format, c = 0x%.2x\n",(u32)c);\r
-\r
- //map i2s fifo\r
-\r
- //TODO: config I2S channel map register according to system\r
-\r
-\r
- //ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_CTRL_REG, c);\r
-\r
- //swap right/left channel\r
- /*ANX7150_i2c_read_p0_reg(ANX7150_I2SCH_SWCTRL_REG, &c);\r
- c1 = 0x00;\r
- c1 &= 0xf0;\r
- c &= ~0xf0;\r
- c |= c1;\r
- ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_SWCTRL_REG, c);\r
- D("map i2s ffio, c = 0x%.2x\n",(u32)c);*/\r
-\r
- //down sample\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c1 = s_ANX7150_audio_config.down_sample;\r
- c1 &= 0x60;\r
- c &= ~0x60;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev,"down sample, c = 0x%.2x\n",(u32)c);\r
-\r
- //config i2s channel status(5 regs)\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS1_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status2;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS2_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status3;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS3_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status4;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- hdmi_dbg(&client->dev,"@@@@@@@@config i2s channel status4, c = 0x%.2x\n",(unsigned int)c);//jack wen\r
-\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status5;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS5_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s channel status, c = 0x%.2x\n",(u32)c);\r
-\r
- exe_result = ANX7150_i2s_input;\r
- //D("return = 0x%.2x\n",(u32)exe_result);\r
-\r
- // open corresponding interrupt\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, (c | 0x22) );\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0x20) );\r
-\r
-\r
- return exe_result;\r
-}\r
-\r
-static u8 anx7150_config_spdif(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- char c = 0x00;\r
- char c1 = 0x00;\r
- // u8 c2 = 0x00;\r
- // u8 freq_mclk = 0x00;\r
-\r
- hdmi_dbg(&client->dev, "ANX7150: config SPDIF audio.\n");\r
-\r
-\r
- //Select MCLK\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //D("ANX7150: enable SPDIF audio.\n");\r
- //Enable SPDIF\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //adjust MCLK phase in interrupt routine\r
-\r
- // adjust FS_FREQ //FS_FREQ\r
- c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
- c &= ANX7150_SPDIFCH_STATUS_FS_FREG;\r
- c = c >> 4;\r
-\r
- if ( c != c1)\r
- {\r
- //D("adjust FS_FREQ by system!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- c &= 0xf0;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
-\r
- //enable using FS_FREQ from 0x59\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (0x02);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- // down sample\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c1 = s_ANX7150_audio_config.down_sample;\r
- c1 &= 0x60;\r
- c &= ~0x60;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-\r
- if (s_ANX7150_audio_config.down_sample) //zy 060816\r
- {\r
- // adjust FS_FREQ by system because down sample\r
- //D("adjust FS_FREQ by system because down sample!\n");\r
-\r
- c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- \r
- c &= 0xf0;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- }\r
-\r
-\r
- // spdif is stable\r
- hdmi_dbg(&client->dev, "config SPDIF audio done");\r
- exe_result = ANX7150_spdif_input;\r
-\r
- // open corresponding interrupt\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
- c |= (0x32);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0xa1) );\r
- return exe_result;\r
-}\r
-\r
-static u8 anx7150_config_super_audio(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- u8 c = 0x00;\r
-\r
-\r
- //D("ANX7150: config one u8 audio.\n");\r
-\r
- // select sck as source\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- // Enable stream 0x60\r
- c = s_ANX7150_audio_config.super_audio_config.one_u8_ctrl;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
-\r
-\r
- // Map stream 0x61\r
- // TODO: config super audio map register according to system\r
-\r
- exe_result = ANX7150_super_audio_input;\r
- return exe_result;\r
-\r
-}\r
-\r
-u8 ANX7150_Config_Audio(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c = 0x00;\r
- u8 exe_result = 0x00;\r
- u8 audio_layout = 0x00;\r
- u8 fs = 0x00;\r
- u32 ACR_N = 0x0000;\r
-\r
- //set audio clock edge\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = ((c & 0xf7) | ANX7150_audio_clock_edge);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- \r
- //cts get select from SCK\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xef);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev, "audio_type = 0x%.2x\n",(u32)s_ANX7150_audio_config.audio_type);\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
- {\r
- hdmi_dbg(&client->dev, "Config I2s.\n");\r
- exe_result |= anx7150_config_i2s(client);\r
- }\r
- else\r
- {\r
- //disable I2S audio input\r
- hdmi_dbg(&client->dev, "Disable I2S audio input.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= 0xc3;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_spdif_input)\r
- {\r
- exe_result |= anx7150_config_spdif(client);\r
- }\r
- else\r
- {\r
- //disable SPDIF audio input\r
- hdmi_dbg(&client->dev, "Disable SPDIF audio input.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
- {\r
- exe_result |= anx7150_config_super_audio(client);\r
- }\r
- else\r
- {\r
- //disable super audio output\r
- hdmi_dbg(&client->dev, "ANX7150: disable super audio output.\n");\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
- }\r
-\r
- if ((s_ANX7150_audio_config.audio_type & 0x07) == 0x00)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150 input no audio type.\n");\r
- }\r
-\r
- //audio layout\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
- {\r
- //ANX7150_i2c_read_p0_reg(ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- audio_layout = s_ANX7150_audio_config.audio_layout;\r
-\r
- //HDMI_RX_ReadI2C_RX0(0x15, &c);\r
-#if 0\r
- if ((c & 0x08) ==0x08 ) //u8[5:3]\r
- {\r
- audio_layout = 0x80;\r
- }\r
- else\r
- {\r
- audio_layout = 0x00;\r
- }\r
-#endif\r
- }\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
- if ( c & 0xfc) //u8[5:3]\r
- {\r
- audio_layout = 0x80;\r
- }\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c &= ~0x80;\r
- c |= audio_layout;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-\r
- if ( (s_ANX7150_audio_config.audio_type & 0x07) == exe_result )\r
- {\r
- //Initial N value\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- fs = c & 0x0f;\r
- // set default value to N\r
- ACR_N = ANX7150_N_48k;\r
- switch (fs)\r
- {\r
- case(0x00)://44.1k\r
- ACR_N = ANX7150_N_44k;\r
- break;\r
- case(0x02)://48k\r
- ACR_N = ANX7150_N_48k;\r
- break;\r
- case(0x03)://32k\r
- ACR_N = ANX7150_N_32k;\r
- break;\r
- case(0x08)://88k\r
- ACR_N = ANX7150_N_88k;\r
- break;\r
- case(0x0a)://96k\r
- ACR_N = ANX7150_N_96k;\r
- break;\r
- case(0x0c)://176k\r
- ACR_N = ANX7150_N_176k;\r
- break;\r
- case(0x0e)://192k\r
- ACR_N = ANX7150_N_192k;\r
- break;\r
- default:\r
- dev_err(&client->dev, "note wrong fs.\n");\r
- break;\r
- }\r
- // write N(ACR) to corresponding regs\r
- c = ACR_N;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N1_SW_REG, &c);\r
- c = ACR_N>>8;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N2_SW_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N3_SW_REG, &c);\r
- \r
- // set the relation of MCLK and Fs xy 070117\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xf8) | FREQ_MCLK;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev, "Audio MCLK input mode is: %.2x\n",(u32)FREQ_MCLK);\r
-\r
- //Enable control of ACR\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= (ANX7150_INFO_PKTCTRL1_ACR_EN);\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- //audio enable:\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- return exe_result;\r
-\r
-}\r
-static u8 ANX7150_Checksum(infoframe_struct *p)\r
-{
- u8 checksum = 0x00;
- u8 i;
-
- checksum = p->type + p->length + p->version;
- for (i=1; i <= p->length; i++)
- {
- checksum += p->pb_u8[i];
- }
- checksum = ~checksum;
- checksum += 0x01;
-
- return checksum;
-}\r
-static u8 anx7150_load_infoframe(struct i2c_client *client, packet_type member,\r
- infoframe_struct *p)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- u8 address[8] = {0x00,0x20,0x40,0x60,0x80,0x80,0xa0,0xa0};\r
- u8 i;\r
- char c;\r
-\r
- p->pb_u8[0] = ANX7150_Checksum(p);\r
-\r
- // write infoframe to according regs\r
- c = p->type;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member], &c);\r
- c = p->version;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+1, &c);\r
- c = p->length;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+2, &c);\r
-\r
- for (i=0; i <= p->length; i++)\r
- {\r
- c = p->pb_u8[i];\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+3+i, &c);\r
- rc = anx7150_i2c_read_p1_reg(client, address[member]+3+i, &c);\r
- }\r
- return exe_result;\r
-}\r
-\r
-//*************** Config Packet ****************************\r
-u8 ANX7150_Config_Packet(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00; // There is no use in current solution\r
- u8 info_packet_sel;\r
- char c;\r
-\r
- info_packet_sel = s_ANX7150_packet_config.packets_need_config;\r
- hdmi_dbg(&client->dev, "info_packet_sel = 0x%.2x\n",(u32) info_packet_sel);\r
- // New packet?\r
- if ( info_packet_sel != 0x00)\r
- {\r
- // avi infoframe\r
- if ( info_packet_sel & ANX7150_avi_sel )\r
- {\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[1]; //color space\r
- c &= 0x9f;\r
- c |= (ANX7150_RGBorYCbCr << 5);\r
- s_ANX7150_packet_config.avi_info.pb_u8[1] = c | 0x10;\r
-\r
- switch(ANX7150_video_timing_id) {\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x59;\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xaa;\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xaa;\r
- break;\r
- default:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xaa;\r
- break;\r
- }\r
-\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[4];// vid ID\r
- c = c & 0x80;\r
- s_ANX7150_packet_config.avi_info.pb_u8[4] = c | ANX7150_video_timing_id;\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[5]; //repeat times\r
- c = c & 0xf0;\r
- c |= (ANX7150_tx_pix_rpt & 0x0f);\r
- s_ANX7150_packet_config.avi_info.pb_u8[5] = c;\r
- hdmi_dbg(&client->dev, "config avi infoframe packet.\n");\r
- // Disable repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL1_AVI_RPT;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
-\r
- // Enable?wait:go\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- if (c & ANX7150_INFO_PKTCTRL1_AVI_EN)\r
- {\r
- //D("wait disable, config avi infoframe packet.\n");\r
- return exe_result; //jack wen\r
- }\r
-\r
- // load packet data to regs\r
- rc = anx7150_load_infoframe(client, ANX7150_avi_infoframe,\r
- &(s_ANX7150_packet_config.avi_info));\r
- // Enable and repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= 0x30;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
-\r
- // complete avi packet\r
- hdmi_dbg(&client->dev, "config avi infoframe packet done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~ANX7150_avi_sel;\r
-\r
- }\r
-\r
- // audio infoframe\r
- if ( info_packet_sel & ANX7150_audio_sel )\r
- {\r
- hdmi_dbg(&client->dev, "config audio infoframe packet.\n");\r
-\r
- // Disable repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
- // Enable?wait:go\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if (c & ANX7150_INFO_PKTCTRL2_AIF_EN)\r
- {\r
- //D("wait disable, config audio infoframe packet.\n");\r
- //return exe_result;//jack wen\r
- }\r
- // config packet\r
-\r
- // load packet data to regs\r
- \r
- anx7150_load_infoframe( client, ANX7150_audio_infoframe,\r
- &(s_ANX7150_packet_config.audio_info));\r
- // Enable and repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x03;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
- // complete avi packet\r
-\r
- hdmi_dbg(&client->dev, "config audio infoframe packet done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~ANX7150_audio_sel;\r
-\r
- }\r
-\r
- // config other 4 packets\r
- /*\r
-\r
- if( info_packet_sel & 0xfc )\r
- {\r
- D("other packets.\n");\r
-\r
- //find the current type need config\r
- if(info_packet_sel & ANX7150_spd_sel) type_sel = ANX7150_spd_sel;\r
- else if(info_packet_sel & ANX7150_mpeg_sel) type_sel = ANX7150_mpeg_sel;\r
- else if(info_packet_sel & ANX7150_acp_sel) type_sel = ANX7150_acp_sel;\r
- else if(info_packet_sel & ANX7150_isrc1_sel) type_sel = ANX7150_isrc1_sel;\r
- else if(info_packet_sel & ANX7150_isrc2_sel) type_sel = ANX7150_isrc2_sel;\r
- else type_sel = ANX7150_vendor_sel;\r
-\r
-\r
- // Disable repeater\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- switch(type_sel)\r
- {\r
- case ANX7150_spd_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL1_SPD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL1_SPD_EN)\r
- {\r
- D("wait disable, config spd infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_mpeg_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_MPEG_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_MPEG_EN)\r
- {\r
- D("wait disable, config mpeg infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_acp_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
- {\r
- D("wait disable, config mpeg infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_isrc1_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
- {\r
- D("wait disable, config isrc1 packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_isrc2_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
- {\r
- D("wait disable, config isrc2 packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_vendor_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
- {\r
- D("wait disable, config vendor packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- default : break;\r
- }\r
-\r
-\r
- // config packet\r
- // TODO: config packet in top level\r
-\r
- // load packet data to regs\r
- switch(type_sel)\r
- {\r
- case ANX7150_spd_sel:\r
- ANX7150_Load_Infoframe( ANX7150_spd_infoframe,\r
- &(s_ANX7150_packet_config.spd_info));\r
- D("config spd done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
- break;\r
-\r
- case ANX7150_mpeg_sel:\r
- ANX7150_Load_Infoframe( ANX7150_mpeg_infoframe,\r
- &(s_ANX7150_packet_config.mpeg_info));\r
- D("config mpeg done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x0c;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_acp_sel:\r
- ANX7150_Load_Packet( ANX7150_acp_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config acp done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x30;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_isrc1_sel:\r
- ANX7150_Load_Packet( ANX7150_isrc1_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config isrc1 done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x30;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_isrc2_sel:\r
- ANX7150_Load_Packet( ANX7150_isrc2_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config isrc2 done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_vendor_sel:\r
- ANX7150_Load_Infoframe( ANX7150_vendor_infoframe,\r
- &(s_ANX7150_packet_config.vendor_info));\r
- D("config vendor done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- default : break;\r
- }\r
-\r
- // Enable and repeater\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x03;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- // complete config packet\r
- D("config other packets done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~type_sel;\r
-\r
- }\r
- */\r
- }\r
-\r
-\r
- if ( s_ANX7150_packet_config.packets_need_config == 0x00)\r
- {\r
- hdmi_dbg(&client->dev, "config packets done\n");\r
- //ANX7150_Set_System_State(ANX7150_HDCP_AUTHENTICATION);\r
- }\r
-\r
-\r
- return exe_result;\r
-}\r
-//******************** HDCP process ********************************\r
-static int anx7150_hardware_hdcp_auth_init(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
-\r
-// ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c); //72:07.2 hdcp on\r
-// ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, (c | ANX7150_SYS_CTRL1_HDCPMODE));\r
- // disable hw hdcp\r
-// ANX7150_i2c_read_p0_reg(ANX7150_HDCP_CTRL0_REG, &c);\r
-// ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, (c & (~ANX7150_HDCP_CTRL0_HW_AUTHEN)));\r
-\r
- //ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, 0x03); //h/w auth off, jh simplay/hdcp\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //bit 0/1 off, as from start, we don't know if Bksv/srm/KSVList valid or not. SY.\r
-\r
- // DDC reset\r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- anx7150_initddc_read(client, 0x74, 0x00, 0x40, 0x01, 0x00);\r
- msleep(5);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bcaps);\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): ANX7150_hdcp_bcaps = 0x%.2x\n", (u32)ANX7150_hdcp_bcaps);\r
-\r
- if (ANX7150_hdcp_bcaps & 0x02)\r
- { //enable 1.1 feature\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps supports 1.1\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c |= ANX7150_HDCP_CTRL1_HDCP11_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
- else\r
- { //disable 1.1 feature and enable HDCP two special point check\r
- hdmi_dbg(&client->dev, "bcaps don't support 1.1\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
- //handle repeater bit. SY.\r
- if (ANX7150_hdcp_bcaps & 0x40)\r
- {\r
- //repeater\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a repeater\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= ANX7150_HDCP_CTRL0_RX_REP;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
- else\r
- {\r
- //receiver\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a receiver\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= ~ANX7150_HDCP_CTRL0_RX_REP;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
- anx7150_rst_ddcchannel(client);\r
- ANX7150_hdcp_auth_en = 0;\r
-\r
- return rc;\r
-}\r
-static u8 anx7150_bksv_srm(struct i2c_client *client)\r
-{
- int rc = 0;\r
-#if 1
- u8 bksv[5],i,bksv_one,c1;
- anx7150_initddc_read(client, 0x74, 0x00, 0x00, 0x05, 0x00);\r
- msleep(15);\r
- for (i = 0; i < 5; i ++)
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &bksv[i]);\r
- }
-
- bksv_one = 0;
- for (i = 0; i < 8; i++)
- {
- c1 = 0x01 << i;
- if (bksv[0] & c1)
- bksv_one ++;
- if (bksv[1] & c1)
- bksv_one ++;
- if (bksv[2] & c1)
- bksv_one ++;
- if (bksv[3] & c1)
- bksv_one ++;
- if (bksv[4] & c1)
- bksv_one ++;
- }
- //wen HDCP CTS
- if (bksv_one != 20)
- {
- hdmi_dbg(&client->dev, "BKSV check fail\n");\r
- return 0;
- }
- else
- {
- hdmi_dbg(&client->dev, "BKSV check OK\n");\r
- return 1;
- }
-#endif
-
-#if 0 //wen HDCP CTS
- /*address by gerard.zhu*/
- u8 i,j,bksv_ones_count,bksv_data[Bksv_Data_Nums] = {0};
- ANX7150_DDC_Addr bksv_ddc_addr;
- u32 bksv_length;
- ANX7150_DDC_Type ddc_type;
-
- i = 0;
- j = 0;
- bksv_ones_count = 0;
- bksv_ddc_addr.dev_addr = HDCP_Dev_Addr;
- bksv_ddc_addr.sgmt_addr = 0;
- bksv_ddc_addr.offset_addr = HDCP_Bksv_Offset;
- bksv_length = Bksv_Data_Nums;
- ddc_type = DDC_Hdcp;
-
- if (!ANX7150_DDC_Read(bksv_ddc_addr, bksv_data, bksv_length, ddc_type))
- {
- /*Judge validity for Bksv*/
- while (i < Bksv_Data_Nums)
- {
- while (j < 8)
- {
- if (((bksv_data[i] >> j) & 0x01) == 1)
- {
- bksv_ones_count++;
- }
- j++;
- }
- i++;
- j = 0;
- }
- if (bksv_ones_count != 20)
- {
- rk29printk ("!!!!BKSV 1s ¡Ù20\n"); //update rk29printk ("!!!!BKSV 1s ¡Ù20\n");
- return 0;
- }
- }
- /*end*/
-
- D("bksv is ready.\n");
- // TODO: Compare the bskv[] value to the revocation list to decide if this value is a illegal BKSV. This is system depended.
- //If illegal, return 0; legal, return 1. Now just return 1
- return 1;
-#endif
-}\r
-\r
-static u8 anx7150_is_ksvlist_vld(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
-//wen HDCP CTS\r
-#if 1\r
- hdmi_dbg(&client->dev, "ANX7150_IS_KSVList_VLD() is called.\n");\r
- anx7150_initddc_read(client, 0x74, 0x00, 0x41, 0x02, 0x00); //Bstatus, two u8s\r
- msleep(5);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[0]);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[1]);\r
-\r
- if ((ANX7150_hdcp_bstatus[0] & 0x80) | (ANX7150_hdcp_bstatus[1] & 0x08))\r
- {\r
- hdmi_dbg(&client->dev, "Max dev/cascade exceeded: ANX7150_hdcp_bstatus[0]: 0x%x,ANX7150_hdcp_bstatus[1]:0x%x\n", (u32)ANX7150_hdcp_bstatus[0],(u32)ANX7150_hdcp_bstatus[1]);\r
- return 0;//HDCP topology error. More than 127 RX are attached or more than seven levels of repeater are cascaded.\r
- }\r
- return 1;\r
-#endif\r
-//wen HDCP CTS\r
-\r
-}\r
-\r
-static void anx7150_show_video_parameter(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- // int h_res,h_act,v_res,v_act,h_fp,hsync_width,h_bp;\r
- char c, c1;\r
-\r
- hdmi_dbg(&client->dev, "\n\n**********************************ANX7150 Info**********************************\n");\r
-\r
- hdmi_dbg(&client->dev, " ANX7150 mode = Normal mode\n");\r
- if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = YC_MUX\n");\r
- if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = 656\n");\r
- if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = YC_MUX + 656\n");\r
- if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = Seperate Sync\n");\r
- if (ANX7150_de_gen_en)\r
- hdmi_dbg(&client->dev, " DE generator = Enable\n");\r
- else\r
- hdmi_dbg(&client->dev, " DE generator = Disable\n");\r
- if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = DDR mode\n");\r
- else if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = DDR mode + 656\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c1);\r
- c1 = (c1 & 0x02);\r
- if (c1)\r
- {\r
- hdmi_dbg(&client->dev, " Output video mode = HDMI\n");\r
- rc = anx7150_i2c_read_p0_reg(client, 0x04, &c);\r
- c = (c & 0x60) >> 5;\r
- switch (c)\r
- {\r
- case ANX7150_RGB:\r
- hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
- break;\r
- case ANX7150_YCbCr422:\r
- hdmi_dbg(&client->dev, " Output video color format = YCbCr422\n");\r
- break;\r
- case ANX7150_YCbCr444:\r
- hdmi_dbg(&client->dev, " Output video color format = YCbCr444\n");\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, " Output video mode = DVI\n");\r
- hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
- }\r
-\r
- /*for(i = 0x10; i < 0x25; i ++)\r
- {\r
- ANX7150_i2c_read_p0_reg(i, &c );\r
- D("0x%.2x = 0x%.2x\n",(unsigned int)i,(unsigned int)c);\r
- }*/\r
- /* ANX7150_i2c_read_p0_reg(ANX7150_VID_STATUS_REG, &c);\r
- if((c & ANX7150_VID_STATUS_TYPE) == 0x04)\r
- D("Video Type = Interlace");\r
- else\r
- D("Video Type = Progressive");\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESH_REG, &c);\r
- h_res = c;\r
- h_res = h_res << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESL_REG, &c);\r
- h_res = h_res + c;\r
- D("H_resolution = %u\n",h_res);\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXH_REG, &c);\r
- h_act = c;\r
- h_act = h_act << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXL_REG, &c);\r
- h_act = h_act + c;\r
- D("H_active = %u\n",h_act);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESH_REG, &c);\r
- v_res = c;\r
- v_res = v_res << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESL_REG, &c);\r
- v_res = v_res + c;\r
- D("V_resolution = %u\n",v_res);\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEH_REG, &c);\r
- v_act = c;\r
- v_act = v_act << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEL_REG, &c);\r
- v_act = v_act + c;\r
- D("V_active = %u\n",v_act);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHH_REG, &c);\r
- h_fp = c;\r
- h_fp = h_fp << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHL_REG, &c);\r
- h_fp = h_fp + c;\r
- D("H_FP = %u\n",h_fp);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHH_REG, &c);\r
- h_bp = c;\r
- h_bp = h_bp << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHL_REG, &c);\r
- h_bp = h_bp + c;\r
- D("H_BP = %u\n",h_bp);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDH_REG, &c);\r
- hsync_width = c;\r
- hsync_width = hsync_width << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDL_REG, &c);\r
- hsync_width = hsync_width + c;\r
- D("Hsync_width = %u\n",hsync_width);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTLINE2VSYNC_REG, &c);\r
- D("Vsync_FP = %bu\n",c);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG, &c);\r
- D("Vsync_BP = %bu\n",c);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCWIDLINE_REG, &c);\r
- D("Vsync_width = %bu\n",c);*/\r
- {\r
- hdmi_dbg(&client->dev, " Normal mode output video format: \n");\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x480p@60\n");\r
- if (ANX7150_edid_result.supported_720x480p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- hdmi_dbg(&client->dev, "1280x720p@60\n");\r
- if (ANX7150_edid_result.supported_720p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- hdmi_dbg(&client->dev, "1920x1080i@60\n");\r
- if (ANX7150_edid_result.supported_1080i_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080p_60Hz:\r
- hdmi_dbg(&client->dev, "1920x1080p@60\n");\r
- if (ANX7150_edid_result.supported_1080p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080p_50Hz:\r
- hdmi_dbg(&client->dev, "1920x1080p@50\n");\r
- if (ANX7150_edid_result.supported_1080p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- hdmi_dbg(&client->dev, "1280x720p@50\n");\r
- if (ANX7150_edid_result.supported_720p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- hdmi_dbg(&client->dev, "1920x1080i@50\n");\r
- if (ANX7150_edid_result.supported_1080i_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x576p@50\n");\r
- if (ANX7150_edid_result.supported_576p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x576i@50\n");\r
- if (ANX7150_edid_result.supported_576i_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x480i@60\n");\r
- if (ANX7150_edid_result.supported_720x480i_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- default:\r
- hdmi_dbg(&client->dev, "unknown(video ID is: %.2x).\n",(u32)ANX7150_video_timing_id);\r
- break;\r
- }\r
- }\r
- if (c1)//HDMI output\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = c & 0x03;\r
- hdmi_dbg(&client->dev, " MCLK Frequence = ");\r
-\r
- switch (c)\r
- {\r
- case 0x00:\r
- hdmi_dbg(&client->dev, "128 * Fs.\n");\r
- break;\r
- case 0x01:\r
- hdmi_dbg(&client->dev, "256 * Fs.\n");\r
- break;\r
- case 0x02:\r
- hdmi_dbg(&client->dev, "384 * Fs.\n");\r
- break;\r
- case 0x03:\r
- hdmi_dbg(&client->dev, "512 * Fs.\n");\r
- break;\r
- default :\r
- hdmi_dbg(&client->dev, "Wrong MCLK output.\n");\r
- break;\r
- }\r
-\r
- if ( ANX7150_AUD_HW_INTERFACE == 0x01)\r
- {\r
- hdmi_dbg(&client->dev, " Input Audio Interface = I2S.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- }\r
- else if (ANX7150_AUD_HW_INTERFACE == 0x02)\r
- {\r
- hdmi_dbg(&client->dev, " Input Audio Interface = SPDIF.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
- c=c>>4;\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- hdmi_dbg(&client->dev, " Audio Fs = ");\r
- c &= 0x0f;\r
- switch (c)\r
- {\r
- case 0x00:\r
- hdmi_dbg(&client->dev, " Audio Fs = 44.1 KHz.\n");\r
- break;\r
- case 0x02:\r
- hdmi_dbg(&client->dev, " Audio Fs = 48 KHz.\n");\r
- break;\r
- case 0x03:\r
- hdmi_dbg(&client->dev, " Audio Fs = 32 KHz.\n");\r
- break;\r
- case 0x08:\r
- hdmi_dbg(&client->dev, " Audio Fs = 88.2 KHz.\n");\r
- break;\r
- case 0x0a:\r
- hdmi_dbg(&client->dev, " Audio Fs = 96 KHz.\n\n");\r
- break;\r
- case 0x0c:\r
- hdmi_dbg(&client->dev, " Audio Fs = 176.4 KHz.\n");\r
- break;\r
- case 0x0e:\r
- hdmi_dbg(&client->dev, " Audio Fs = 192 KHz.\n");\r
- hdmi_dbg(&client->dev, "192 KHz.\n");\r
- break;\r
- default :\r
- hdmi_dbg(&client->dev, " Audio Fs = Wrong Fs output.\n");\r
- hdmi_dbg(&client->dev, "Wrong Fs output.\n");\r
- break;\r
- }\r
-\r
- if (ANX7150_HDCP_enable == 1)\r
- hdmi_dbg(&client->dev, " ANX7150_HDCP_Enable.\n");\r
- else\r
- hdmi_dbg(&client->dev, " ANX7150_HDCP_Disable.\n");\r
-\r
- }\r
- hdmi_dbg(&client->dev, "\n********************************************************************************\n\n");\r
-}\r
-void ANX7150_HDCP_Process(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c,i;\r
- //u8 c1;\r
- u8 Bksv_valid=0;//wen HDCP CTS\r
-\r
- if (ANX7150_HDCP_enable)\r
- { //HDCP_EN =1 means to do HDCP authentication,SWITCH4 = 0 means not to do HDCP authentication.\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c | 0x04);//power on HDCP, 090630\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR2_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR2_MASK_REG, c |0x03);\r
- msleep(10);//let unencrypted video play a while, required by HDCP CTS. SY//wen HDCP CTS\r
- anx7150_set_avmute(client);//before auth, set_avmute//wen\r
- msleep(10);//wen HDCP CTS\r
-\r
- if ( !ANX7150_hdcp_init_done )\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= ANX7150_SYS_CTRL1_HDCPMODE;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- if (ANX7150_edid_result.is_HDMI)\r
- rc = anx7150_hardware_hdcp_auth_init(client);\r
- else\r
- { //DVI, disable 1.1 feature and enable HDCP two special point check\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
-\r
- //wen HDCP CTS\r
- if (!anx7150_bksv_srm(client))\r
- {\r
- anx7150_blue_screen_enable(client);\r
- anx7150_clear_avmute(client);\r
- Bksv_valid=0;\r
- return;\r
- }\r
- else //SY.\r
- {\r
- Bksv_valid=1;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= 0x03;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
-\r
- ANX7150_hdcp_init_done = 1;\r
-//wen HDCP CTS\r
- }\r
-\r
-\r
-//wen HDCP CTS\r
- if ((Bksv_valid) && (!ANX7150_hdcp_auth_en))\r
- {\r
- hdmi_dbg(&client->dev, "enable hw hdcp\n");\r
- anx7150_rst_ddcchannel(client);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 1;\r
- }\r
-\r
- if ((Bksv_valid) && (ANX7150_hdcp_wait_100ms_needed))\r
- {\r
- ANX7150_hdcp_wait_100ms_needed = 0;\r
- //disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- \r
- hdmi_dbg(&client->dev, "++++++++ANX7150_hdcp_wait_100ms_needed+++++++++\n");\r
- msleep(150); // 100 -> 150\r
- return;\r
- }\r
-//wen HDCP CTS\r
-\r
- if (ANX7150_hdcp_auth_pass) //wen HDCP CTS\r
- {\r
- //Clear the SRM_Check_Pass u8, then when reauthentication occurs, firmware can catch it.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= 0xfc;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
-\r
- //Enable HDCP Hardware encryption\r
- if (!ANX7150_hdcp_encryption)\r
- {\r
- anx7150_hdcp_encryption_enable(client);\r
- }\r
- if (ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_disable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
-\r
- i = 0;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- while((c&0x04)==0x00)//wait for encryption.\r
- {\r
- msleep(2);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- i++;\r
- if (i > 10)\r
- break;\r
- }\r
-\r
- //enable audio SY.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- hdmi_dbg(&client->dev, "@@@@@ HDCP Auth PASSED! @@@@@\n");\r
-\r
- if (ANX7150_hdcp_bcaps & 0x40) //repeater\r
- {\r
- hdmi_dbg(&client->dev, "Find a repeater!\n");\r
- //actually it is KSVList check. we can't do SRM check due to the lack of SRM file. SY.\r
- if (!ANX7150_srm_checked)\r
- {\r
- if (!anx7150_is_ksvlist_vld(client))\r
- {\r
- hdmi_dbg(&client->dev, "ksvlist not good. disable encryption");\r
- anx7150_hdcp_encryption_disable(client);\r
- anx7150_blue_screen_enable(client);\r
- anx7150_clear_avmute(client);\r
- ANX7150_ksv_srm_pass = 0;\r
- anx7150_clean_hdcp(client);//SY.\r
- //remove below will pass 1b-05/1b-06\r
- //ANX7150_Set_System_State(ANX7150_WAIT_HOTPLUG);//SY.\r
- return;\r
- }\r
- ANX7150_srm_checked=1;\r
- ANX7150_ksv_srm_pass = 1;\r
- }\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "Find a receiver.\n");\r
- }\r
- }\r
- else //wen HDCP CTS\r
- {\r
- hdmi_dbg(&client->dev, "##### HDCP Auth FAILED! #####\n");\r
- //also need to disable HW AUTHEN\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= ~ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
- //ANX7150_hdcp_init_done = 0;\r
- //ANX7150_hdcp_wait_100ms_needed = 1; //wen, update 080703\r
-\r
- if (ANX7150_hdcp_encryption)\r
- {\r
- anx7150_hdcp_encryption_disable(client);\r
- }\r
- if (!ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_enable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- \r
- return;\r
- }\r
-\r
- }\r
- else //wen HDCP CTS\r
- {\r
- hdmi_dbg(&client->dev, "hdcp pin is off.\n");\r
- if (ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_disable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
- //enable audio SY.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
-//wen HDCP CTS\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c); //72:07.1 hdmi or dvi mode\r
- c = c & 0x02;\r
- if (c == 0x02)\r
- {\r
- hdmi_dbg(&client->dev, "end of ANX7150_HDCP_Process(): in HDMI mode.\n");\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "!end of ANX7150_HDCP_Process(): in DVI mode.\n");\r
- //To-Do: Config to DVI mode.\r
- }\r
-\r
- anx7150_show_video_parameter(client);\r
-}\r
-\r
-void HDMI_Set_Video_Format(u8 video_format) //CPU set the lowpower mode\r
-{ \r
- switch (video_format)\r
- {\r
- case HDMI_1280x720p_50Hz:\r
- g_video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- g_video_format = ANX7150_V1280x720p_60Hz;\r
- break;\r
- case HDMI_720x576p_50Hz:\r
- g_video_format = ANX7150_V720x576p_50Hz_4x3;\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- g_video_format = ANX7150_V1920x1080p_50Hz;\r
- break;\r
- default:\r
- g_video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- }\r
-// ANX7150_system_config_done = 0;\r
-}\r
-void HDMI_Set_Audio_Fs( u8 audio_fs) //ANX7150 call this to check lowpower\r
-{\r
- g_audio_format = audio_fs;\r
-// ANX7150_system_config_done = 0;\r
-}\r
-int ANX7150_PLAYBACK_Process(void)\r
-{\r
-// D("enter\n");\r
-\r
- if ((s_ANX7150_packet_config.packets_need_config != 0x00) && (ANX7150_edid_result.is_HDMI == 1))\r
- {\r
- return 1;\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-\r
+++ /dev/null
-#ifndef _ANX7150_HW_H\r
-#define _ANX7150_HW_H\r
-\r
-#include <linux/hdmi.h>\r
-extern u8 timer_slot,misc_reset_needed;\r
-extern u8 bist_switch_value_pc,switch_value;\r
-extern u8 switch_value_sw_backup,switch_value_pc_backup;\r
-extern u8 ANX7150_system_state;\r
-extern u8 ANX7150_srm_checked;\r
-extern u8 ANX7150_HDCP_enable;\r
-extern u8 ANX7150_INT_Done;\r
-extern u8 FREQ_MCLK;\r
-//extern u8 int_s1, int_s2, int_s3;\r
-extern u8 HDMI_Mode_Auto_Manual,HDMI_Lowpower_Mode;\r
-\r
-struct anx7150_interrupt_s{\r
- int hotplug_change;\r
- int video_format_change;\r
- int auth_done;\r
- int auth_state_change;\r
- int pll_lock_change;\r
- int rx_sense_change;\r
- int HDCP_link_change;\r
- int audio_clk_change;\r
- int audio_FIFO_overrun;\r
- int SPDIF_bi_phase_error;\r
- int SPDIF_error;\r
-};\r
-typedef struct\r
-{\r
- u8 is_HDMI;\r
- u8 ycbcr444_supported;\r
- u8 ycbcr422_supported;\r
- u8 supported_1080p_60Hz;\r
- u8 supported_1080p_50Hz;\r
- u8 supported_1080i_60Hz;\r
- u8 supported_1080i_50Hz;\r
- u8 supported_720p_60Hz;\r
- u8 supported_720p_50Hz;\r
- u8 supported_576p_50Hz;\r
- u8 supported_576i_50Hz;\r
- u8 supported_640x480p_60Hz;\r
- u8 supported_720x480p_60Hz;\r
- u8 supported_720x480i_60Hz;\r
- u8 AudioFormat[10];//MAX audio STD block is 10(0x1f / 3)\r
- u8 AudioChannel[10];\r
- u8 AudioFs[10];\r
- u8 AudioLength[10];\r
- u8 SpeakerFormat;u8 edid_errcode;}ANX7150_edid_result_4_system;\r
- extern ANX7150_edid_result_4_system ANX7150_edid_result;\r
-//#define ITU656\r
-//#ifdef ITU656\r
-struct ANX7150_video_timingtype{ //CEA-861C format\r
- u8 ANX7150_640x480p_60Hz[18];//format 1\r
- u8 ANX7150_720x480p_60Hz[18];//format 2 & 3\r
- u8 ANX7150_1280x720p_60Hz[18];//format 4\r
- u8 ANX7150_1920x1080i_60Hz[18];//format 5\r
- u8 ANX7150_720x480i_60Hz[18];//format 6 & 7\r
- u8 ANX7150_1920x1080p_60Hz[18];\r
- //u8 ANX7150_720x240p_60Hz[18];//format 8 & 9\r
- //u8 ANX7150_2880x480i_60Hz[18];//format 10 & 11\r
- //u8 ANX7150_2880x240p_60Hz[18];//format 12 & 13\r
- //u8 ANX7150_1440x480p_60Hz[18];//format 14 & 15\r
- //u8 ANX7150_1920x1080p_60Hz[18];//format 16\r
- u8 ANX7150_720x576p_50Hz[18];//format 17 & 18\r
- u8 ANX7150_1280x720p_50Hz[18];//format 19\r
- u8 ANX7150_1920x1080i_50Hz[18];//format 20*/\r
- u8 ANX7150_720x576i_50Hz[18];//format 21 & 22\r
- u8 ANX7150_1920x1080p_50Hz[18];\r
- /* u8 ANX7150_720x288p_50Hz[18];//formats 23 & 24\r
- u8 ANX7150_2880x576i_50Hz[18];//formats 25 & 26\r
- u8 ANX7150_2880x288p_50Hz[18];//formats 27 & 28\r
- u8 ANX7150_1440x576p_50Hz[18];//formats 29 & 30\r
- u8 ANX7150_1920x1080p_50Hz[18];//format 31\r
- u8 ANX7150_1920x1080p_24Hz[18];//format 32\r
- u8 ANX7150_1920x1080p_25Hz[18];//format 33\r
- u8 ANX7150_1920x1080p_30Hz[18];//format 34*/\r
-};\r
-//#endif\r
-// 8 type of packets are legal, It is possible to sent 6 types in the same time;\r
-// So select 6 types below at most;\r
-// avi_infoframe and audio_infoframe have fixxed address;\r
-// config other selected types of packet to the rest 4 address with no limits.\r
-typedef enum\r
-{\r
- ANX7150_avi_infoframe,\r
- ANX7150_audio_infoframe,\r
- /*ANX7150_spd_infoframe,\r
- ANX7150_mpeg_infoframe,\r
- ANX7150_acp_packet,\r
- ANX7150_isrc1_packet,\r
- ANX7150_isrc2_packet,\r
- ANX7150_vendor_infoframe,*/\r
-}packet_type;\r
-\r
-typedef struct\r
-{\r
- u8 type;\r
- u8 version;\r
- u8 length;\r
- u8 pb_u8[28];\r
-}infoframe_struct;\r
-\r
-typedef struct\r
-{\r
- u8 packets_need_config; //which infoframe packet is need updated\r
- infoframe_struct avi_info;\r
- infoframe_struct audio_info;\r
- /* for the funture use\r
- infoframe_struct spd_info;\r
- infoframe_struct mpeg_info;\r
- infoframe_struct acp_pkt;\r
- infoframe_struct isrc1_pkt;\r
- infoframe_struct isrc2_pkt;\r
- infoframe_struct vendor_info; */\r
-\r
-} config_packets;\r
-/*\r
- u8 i2s_format;\r
-\r
- u8(s) Name Type Default Description\r
- 7 EXT_VUCP R/W 0x0\r
- Enable indicator of VUCP u8s extraction from input\r
- I2S audio stream. 0 = disable; 1 = enable.\r
- 6:5 MCLK_PHS_CTRL R/W 0x0\r
- MCLK phase control for audio SPDIF input, which value\r
- is depended on the value of MCLK frequency set and not great than it.\r
- 4 Reserved\r
- 3 SHIFT_CTRL R/W 0x0\r
- WS to SD shift first u8. 0 = fist u8 shift (Philips Spec); 1 = no shift.\r
- 2 DIR_CTRL R/W 0x0\r
- SD data Indian (MSB or LSB first) control. 0 = MSB first; 1 = LSB first.\r
- 1 WS_POL R/W 0x0\r
- Word select left/right polarity select. 0 = left polarity\r
- when works select is low; 1 = left polarity when word select is high.\r
- 0 JUST_CTRL R/W 0x0\r
- SD Justification control. 1 = data is right justified;\r
- 0 = data is left justified.\r
-\r
-*/\r
-/*\r
- u8 audio_channel\r
-u8(s) Name Type Default Description\r
-5 AUD_SD3_IN R/W 0x0 Set I2S input channel #3 enable. 0 = disable; 1 = enable.\r
-4 AUD_SD2_IN R/W 0x0 Set I2S input channel #2 enable. 0 = disable; 1 = enable.\r
-3 AUD_SD1_IN R/W 0x0 Set I2S input channel #1 enable. 0 = disable; 1 = enable.\r
-2 AUD_SD0_IN R/W 0x0 Set I2S input channel #0 enable. 0 = disable; 1 = enable.\r
-\r
-\r
-*/\r
-/*\r
- u8 i2s_map0\r
-u8(s) Name Type Default Description\r
-7:6 FIFO3_SEL R/W 0x3 I2S Channel data stream select for audio FIFO 3. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-5:4 FIFO2_SEL R/W 0x2 I2S Channel data stream select for audio FIFO 2. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-3:2 FIFO1_SEL R/W 0x1 I2S Channel data stream select for audio FIFO 1. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-1:0 FIFO0_SEL R/W 0x0 I2S Channel data stream select for audio FIFO 0. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-\r
- u8 i2s_map1\r
-u8(s) Name Type Default Description\r
-7 SW3 R/W 0x0 Swap left/right channel on I2S channel 3. 1 = swap; 0 = no swap.\r
-6 SW2 R/W 0x0 Swap left/right channel on I2S channel 2. 1 = swap; 0 = no swap.\r
-5 SW1 R/W 0x0 Swap left/right channel on I2S channel 1. 1 = swap; 0 = no swap.\r
-4 SW0 R/W 0x0 Swap left/right channel on I2S channel 0. 1 = swap; 0 = no swap.\r
-3:1 IN_WORD_LEN R/W 0x5 Input I2S audio word length (corresponding to channel status u8s [35:33]). When IN_WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when IN_WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
-0 IN_WORD_MAX R/W 0x1 Input I2S audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
-*/\r
-/*\r
- u8 Channel_status1\r
-u8(s) Name Type Default Description\r
-7:6 MODE R/W 0x0 00 = PCM Audio\r
-5:3 PCM_MODE R/W 0x0 000 = 2 audio channels without pre-emphasis;\r
- 001 = 2 audio channels with 50/15 usec pre-emphasis\r
-2 SW_CPRGT R/W 0x0 0 = software for which copyright is asserted;\r
- 1 = software for which no copyright is asserted\r
-1 NON_PCM R/W 0x0 0 = audio sample word represents linear PCM samples;\r
- 1 = audio sample word used for other purposes.\r
-0 PROF_APP R/W 0x0 0 = consumer applications; 1 = professional applications.\r
-\r
- u8 Channel_status2\r
-u8(s) Name Type Default Description\r
-7:0 CAT_CODE R/W 0x0 Category code (corresponding to channel status u8s [15:8])\r
-\r
- u8 Channel_status3\r
-u8(s) Name Type Default Description\r
-7:4 CH_NUM R/W 0x0 Channel number (corresponding to channel status u8s [23:20])\r
-3:0 SOURCE_NUM R/W 0x0 Source number (corresponding to channel status u8s [19:16])\r
-\r
- u8 Channel_status4\r
-u8(s) Name Type Default Description\r
-7:6 CHNL_u81 R/W 0x0 corresponding to channels status u8s [31:30]\r
-5:4 CLK_ACCUR R/W 0x0 Clock accuracy (corresponding to channels status u8s [29:28]). These two u8s define the sampling frequency tolerance. The u8s are set in the transmitter.\r
-3:0 FS_FREQ R/W 0x0 Sampling clock frequency (corresponding to channel status u8s [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
-\r
- u8 Channel_status5\r
-u8(s) Name Type Default Description\r
-7:4 CHNL_u82 R/W 0x0 corresponding to channels status u8s [39:36]\r
-3:1 WORD_LENGTH R/W 0x5 Audio word length (corresponding to channel status u8s [35:33]). When WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
-0 WORD_MAX R/W 0x1 Audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
-\r
-*/\r
-typedef struct\r
-{\r
- u8 audio_channel;\r
- u8 i2s_format;\r
- u8 i2s_swap;\r
- u8 Channel_status1;\r
- u8 Channel_status2;\r
- u8 Channel_status3;\r
- u8 Channel_status4;\r
- u8 Channel_status5;\r
-} i2s_config_struct;\r
-/*\r
- u8 FS_FREQ;\r
-\r
- 7:4 FS_FREQ R 0x0\r
- Sampling clock frequency (corresponding to channel status u8s [27:24]).\r
- 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz;\r
- 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
-*/\r
-\r
-typedef struct\r
-{\r
- u8 one_u8_ctrl;\r
-\r
-} super_audio_config_struct;\r
-\r
-typedef struct\r
-{\r
- u8 audio_type; // audio type\r
- // #define ANX7150_i2s_input 0x01\r
- // #define ANX7150_spdif_input 0x02\r
- // #define ANX7150_super_audio_input 0x04\r
-\r
- u8 down_sample; // 0x72:0x50\r
- // 0x00: 00 no down sample\r
- // 0x20: 01 2 to 1 down sample\r
- // 0x60: 11 4 to 1 down sample\r
- // 0x40: 10 reserved\r
- u8 audio_layout;//audio layout;\r
- //0x00, 2-channel\r
- //0x80, 8-channel\r
-\r
- i2s_config_struct i2s_config;\r
- super_audio_config_struct super_audio_config;\r
-\r
-} audio_config_struct;\r
-\r
-/*added by gerard.zhu*/\r
-/*DDC type*/\r
-typedef enum {\r
- DDC_Hdcp,\r
- DDC_Edid,\r
-}ANX7150_DDC_Type;\r
-\r
-/*Read DDC status type*/\r
-typedef enum {\r
- report,\r
- Judge,\r
-}ANX7150_DDC_Status_Check_Type;\r
-\r
-/*Define DDC address struction*/\r
-typedef struct {\r
- u8 dev_addr;\r
- u8 sgmt_addr;\r
- u8 offset_addr;\r
-}ANX7150_DDC_Addr;\r
-\r
-/*DDC status u8*/\r
-#define DDC_Error_u8 0x07\r
-#define DDC_Occup_u8 0x06\r
-#define DDC_Fifo_Full_u8 0x05\r
-#define DDC_Fifo_Empt_u8 0x04\r
-#define DDC_No_Ack_u8 0x03\r
-#define DDC_Fifo_Rd_u8 0x02\r
-#define DDC_Fifo_Wr_u8 0x01\r
-#define DDC_Progress_u8 0x00\r
-\r
-#define YCbCr422 0x20\r
-#define null 0\r
-#define source_ratio 0x08\r
-\r
-/*DDC Command*/\r
-#define Abort_Current_Operation 0x00\r
-#define Sequential_u8_Read 0x01\r
-#define Sequential_u8_Write 0x02\r
-#define Implicit_Offset_Address_Read 0x3\r
-#define Enhanced_DDC_Sequenital_Read 0x04\r
-#define Clear_DDC_Fifo 0x05\r
-#define I2c_reset 0x06\r
-\r
-/*DDC result*/\r
-#define DDC_NO_Err 0x00\r
-#define DDC_Status_Err 0x01\r
-#define DDC_Data_Addr_Err 0x02\r
-#define DDC_Length_Err 0x03\r
-\r
-/*checksum result*/\r
-#define Edid_Checksum_No_Err 0x00\r
-#define Edid_Checksum_Err 0x01\r
-\r
-/*HDCP device base address*/\r
-#define HDCP_Dev_Addr 0x74\r
-\r
-/*HDCP Bksv offset*/\r
-#define HDCP_Bksv_Offset 0x00\r
-\r
-/*HDCP Bcaps offset*/\r
-#define HDCP_Bcaps_Offset 0x40\r
-\r
-/*HDCP Bstatus offset*/\r
-#define HDCP_Bstatus_offset 0x41\r
-\r
-/*HDCP KSV Fifo offset */\r
-#define HDCP_Ksv_Fifo_Offset 0x43\r
-\r
-/*HDCP bksv data nums*/\r
-#define Bksv_Data_Nums 5\r
-\r
-/*HDCP ksvs data number by defult*/\r
-#define ksvs_data_nums 50\r
-\r
-/*DDC Max u8s*/\r
-#define DDC_Max_Length 1024\r
-\r
-/*DDC fifo depth*/\r
-#define DDC_Fifo_Depth 16\r
-\r
-/*DDC read delay ms*/\r
-#define DDC_Read_Delay 3\r
-\r
-/*DDC Write delay ms*/\r
-#define DDC_Write_Delay 3\r
-/*end*/\r
-\r
-extern u8 ANX7150_parse_edid_done;\r
-extern u8 ANX7150_system_config_done;\r
-extern u8 ANX7150_video_format_config,ANX7150_video_timing_id;\r
-extern u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
-extern u8 ANX7150_ddr_edge;\r
-extern u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
-extern u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
-extern u8 ANX7150_pix_rpt_set_by_sys;\r
-extern u8 ANX7150_RGBorYCbCr;\r
-extern audio_config_struct s_ANX7150_audio_config;\r
-extern config_packets s_ANX7150_packet_config;\r
-\r
-//********************** BIST Enable***********************************\r
-\r
-\r
-#define ddr_falling_edge 1\r
-#define ddr_rising_edge 0\r
-\r
-#define input_pixel_clk_1x_repeatition 0x00\r
-#define input_pixel_clk_2x_repeatition 0x01\r
-#define input_pixel_clk_4x_repeatition 0x03\r
-\r
-//***********************Video Config***********************************\r
-#define ANX7150_RGB_YCrCb444_SepSync 0\r
-#define ANX7150_YCrCb422_SepSync 1\r
-#define ANX7150_YCrCb422_EmbSync 2\r
-#define ANX7150_YCMux422_SepSync_Mode1 3\r
-#define ANX7150_YCMux422_SepSync_Mode2 4\r
-#define ANX7150_YCMux422_EmbSync_Mode1 5\r
-#define ANX7150_YCMux422_EmbSync_Mode2 6\r
-#define ANX7150_RGB_YCrCb444_DDR_SepSync 7\r
-#define ANX7150_RGB_YCrCb444_DDR_EmbSync 8\r
-\r
-#define ANX7150_RGB_YCrCb444_SepSync_No_DE 9\r
-#define ANX7150_YCrCb422_SepSync_No_DE 10\r
-\r
-#define ANX7150_Progressive 0\r
-#define ANX7150_Interlace 0x08\r
-#define ANX7150_Neg_Hsync_pol 0x20\r
-#define ANX7150_Pos_Hsync_pol 0\r
-#define ANX7150_Neg_Vsync_pol 0x40\r
-#define ANX7150_Pos_Vsync_pol 0\r
-\r
-#define ANX7150_V640x480p_60Hz 1\r
-#define ANX7150_V720x480p_60Hz_4x3 2\r
-#define ANX7150_V720x480p_60Hz_16x9 3\r
-#define ANX7150_V1280x720p_60Hz 4\r
-#define ANX7150_V1280x720p_50Hz 19\r
-#define ANX7150_V1920x1080i_60Hz 5\r
-#define ANX7150_V1920x1080p_60Hz 16\r
-#define ANX7150_V1920x1080p_50Hz 31\r
-#define ANX7150_V1920x1080i_50Hz 20\r
-#define ANX7150_V720x480i_60Hz_4x3 6\r
-#define ANX7150_V720x480i_60Hz_16x9 7\r
-#define ANX7150_V720x576i_50Hz_4x3 21\r
-#define ANX7150_V720x576i_50Hz_16x9 22\r
-#define ANX7150_V720x576p_50Hz_4x3 17\r
-#define ANX7150_V720x576p_50Hz_16x9 18\r
-\r
-#define ANX7150_RGB 0x00\r
-#define ANX7150_YCbCr422 0x01\r
-#define ANX7150_YCbCr444 0x02\r
-#define ANX7150_CSC_BT709 1\r
-#define ANX7150_CSC_BT601 0\r
-\r
-#define ANX7150_EMBEDED_BLUE_SCREEN_ENABLE 1\r
-#define ANX7150_HDCP_FAIL_THRESHOLD 10\r
-\r
-#define ANX7150_avi_sel 0x01\r
-#define ANX7150_audio_sel 0x02\r
-#define ANX7150_spd_sel 0x04\r
-#define ANX7150_mpeg_sel 0x08\r
-#define ANX7150_acp_sel 0x10\r
-#define ANX7150_isrc1_sel 0x20\r
-#define ANX7150_isrc2_sel 0x40\r
-#define ANX7150_vendor_sel 0x80\r
-\r
-// audio type\r
-#define ANX7150_i2s_input 0x01\r
-#define ANX7150_spdif_input 0x02\r
-#define ANX7150_super_audio_input 0x04\r
-// freq_mclk\r
-#define ANX7150_mclk_128_Fs 0x00\r
-#define ANX7150_mclk_256_Fs 0x01\r
-#define ANX7150_mclk_384_Fs 0x02\r
-#define ANX7150_mclk_512_Fs 0x03\r
-// thresholds\r
-#define ANX7150_spdif_stable_th 0x03\r
-// fs -> N(ACR)\r
-#define ANX7150_N_32k 0x1000\r
-#define ANX7150_N_44k 0x1880\r
-#define ANX7150_N_88k 0x3100\r
-#define ANX7150_N_176k 0x6200\r
-#define ANX7150_N_48k 0x1800\r
-#define ANX7150_N_96k 0x3000\r
-#define ANX7150_N_192k 0x6000\r
-\r
-#define spdif_error_th 0x0a\r
-\r
-#define Hresolution_1920 1920\r
-#define Vresolution_540 540\r
-#define Vresolution_1080 1080\r
-#define Hresolution_1280 1280\r
-#define Vresolution_720 720\r
-#define Hresolution_640 640\r
-#define Vresolution_480 480\r
-#define Hresolution_720 720\r
-#define Vresolution_240 240\r
-#define Vresolution_576 576\r
-#define Vresolution_288 288\r
-#define Hz_50 50\r
-#define Hz_60 60\r
-#define Interlace_EDID 0\r
-#define Progressive_EDID 1\r
-#define ratio_16_9 1.777778\r
-#define ratio_4_3 1.333333\r
-\r
-#define ANX7150_EDID_BadHeader 0x01\r
-#define ANX7150_EDID_861B_not_supported 0x02\r
-#define ANX7150_EDID_CheckSum_ERR 0x03\r
-#define ANX7150_EDID_No_ExtBlock 0x04\r
-#define ANX7150_EDID_ExtBlock_NotFor_861B 0x05\r
-\r
-#define ANX7150_VND_IDL_REG 0x00\r
-#define ANX7150_VND_IDH_REG 0x01\r
-#define ANX7150_DEV_IDL_REG 0x02\r
-#define ANX7150_DEV_IDH_REG 0x03\r
-#define ANX7150_DEV_REV_REG 0x04\r
-\r
-#define ANX7150_SRST_REG 0x05\r
-#define ANX7150_TX_RST 0x40\r
-#define ANX7150_SRST_VIDCAP_RST 0x20 // u8 position\r
-#define ANX7150_SRST_AFIFO_RST 0x10 // u8 position\r
-#define ANX7150_SRST_HDCP_RST 0x08 // u8 position\r
-#define ANX7150_SRST_VID_FIFO_RST 0x04 // u8 position\r
-#define ANX7150_SRST_AUD_RST 0x02 // u8 position\r
-#define ANX7150_SRST_SW_RST 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_STATE_REG 0x06\r
-#define ANX7150_SYS_STATE_AUD_CLK_DET 0x20 // u8 position\r
-#define ANX7150_SYS_STATE_AVMUTE 0x10 // u8 position\r
-#define ANX7150_SYS_STATE_HP 0x08 // u8 position\r
-#define ANX7150_SYS_STATE_VSYNC 0x04 // u8 position\r
-#define ANX7150_SYS_STATE_CLK_DET 0x02 // u8 position\r
-#define ANX7150_SYS_STATE_RSV_DET 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL1_REG 0x07\r
-#define ANX7150_SYS_CTRL1_LINKMUTE_EN 0x80 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDCPHPD_RST 0x40 // u8 position\r
-#define ANX7150_SYS_CTRL1_PDINT_SEL 0x20 // u8 position\r
-#define ANX7150_SYS_CTRL1_DDC_FAST 0x10 // u8 position\r
-#define ANX7150_SYS_CTRL1_DDC_SWCTRL 0x08 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDCPMODE 0x04 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDMI 0x02 // u8 position\r
-#define ANX7150_SYS_CTRL1_PWDN_CTRL 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL2_REG 0x08\r
-#define ANX7150_SYS_CTRL2_DDC_RST 0x08 // u8 position\r
-#define ANX7150_SYS_CTRL2_TMDSBIST_RST 0x04 // u8 position\r
-#define ANX7150_SYS_CTRL2_MISC_RST 0x02 // u8 position\r
-#define ANX7150_SYS_CTRL2_HW_RST 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL3_REG 0x09\r
-#define ANX7150_SYS_CTRL3_I2C_PWON 0x02\r
-#define ANX7150_SYS_CTRL3_PWON_ALL 0x01\r
-\r
-#define ANX7150_SYS_CTRL4_REG 0x0b\r
-\r
-#define ANX7150_VID_STATUS_REG 0x10\r
-#define ANX7150_VID_STATUS_VID_STABLE 0x20 // u8 position\r
-#define ANX7150_VID_STATUS_EMSYNC_ERR 0x10 // u8 position\r
-#define ANX7150_VID_STATUS_FLD_POL 0x08 // u8 position\r
-#define ANX7150_VID_STATUS_TYPE 0x04 // u8 position\r
-#define ANX7150_VID_STATUS_VSYNC_POL 0x02 // u8 position\r
-#define ANX7150_VID_STATUS_HSYNC_POL 0x01 // u8 position\r
-\r
-#define ANX7150_VID_MODE_REG 0x11\r
-#define ANX7150_VID_MODE_CHKSHARED_EN 0x80 // u8 position\r
-#define ANX7150_VID_MODE_LINKVID_EN 0x40 // u8 position\r
-#define ANX7150_VID_MODE_RANGE_Y2R 0x20 // u8 position\r
-#define ANX7150_VID_MODE_CSPACE_Y2R 0x10 // u8 position\r
-#define ANX7150_VID_MODE_Y2R_SEL 0x08 // u8 position\r
-#define ANX7150_VID_MODE_UPSAMPLE 0x04 // u8 position\r
-\r
-#define ANX7150_VID_CTRL_REG 0x12\r
-#define ANX7150_VID_CTRL_IN_EN 0x10 // u8 position\r
-#define ANX7150_VID_CTRL_YCu8_SEL 0x08 // u8 position\r
-#define ANX7150_VID_CTRL_u8CTRL_EN 0x04 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL0_REG 0x13\r
-#define ANX7150_VID_CAPCTRL0_DEGEN_EN 0x80 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_EMSYNC_EN 0x40 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DEMUX_EN 0x20 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_INV_IDCK 0x10 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DV_BUSMODE 0x08 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DDR_EDGE 0x04 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_VIDu8_SWAP 0x02 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_VIDBIST_EN 0x01 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL1_REG 0x14\r
-#define ANX7150_VID_CAPCTRL1_FORMAT_SEL 0x80 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_VSYNC_POL 0x40 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_HSYNC_POL 0x20 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_INV_FLDPOL 0x10 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_VID_TYPE 0x08 // u8 position\r
-\r
-#define ANX7150_H_RESL_REG 0x15\r
-#define ANX7150_H_RESH_REG 0x16\r
-#define ANX7150_VID_PIXL_REG 0x17\r
-#define ANX7150_VID_PIXH_REG 0x18\r
-#define ANX7150_H_FRONTPORCHL_REG 0x19\r
-#define ANX7150_H_FRONTPORCHH_REG 0x1A\r
-#define ANX7150_HSYNC_ACT_WIDTHL_REG 0x1B\r
-#define ANX7150_HSYNC_ACT_WIDTHH_REG 0x1C\r
-#define ANX7150_H_BACKPORCHL_REG 0x1D\r
-#define ANX7150_H_BACKPORCHH_REG 0x1E\r
-#define ANX7150_V_RESL_REG 0x1F\r
-#define ANX7150_V_RESH_REG 0x20\r
-#define ANX7150_ACT_LINEL_REG 0x21\r
-#define ANX7150_ACT_LINEH_REG 0x22\r
-#define ANX7150_ACT_LINE2VSYNC_REG 0x23\r
-#define ANX7150_VSYNC_WID_REG 0x24\r
-#define ANX7150_VSYNC_TAIL2VIDLINE_REG 0x25\r
-#define ANX7150_VIDF_HRESL_REG 0x26\r
-#define ANX7150_VIDF_HRESH_REG 0x27\r
-#define ANX7150_VIDF_PIXL_REG 0x28\r
-#define ANX7150_VIDF_PIXH_REG 0x29\r
-#define ANX7150_VIDF_HFORNTPORCHL_REG 0x2A\r
-#define ANX7150_VIDF_HFORNTPORCHH_REG 0x2B\r
-#define ANX7150_VIDF_HSYNCWIDL_REG 0x2C\r
-#define ANX7150_VIDF_HSYNCWIDH_REG 0x2D\r
-#define ANX7150_VIDF_HBACKPORCHL_REG 0x2E\r
-#define ANX7150_VIDF_HBACKPORCHH_REG 0x2F\r
-#define ANX7150_VIDF_VRESL_REG 0x30\r
-#define ANX7150_VIDF_VRESH_REG 0x31\r
-#define ANX7150_VIDF_ACTVIDLINEL_REG 0x32\r
-#define ANX7150_VIDF_ACTVIDLINEH_REG 0x33\r
-#define ANX7150_VIDF_ACTLINE2VSYNC_REG 0x34\r
-#define ANX7150_VIDF_VSYNCWIDLINE_REG 0x35\r
-#define ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG 0x36\r
-\r
-//Video input data u8 control registers\r
-\r
-#define VID_u8_CTRL0 0x37 //added\r
-#define VID_u8_CTRL1 0x38\r
-#define VID_u8_CTRL2 0x39\r
-#define VID_u8_CTRL3 0x3A\r
-#define VID_u8_CTRL4 0x3B\r
-#define VID_u8_CTRL5 0x3C\r
-#define VID_u8_CTRL6 0x3D\r
-#define VID_u8_CTRL7 0x3E\r
-#define VID_u8_CTRL8 0x3F\r
-#define VID_u8_CTRL9 0x48\r
-#define VID_u8_CTRL10 0x49\r
-#define VID_u8_CTRL11 0x4A\r
-#define VID_u8_CTRL12 0x4B\r
-#define VID_u8_CTRL13 0x4C\r
-#define VID_u8_CTRL14 0x4D\r
-#define VID_u8_CTRL15 0x4E\r
-#define VID_u8_CTRL16 0x4F\r
-#define VID_u8_CTRL17 0x89\r
-#define VID_u8_CTRL18 0x8A\r
-#define VID_u8_CTRL19 0x8B\r
-#define VID_u8_CTRL20 0x8C\r
-#define VID_u8_CTRL21 0x8D\r
-#define VID_u8_CTRL22 0x8E\r
-#define VID_u8_CTRL23 0x8F\r
-\r
-\r
-#define ANX7150_INTR_STATE_REG 0x40\r
-\r
-#define ANX7150_INTR_CTRL_REG 0x41\r
-\r
-#define ANX7150_INTR_CTRL_SOFT_INTR 0x04 // u8 position\r
-#define ANX7150_INTR_CTRL_TYPE 0x02 // u8 position\r
-#define ANX7150_INTR_CTRL_POL 0x01 // u8 position\r
-\r
-#define ANX7150_INTR1_STATUS_REG 0x42\r
-#define ANX7150_INTR1_STATUS_CTS_CHG 0x80 // u8 position\r
-#define ANX7150_INTR1_STATUS_AFIFO_UNDER 0x40 // u8 position\r
-#define ANX7150_INTR1_STATUS_AFIFO_OVER 0x20 // u8 position\r
-#define ANX7150_INTR1_STATUS_SPDIF_ERR 0x10 // u8 position\r
-#define ANX7150_INTR1_STATUS_SW_INT 0x08 // u8 position\r
-#define ANX7150_INTR1_STATUS_HP_CHG 0x04 // u8 position\r
-#define ANX7150_INTR1_STATUS_CTS_OVRWR 0x02 // u8 position\r
-#define ANX7150_INTR1_STATUS_CLK_CHG 0x01 // u8 position\r
-\r
-#define ANX7150_INTR2_STATUS_REG 0x43\r
-#define ANX7150_INTR2_STATUS_ENCEN_CHG 0x80 // u8 position\r
-#define ANX7150_INTR2_STATUS_HDCPLINK_CHK 0x40 // u8 position\r
-#define ANX7150_INTR2_STATUS_HDCPENHC_CHK 0x20 // u8 position\r
-#define ANX7150_INTR2_STATUS_BKSV_RDY 0x10 // u8 position\r
-#define ANX7150_INTR2_STATUS_PLLLOCK_CHG 0x08 // u8 position\r
-#define ANX7150_INTR2_STATUS_SHA_DONE 0x04 // u8 position\r
-#define ANX7150_INTR2_STATUS_AUTH_CHG 0x02 // u8 position\r
-#define ANX7150_INTR2_STATUS_AUTH_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_INTR3_STATUS_REG 0x44\r
-#define ANX7150_INTR3_STATUS_SPDIFBI_ERR 0x80 // u8 position\r
-#define ANX7150_INTR3_STATUS_VIDF_CHG 0x40 // u8 position\r
-#define ANX7150_INTR3_STATUS_AUDCLK_CHG 0x20 // u8 position\r
-#define ANX7150_INTR3_STATUS_DDCACC_ERR 0x10 // u8 position\r
-#define ANX7150_INTR3_STATUS_DDC_NOACK 0x08 // u8 position\r
-#define ANX7150_INTR3_STATUS_VSYNC_DET 0x04 // u8 position\r
-#define ANX7150_INTR3_STATUS_RXSEN_CHG 0x02 // u8 position\r
-#define ANX7150_INTR3_STATUS_SPDIF_UNSTBL 0x01 // u8 position\r
-\r
-#define ANX7150_INTR1_MASK_REG 0x45\r
-#define ANX7150_INTR2_MASK_REG 0x46\r
-#define ANX7150_INTR3_MASK_REG 0x47\r
-\r
-#define ANX7150_HDMI_AUDCTRL0_REG 0x50\r
-#define ANX7150_HDMI_AUDCTRL0_LAYOUT 0x80 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_DOWN_SMPL 0x60 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_CTSGEN_SC 0x10 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_INV_AUDCLK 0x08 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDCTRL1_REG 0x51\r
-#define ANX7150_HDMI_AUDCTRL1_IN_EN 0x80 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN 0x40 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD3IN_EN 0x20 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD2IN_EN 0x10 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD1IN_EN 0x08 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD0IN_EN 0x04 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SPDIFFS_OVRWR 0x02 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_CLK_SEL 0x01 // u8 position\r
-\r
-#define ANX7150_I2S_CTRL_REG 0x52\r
-#define ANX7150_I2S_CTRL_VUCP 0x80 // u8 position\r
-#define SPDIF_IN_SEL 0x10 //0-spdif, 1-multi with sd0\r
-#define ANX7150_I2S_CTRL_SHIFT_CTRL 0x08 // u8 position\r
-#define ANX7150_I2S_CTRL_DIR_CTRL 0x04 // u8 position\r
-#define ANX7150_I2S_CTRL_WS_POL 0x02 // u8 position\r
-#define ANX7150_I2S_CTRL_JUST_CTRL 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_CTRL_REG 0x53\r
-#define ANX7150_I2SCH_FIFO3_SEL 0xC0 // u8 position\r
-#define ANX7150_I2SCH_FIFO2_SEL 0x30 // u8 position\r
-#define ANX7150_I2SCH_FIFO1_SEL 0x0C // u8 position\r
-#define ANX7150_I2SCH_FIFO0_SEL 0x03 // u8 position\r
-\r
-#define ANX7150_I2SCH_SWCTRL_REG 0x54\r
-\r
-#define ANX7150_I2SCH_SWCTRL_SW3 0x80 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW2 0x40 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW1 0x20 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW0 0x10 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_INWD_LEN 0xE0 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_INWD_MAX 0x01 // u8 position\r
-\r
-#define ANX7150_SPDIFCH_STATUS_REG 0x55\r
-#define ANX7150_SPDIFCH_STATUS_FS_FREG 0xF0 // u8 position\r
-#define ANX7150_SPDIFCH_STATUS_WD_LEN 0x0E // u8 position\r
-#define ANX7150_SPDIFCH_STATUS_WD_MX 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_STATUS1_REG 0x56\r
-#define ANX7150_I2SCH_STATUS1_MODE 0xC0 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_PCM_MODE 0x38 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_SW_CPRGT 0x04 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_NON_PCM 0x02 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_PROF_APP 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_STATUS2_REG 0x57\r
-\r
-#define ANX7150_I2SCH_STATUS3_REG 0x58\r
-#define ANX7150_I2SCH_STATUS3_CH_NUM 0xF0 // u8 position\r
-#define ANX7150_I2SCH_STATUS3_SRC_NUM 0x0F // u8 position\r
-\r
-\r
-\r
-#define ANX7150_I2SCH_STATUS4_REG 0x59\r
-\r
-#define ANX7150_I2SCH_STATUS5_REG 0x5A\r
-\r
-#define ANX7150_I2SCH_STATUS5_WORD_MAX 0x01 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDSTATUS_REG 0x5B\r
-\r
-#define ANX7150_HDMI_AUDSTATUS_SPDIF_DET 0x01 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDBIST_CTRL_REG 0x5C\r
-\r
-#define ANX7150_HDMI_AUDBIST_EN3 0x08 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN2 0x04 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN1 0x02 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN0 0x01 // u8 position\r
-\r
-#define ANX7150_AUD_INCLK_CNT_REG 0x5D\r
-#define ANX7150_AUD_DEBUG_STATUS_REG 0x5E\r
-\r
-#define ANX7150_ONEu8_AUD_CTRL_REG 0x60\r
-\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN7 0x80 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN6 0x40 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN5 0x20 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN4 0x10 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN3 0x08 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN2 0x04 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN1 0x02 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN0 0x01 // u8 position\r
-\r
-#define ANX7150_ONEu8_AUD0_CTRL_REG 0x61\r
-#define ANX7150_ONEu8_AUD1_CTRL_REG 0x62\r
-#define ANX7150_ONEu8_AUD2_CTRL_REG 0x63\r
-#define ANX7150_ONEu8_AUD3_CTRL_REG 0x64\r
-\r
-#define ANX7150_ONEu8_AUDCLK_CTRL_REG 0x65\r
-\r
-#define ANX7150_ONEu8_AUDCLK_DET 0x08 // u8 position\r
-\r
-#define ANX7150_SPDIF_ERR_THRSHLD_REG 0x66\r
-#define ANX7150_SPDIF_ERR_CNT_REG 0x67\r
-\r
-#define ANX7150_HDMI_LINK_CTRL_REG 0x70\r
-\r
-#define ANX7150_HDMI_LINK_DATA_MUTEEN1 0x80 // u8 position\r
-#define ANX7150_HDMI_LINK_DATA_MUTEEN0 0x40 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN2 0x20 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN1 0x10 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN0 0x08 // u8 position\r
-#define ANX7150_HDMI_LINK_DEC_DE 0x04 // u8 position\r
-#define ANX7150_HDMI_LINK_PRMB_INC 0x02 // u8 position\r
-#define ANX7150_HDMI_LINK_AUTO_PROG 0x01 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL2_REG 0x71\r
-\r
-#define ANX7150_VID_CAPCTRL2_CHK_UPDATEEN 0x10 // u8 position\r
-\r
-#define ANX7150_LINK_MUTEEE_REG 0x72\r
-\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN2 0x20 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN1 0x10 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN0 0x08 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN2 0x04 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN1 0x02 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN0 0x01 // u8 position\r
-\r
-#define ANX7150_SERDES_TEST0_REG 0x73\r
-#define ANX7150_SERDES_TEST1_REG 0x74\r
-#define ANX7150_SERDES_TEST2_REG 0x75\r
-\r
-#define ANX7150_PLL_TX_AMP 0x76\r
-\r
-\r
-#define ANX7150_DDC_SLV_ADDR_REG 0x80\r
-#define ANX7150_DDC_SLV_SEGADDR_REG 0x81\r
-#define ANX7150_DDC_SLV_OFFADDR_REG 0x82\r
-#define ANX7150_DDC_ACC_CMD_REG 0x83\r
-#define ANX7150_DDC_ACCNUM0_REG 0x84\r
-#define ANX7150_DDC_ACCNUM1_REG 0x85\r
-\r
-#define ANX7150_DDC_CHSTATUS_REG 0x86\r
-\r
-#define ANX7150_DDC_CHSTATUS_DDCERR 0x80 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_DDC_OCCUPY 0x40 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_FULL 0x20 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_EMPT 0x10 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_NOACK 0x08 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_RD 0x04 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_WR 0x02 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_INPRO 0x01 // u8 position\r
-\r
-#define ANX7150_DDC_FIFO_ACC_REG 0x87\r
-#define ANX7150_DDC_FIFOCNT_REG 0x88\r
-\r
-#define ANX7150_SYS_PD_REG 0x90\r
-#define ANX7150_SYS_PD_PLL 0x80 // u8 position\r
-#define ANX7150_SYS_PD_TMDS 0x40 // u8 position\r
-#define ANX7150_SYS_PD_TMDS_CLK 0x20 // u8 position\r
-#define ANX7150_SYS_PD_MISC 0x10 // u8 position\r
-#define ANX7150_SYS_PD_LINK 0x08 // u8 position\r
-#define ANX7150_SYS_PD_IDCK 0x04 // u8 position\r
-#define ANX7150_SYS_PD_AUD 0x02 // u8 position\r
-#define ANX7150_SYS_PD_MACRO_ALL 0x01 // u8 position\r
-\r
-#define ANX7150_LINKFSM_DEBUG0_REG 0x91\r
-#define ANX7150_LINKFSM_DEBUG1_REG 0x92\r
-\r
-#define ANX7150_PLL_CTRL0_REG 0x93\r
-#define ANX7150_PLL_CTRL0_CPREG_BLEED 0x02 // u8 position\r
-#define ANX7150_PLL_CTRL0_TEST_EN 0x01 // u8 position\r
-\r
-#define ANX7150_PLL_CTRL1_REG 0x94\r
-#define ANX7150_PLL_CTRL1_TESTEN 0x80 // u8 position\r
-\r
-#define ANX7150_OSC_CTRL_REG 0x95\r
-#define ANX7150_OSC_CTRL_TESTEN 0x80 // u8 position\r
-#define ANX7150_OSC_CTRL_SEL_BG 0x40 // u8 position\r
-\r
-#define ANX7150_TMDS_CH0_CONFIG_REG 0x96\r
-#define ANX7150_TMDS_CH0_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH0_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CHO_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CH1_CONFIG_REG 0x97\r
-#define ANX7150_TMDS_CH1_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH1_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CH1_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CH2_CONFIG_REG 0x98\r
-#define ANX7150_TMDS_CH2_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH2_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CH2_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CLKCH_CONFIG_REG 0x99\r
-#define ANX7150_TMDS_CLKCH_MUTE 0x80 // u8 position\r
-#define ANX7150_TMDS_CLKCH_TESTEN 0x08 // u8 position\r
-#define ANX7150_TMDS_CLKCH_AMP 0x07 // u8 position\r
-\r
-#define ANX7150_CHIP_CTRL_REG 0x9A\r
-#define ANX7150_CHIP_CTRL_PRBS_GENEN 0x80 // u8 position\r
-#define ANX7150_CHIP_CTRL_LINK_DBGSEL 0x70 // u8 position\r
-#define ANX7150_CHIP_CTRL_VIDCHK_EN 0x08 // u8 position\r
-#define ANX7150_CHIP_CTRL_MISC_TIMER 0x04 // u8 position\r
-#define ANX7150_CHIP_CTRL_PLL_RNG 0x02 // u8 position\r
-#define ANX7150_CHIP_CTRL_PLL_MAN 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_STATUS_REG 0x9B\r
-#define ANX7150_CHIP_STATUS_GPIO 0x80 // u8 position\r
-#define ANX7150_CHIP_STATUS_SDA 0x40 // u8 position\r
-#define ANX7150_CHIP_STATUS_SCL 0x20 // u8 position\r
-#define ANX7150_CHIP_STATUS_PLL_HSPO 0x04 // u8 position\r
-#define ANX7150_CHIP_STATUS_PLL_LOCK 0x02 // u8 position\r
-#define ANX7150_CHIP_STATUS_MISC_LOCK 0x01 // u8 position\r
-\r
-#define ANX7150_DBG_PINGPIO_CTRL_REG 0x9C\r
-#define ANX7150_DBG_PINGPIO_VDLOW_SHAREDEN 0x04 // u8 position\r
-#define ANX7150_DBG_PINGPIO_GPIO_ADDREN 0x02 // u8 position\r
-#define ANX7150_DBG_PINGPIO_GPIO_OUT 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG0_CTRL_REG 0x9D\r
-#define ANX7150_CHIP_DEBUG0_PRBS_ERR 0xE0 // u8 position\r
-#define ANX7150_CHIP_DEBUG0_CAPST 0x1F // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG1_CTRL_REG 0x9E\r
-#define ANX7150_CHIP_DEBUG1_SDA_SW 0x80 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_SCL_SW 0x40 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_SERDES_TESTEN 0x20 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_CLK_BYPASS 0x10 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_FORCE_PLLLOCK 0x08 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_PLLLOCK_BYPASS 0x04 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_FORCE_HP 0x02 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_HP_DEGLITCH 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG2_CTRL_REG 0x9F\r
-#define ANX7150_CHIP_DEBUG2_EXEMB_SYNCEN 0x04 // u8 position\r
-#define ANX7150_CHIP_DEBUG2_VIDBIST 0x02 // u8 position\r
-\r
-#define ANX7150_VID_INCLK_REG 0x5F\r
-\r
-#define ANX7150_HDCP_STATUS_REG 0xA0\r
-#define ANX7150_HDCP_STATUS_ADV_CIPHER 0x80 // u8 position\r
-#define ANX7150_HDCP_STATUS_R0_READY 0x10 // u8 position\r
-#define ANX7150_HDCP_STATUS_AKSV_ACT 0x08 // u8 position\r
-#define ANX7150_HDCP_STATUS_ENCRYPT 0x04 // u8 position\r
-#define ANX7150_HDCP_STATUS_AUTH_PASS 0x02 // u8 position\r
-#define ANX7150_HDCP_STATUS_KEY_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_CTRL0_REG 0xA1\r
-#define ANX7150_HDCP_CTRL0_STORE_AN 0x80 // u8 position\r
-#define ANX7150_HDCP_CTRL0_RX_REP 0x40 // u8 position\r
-#define ANX7150_HDCP_CTRL0_RE_AUTH 0x20 // u8 position\r
-#define ANX7150_HDCP_CTRL0_SW_AUTHOK 0x10 // u8 position\r
-#define ANX7150_HDCP_CTRL0_HW_AUTHEN 0x08 // u8 position\r
-#define ANX7150_HDCP_CTRL0_ENC_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_CTRL0_BKSV_SRM 0x02 // u8 position\r
-#define ANX7150_HDCP_CTRL0_KSV_VLD 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_CTRL1_REG 0xA2\r
-#define ANX7150_LINK_CHK_12_EN 0x40\r
-#define ANX7150_HDCP_CTRL1_DDC_NOSTOP 0x20 // u8 position\r
-#define ANX7150_HDCP_CTRL1_DDC_NOACK 0x10 // u8 position\r
-#define ANX7150_HDCP_CTRL1_EDDC_NOACK 0x08 // u8 position\r
-#define ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_CTRL1_RCV11_EN 0x02 // u8 position\r
-#define ANX7150_HDCP_CTRL1_HDCP11_EN 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_Link_Check_FRAME_NUM_REG 0xA3\r
-#define ANX7150_HDCP_AKSV1_REG 0xA5\r
-#define ANX7150_HDCP_AKSV2_REG 0xA6\r
-#define ANX7150_HDCP_AKSV3_REG 0xA7\r
-#define ANX7150_HDCP_AKSV4_REG 0xA8\r
-#define ANX7150_HDCP_AKSV5_REG 0xA9\r
-\r
-#define ANX7150_HDCP_AN1_REG 0xAA\r
-#define ANX7150_HDCP_AN2_REG 0xAB\r
-#define ANX7150_HDCP_AN3_REG 0xAC\r
-#define ANX7150_HDCP_AN4_REG 0xAD\r
-#define ANX7150_HDCP_AN5_REG 0xAE\r
-#define ANX7150_HDCP_AN6_REG 0xAF\r
-#define ANX7150_HDCP_AN7_REG 0xB0\r
-#define ANX7150_HDCP_AN8_REG 0xB1\r
-\r
-#define ANX7150_HDCP_BKSV1_REG 0xB2\r
-#define ANX7150_HDCP_BKSV2_REG 0xB3\r
-#define ANX7150_HDCP_BKSV3_REG 0xB4\r
-#define ANX7150_HDCP_BKSV4_REG 0xB5\r
-#define ANX7150_HDCP_BKSV5_REG 0xB6\r
-\r
-#define ANX7150_HDCP_RI1_REG 0xB7\r
-#define ANX7150_HDCP_RI2_REG 0xB8\r
-\r
-#define ANX7150_HDCP_PJ_REG 0xB9\r
-#define ANX7150_HDCP_RX_CAPS_REG 0xBA\r
-#define ANX7150_HDCP_BSTATUS0_REG 0xBB\r
-#define ANX7150_HDCP_BSTATUS1_REG 0xBC\r
-\r
-#define ANX7150_HDCP_AMO0_REG 0xD0\r
-#define ANX7150_HDCP_AMO1_REG 0xD1\r
-#define ANX7150_HDCP_AMO2_REG 0xD2\r
-#define ANX7150_HDCP_AMO3_REG 0xD3\r
-#define ANX7150_HDCP_AMO4_REG 0xD4\r
-#define ANX7150_HDCP_AMO5_REG 0xD5\r
-#define ANX7150_HDCP_AMO6_REG 0xD6\r
-#define ANX7150_HDCP_AMO7_REG 0xD7\r
-\r
-#define ANX7150_HDCP_DBG_CTRL_REG 0xBD\r
-\r
-#define ANX7150_HDCP_DBG_ENC_INC 0x08 // u8 position\r
-#define ANX7150_HDCP_DBG_DDC_SPEED 0x06 // u8 position\r
-#define ANX7150_HDCP_DBG_SKIP_RPT 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_KEY_STATUS_REG 0xBE\r
-#define ANX7150_HDCP_KEY_BIST_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_KEY_BIST_ERR 0x02 // u8 position\r
-#define ANX7150_HDCP_KEY_CMD_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_KEY_CMD_REGISTER 0xBF //added\r
-\r
-#define ANX7150_HDCP_AUTHDBG_STATUS_REG 0xC7\r
-#define ANX7150_HDCP_ENCRYPTDBG_STATUS_REG 0xC8\r
-#define ANX7150_HDCP_FRAME_NUM_REG 0xC9\r
-\r
-#define ANX7150_DDC_MSTR_INTER_REG 0xCA\r
-#define ANX7150_DDC_MSTR_LINK_REG 0xCB\r
-\r
-#define ANX7150_HDCP_BLUESCREEN0_REG 0xCC\r
-#define ANX7150_HDCP_BLUESCREEN1_REG 0xCD\r
-#define ANX7150_HDCP_BLUESCREEN2_REG 0xCE\r
-// DEV_ADDR = 0x7A or 0x7E\r
-#define ANX7150_INFO_PKTCTRL1_REG 0xC0\r
-#define ANX7150_INFO_PKTCTRL1_SPD_RPT 0x80 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_SPD_EN 0x40 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_AVI_RPT 0x20 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_AVI_EN 0x10 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_GCP_RPT 0x08 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_GCP_EN 0x04 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_ACR_NEW 0x02 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_ACR_EN 0x01 // u8 position\r
-\r
-#define ANX7150_INFO_PKTCTRL2_REG 0xC1\r
-#define ANX7150_INFO_PKTCTRL2_UD1_RPT 0x80 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD1_EN 0x40 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD0_RPT 0x20 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD0_EN 0x10 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_MPEG_RPT 0x08 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_MPEG_EN 0x04 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_AIF_RPT 0x02 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_AIF_EN 0x01 // u8 position\r
-\r
-#define ANX7150_ACR_N1_SW_REG 0xC2\r
-#define ANX7150_ACR_N2_SW_REG 0xC3\r
-#define ANX7150_ACR_N3_SW_REG 0xC4\r
-\r
-#define ANX7150_ACR_CTS1_SW_REG 0xC5\r
-#define ANX7150_ACR_CTS2_SW_REG 0xC6\r
-#define ANX7150_ACR_CTS3_SW_REG 0xC7\r
-\r
-#define ANX7150_ACR_CTS1_HW_REG 0xC8\r
-#define ANX7150_ACR_CTS2_HW_REG 0xC9\r
-#define ANX7150_ACR_CTS3_HW_REG 0xCA\r
-\r
-#define ANX7150_ACR_CTS_CTRL_REG 0xCB\r
-\r
-#define ANX7150_GNRL_CTRL_PKT_REG 0xCC\r
-#define ANX7150_GNRL_CTRL_CLR_AVMUTE 0x02 // u8 position\r
-#define ANX7150_GNRL_CTRL_SET_AVMUTE 0x01 // u8 position\r
-\r
-#define ANX7150_AUD_PKT_FLATCTRL_REG 0xCD\r
-#define ANX7150_AUD_PKT_AUTOFLAT_EN 0x80 // u8 position\r
-#define ANX7150_AUD_PKT_FLAT 0x07 // u8 position\r
-\r
-\r
-//select video hardware interface\r
-#define ANX7150_VID_HW_INTERFACE 0x03//0x00:RGB and YcbCr 4:4:4 Formats with Separate Syncs (24-bpp mode)\r
- //0x01:YCbCr 4:2:2 Formats with Separate Syncs(16-bbp)\r
- //0x02:YCbCr 4:2:2 Formats with Embedded Syncs(No HS/VS/DE)\r
- //0x03:YC Mux 4:2:2 Formats with Separate Sync Mode1(u815:8 and u8 3:0 are used)\r
- //0x04:YC Mux 4:2:2 Formats with Separate Sync Mode2(u811:0 are used)\r
- //0x05:YC Mux 4:2:2 Formats with Embedded Sync Mode1(u815:8 and u8 3:0 are used)\r
- //0x06:YC Mux 4:2:2 Formats with Embedded Sync Mode2(u811:0 are used)\r
- //0x07:RGB and YcbCr 4:4:4 DDR Formats with Separate Syncs\r
- //0x08:RGB and YcbCr 4:4:4 DDR Formats with Embedded Syncs\r
- //0x09:RGB and YcbCr 4:4:4 Formats with Separate Syncs but no DE\r
- //0x0a:YCbCr 4:2:2 Formats with Separate Syncs but no DE\r
-//select input color space\r
-#define ANX7150_INPUT_COLORSPACE 0x01//0x00: input color space is RGB\r
- //0x01: input color space is YCbCr422\r
- //0x02: input color space is YCbCr444\r
-//select input pixel clock edge for DDR mode\r
-#define ANX7150_IDCK_EDGE_DDR 0x00 //0x00:use rising edge to latch even numbered pixel data//jack wen\r
- //0x01:use falling edge to latch even numbered pixel data\r
-\r
-//select audio hardware interface\r
-#define ANX7150_AUD_HW_INTERFACE 0x01//0x01:audio input comes from I2S\r
- //0x02:audio input comes from SPDIF\r
- //0x04:audio input comes from one u8 audio\r
-//select MCLK and Fs relationship if audio HW interface is I2S\r
-#define ANX7150_MCLK_Fs_RELATION 0x01//0x00:MCLK = 128 * Fs\r
- //0x01:MCLK = 256 * Fs\r
- //0x02:MCLK = 384 * Fs\r
- //0x03:MCLK = 512 * Fs //wen updated error\r
-\r
-#define ANX7150_AUD_CLK_EDGE 0x00 //0x00:use MCLK and SCK rising edge to latch audio data\r
- //0x08, revised by wen. //0x80:use MCLK and SCK falling edge to latch audio data\r
-//select I2S channel numbers if audio HW interface is I2S\r
-#define ANX7150_I2S_CH0_ENABLE 0x01 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH1_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH2_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH3_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-//select I2S word length if audio HW interface is I2S\r
-#define ANX7150_I2S_WORD_LENGTH 0x0b\r
- //0x02 = 16u8s; 0x04 = 18 u8s; 0x08 = 19 u8s; 0x0a = 20 u8s(maximal word length is 20u8s); 0x0c = 17 u8s;\r
- // 0x03 = 20u8s(maximal word length is 24u8s); 0x05 = 22 u8s; 0x09 = 23 u8s; 0x0b = 24 u8s; 0x0d = 21 u8s;\r
-\r
-//select I2S format if audio HW interface is I2S\r
-#define ANX7150_I2S_SHIFT_CTRL 0x00//0x00: fist u8 shift(philips spec)\r
- //0x01:no shift\r
-#define ANX7150_I2S_DIR_CTRL 0x00//0x00:SD data MSB first\r
- //0x01:LSB first\r
-#define ANX7150_I2S_WS_POL 0x00//0x00:left polarity when word select is low\r
- //0x01:left polarity when word select is high\r
-#define ANX7150_I2S_JUST_CTRL 0x00//0x00:data is left justified\r
- //0x01:data is right justified\r
-\r
-#define EDID_Parse_Enable 1 // cwz 0 for test, 1 normal\r
-//InfoFrame and Control Packet Registers\r
-// 0x7A or 0X7E\r
-/*\r
-#define AVI_HB0 0x00\r
-#define AVI_HB1 0x01\r
-#define AVI_HB2 0x02\r
-#define AVI_PB0 0x03\r
-#define AVI_PB1 0x04\r
-#define AVI_PB2 0x05\r
-#define AVI_PB3 0x06\r
-#define AVI_PB4 0x07\r
-#define AVI_PB5 0x08\r
-#define AVI_PB6 0x09\r
-#define AVI_PB7 0x0A\r
-#define AVI_PB8 0x0B\r
-#define AVI_PB9 0x0C\r
-#define AVI_PB10 0x0D\r
-#define AVI_PB11 0x0E\r
-#define AVI_PB12 0x0F\r
-#define AVI_PB13 0x10\r
-#define AVI_PB14 0x11\r
-#define AVI_PB15 0x12\r
-\r
-#define AUD_HBO 0x20\r
-#define AUD_HB1 0x21\r
-#define AUD_HB2 0x22\r
-#define AUD_PB0 0x23\r
-#define AUD_PB1 0x24\r
-#define AUD_PB2 0x25\r
-#define AUD_PB3 0x26\r
-#define AUD_PB4 0x27\r
-#define AUD_PB5 0x28\r
-#define AUD_PB6 0x29\r
-#define AUD_PB7 0x2A\r
-#define AUD_PB8 0x2B\r
-#define AUD_PB9 0x2C\r
-#define AUD_PB10 0x2D\r
-\r
-#define SPD_HBO 0x40\r
-#define SPD_HB1 0x41\r
-#define SPD_HB2 0x42\r
-#define SPD_PB0 0x43\r
-#define SPD_PB1 0x44\r
-#define SPD_PB2 0x45\r
-#define SPD_PB3 0x46\r
-#define SPD_PB4 0x47\r
-#define SPD_PB5 0x48\r
-#define SPD_PB6 0x49\r
-#define SPD_PB7 0x4A\r
-#define SPD_PB8 0x4B\r
-#define SPD_PB9 0x4C\r
-#define SPD_PB10 0x4D\r
-#define SPD_PB11 0x4E\r
-#define SPD_PB12 0x4F\r
-#define SPD_PB13 0x50\r
-#define SPD_PB14 0x51\r
-#define SPD_PB15 0x52\r
-#define SPD_PB16 0x53\r
-#define SPD_PB17 0x54\r
-#define SPD_PB18 0x55\r
-#define SPD_PB19 0x56\r
-#define SPD_PB20 0x57\r
-#define SPD_PB21 0x58\r
-#define SPD_PB22 0x59\r
-#define SPD_PB23 0x5A\r
-#define SPD_PB24 0x5B\r
-#define SPD_PB25 0x5C\r
-#define SPD_PB26 0x5D\r
-#define SPD_PB27 0x5E\r
-\r
-#define MPEG_HBO 0x60\r
-#define MPEG_HB1 0x61\r
-#define MPEG_HB2 0x62\r
-#define MPEG_PB0 0x63\r
-#define MPEG_PB1 0x64\r
-#define MPEG_PB2 0x65\r
-#define MPEG_PB3 0x66\r
-#define MPEG_PB4 0x67\r
-#define MPEG_PB5 0x68\r
-#define MPEG_PB6 0x69\r
-#define MPEG_PB7 0x6A\r
-#define MPEG_PB8 0x6B\r
-#define MPEG_PB9 0x6C\r
-#define MPEG_PB10 0x6D\r
-#define MPEG_PB11 0x6E\r
-#define MPEG_PB12 0x6F\r
-#define MPEG_PB13 0x70\r
-#define MPEG_PB14 0x71\r
-#define MPEG_PB15 0x72\r
-#define MPEG_PB16 0x73\r
-#define MPEG_PB17 0x74\r
-#define MPEG_PB18 0x75\r
-#define MPEG_PB19 0x76\r
-#define MPEG_PB20 0x77\r
-#define MPEG_PB21 0x78\r
-#define MPEG_PB22 0x79\r
-#define MPEG_PB23 0x7A\r
-#define MPEG_PB24 0x7B\r
-#define MPEG_PB25 0x7C\r
-#define MPEG_PB26 0x7D\r
-#define MPEG_PB27 0x7E\r
-\r
-#define USRDF0_HBO 0x80\r
-#define USRDF0_HB1 0x81\r
-#define USRDF0_HB2 0x82\r
-#define USRDF0_PB0 0x83\r
-#define USRDF0_PB1 0x84\r
-#define USRDF0_PB2 0x85\r
-#define USRDF0_PB3 0x86\r
-#define USRDF0_PB4 0x87\r
-#define USRDF0_PB5 0x88\r
-#define USRDF0_PB6 0x89\r
-#define USRDF0_PB7 0x8A\r
-#define USRDF0_PB8 0x8B\r
-#define USRDF0_PB9 0x8C\r
-#define USRDF0_PB10 0x8D\r
-#define USRDF0_PB11 0x8E\r
-#define USRDF0_PB12 0x8F\r
-#define USRDF0_PB13 0x90\r
-#define USRDF0_PB14 0x91\r
-#define USRDF0_PB15 0x92\r
-#define USRDF0_PB16 0x93\r
-#define USRDF0_PB17 0x94\r
-#define USRDF0_PB18 0x95\r
-#define USRDF0_PB19 0x96\r
-#define USRDF0_PB20 0x97\r
-#define USRDF0_PB21 0x98\r
-#define USRDF0_PB22 0x99\r
-#define USRDF0_PB23 0x9A\r
-#define USRDF0_PB24 0x9B\r
-#define USRDF0_PB25 0x9C\r
-#define USRDF0_PB26 0x9D\r
-#define USRDF0_PB27 0x9E\r
-\r
-#define USRDF1_HBO 0xA0\r
-#define USRDF1_HB1 0xA1\r
-#define USRDF1_HB2 0xA2\r
-#define USRDF1_PB0 0xA3\r
-#define USRDF1_PB1 0xA4\r
-#define USRDF1_PB2 0xA5\r
-#define USRDF1_PB3 0xA6\r
-#define USRDF1_PB4 0xA7\r
-#define USRDF1_PB5 0xA8\r
-#define USRDF1_PB6 0xA9\r
-#define USRDF1_PB7 0xAA\r
-#define USRDF1_PB8 0xAB\r
-#define USRDF1_PB9 0xAC\r
-#define USRDF1_PB10 0xAD\r
-#define USRDF1_PB11 0xAE\r
-#define USRDF1_PB12 0xAF\r
-#define USRDF1_PB13 0xB0\r
-#define USRDF1_PB14 0xB1\r
-#define USRDF1_PB15 0xB2\r
-#define USRDF1_PB16 0xB3\r
-#define USRDF1_PB17 0xB4\r
-#define USRDF1_PB18 0xB5\r
-#define USRDF1_PB19 0xB6\r
-#define USRDF1_PB20 0xB7\r
-#define USRDF1_PB21 0xB8\r
-#define USRDF1_PB22 0xB9\r
-#define USRDF1_PB23 0xBA\r
-#define USRDF1_PB24 0xBB\r
-#define USRDF1_PB25 0xBC\r
-#define USRDF1_PB26 0xBD\r
-#define USRDF1_PB27 0xBE\r
-*/\r
-\r
-void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF);\r
-int anx7150_detect_device(struct anx7150_pdata *anx);\r
-u8 ANX7150_Get_System_State(void);\r
-int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state);\r
-int anx7150_unplug(struct i2c_client *client);\r
-int anx7150_plug(struct i2c_client *client);\r
-int ANX7150_API_Initial(struct i2c_client *client);\r
-void ANX7150_Shutdown(struct i2c_client *client);\r
-int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev);\r
-int ANX7150_GET_SENSE_STATE(struct i2c_client *client);\r
-int ANX7150_Get_Optimal_resolution(int resolution_set);\r
-void HDMI_Set_Video_Format(u8 video_format);\r
-void HDMI_Set_Audio_Fs( u8 audio_fs);\r
-void ANX7150_API_System_Config(void);\r
-u8 ANX7150_Config_Audio(struct i2c_client *client);\r
-u8 ANX7150_Config_Packet(struct i2c_client *client);\r
-void ANX7150_HDCP_Process(struct i2c_client *client);\r
-int ANX7150_PLAYBACK_Process(void);\r
-void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state);\r
-int ANX7150_Config_Video(struct i2c_client *client);\r
-int ANX7150_GET_RECIVER_TYPE(void);\r
-void HDMI_Set_Video_Format(u8 video_format);\r
-void HDMI_Set_Audio_Fs( u8 audio_fs);\r
-int ANX7150_PLAYBACK_Process(void);\r
-int ANX7150_Blue_Screen(struct anx7150_pdata *anx);\r
-\r
-\r
-#endif\r
+++ /dev/null
-// ANALOGIX Company\r
-// ANX7150 Demo Firmware\r
-#include <linux/delay.h>\r
-#include <linux/i2c.h>\r
-#include <linux/hdmi.h>\r
-\r
-\r
-#include "anx7150_sys.h"\r
-\r
-\r
-/******** define uint8 and WORD, by kfx *******/\r
-int anx7150_tmds_enable(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- /* andio stream enable */\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_HDMI_AUDCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDMI_AUDCTRL1_IN_EN);\r
-\r
- if((rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_HDMI_AUDCTRL1_REG, &c)) < 0)\r
- return rc;\r
-\r
- /* video stream enable */\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_VID_CTRL_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_VID_CTRL_IN_EN);\r
-\r
- if((rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_VID_CTRL_REG, &c)) < 0)\r
- return rc;\r
-\r
- /* TMDS enable */\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_TMDS_CLKCH_MUTE);\r
-\r
- if((rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c)) < 0)\r
- return rc;\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_tmds_disable(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- /* andio stream disable */\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_HDMI_AUDCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
-\r
- if((rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_HDMI_AUDCTRL1_REG, &c)) < 0)\r
- return rc;\r
-\r
- /* video stream disable */\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_VID_CTRL_REG, &c)) < 0)\r
- return rc;\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
-\r
- if((rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_VID_CTRL_REG, &c)) < 0)\r
- return rc;\r
-\r
- /* TMDS disable */\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c)) < 0)\r
- return rc;\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
-\r
- if((rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c)) < 0)\r
- return rc;\r
-\r
- return rc;\r
-}\r
-static void anx7150_set_video_format(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- switch(hdmi->resolution)\r
- {\r
- case HDMI_720x576p_50Hz:\r
- anx->video_format = ANX7150_V720x576p_50Hz_4x3;\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- anx->video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- anx->video_format = ANX7150_V1280x720p_60Hz;\r
- break;\r
- default:\r
- anx->video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- }\r
- anx->system_config_done = 0;\r
- return; \r
-}\r
-static void anx7150_set_audio_fs(struct hdmi *hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- anx->audio_format = hdmi->audio_fs;\r
- anx->system_config_done = 0;\r
- return; \r
-}\r
-\r
-static void anx7150_set_system_state(struct hdmi *hdmi, unsigned char ss)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- anx->system_state = ss;\r
- switch (ss)\r
- {\r
- case ANX7150_INITIAL:\r
- dev_info(hdmi->dev, "system state: ANX7150_INITIAL\n");\r
- break;\r
- case ANX7150_WAIT_HOTPLUG:\r
- dev_info(hdmi->dev, "system state: ANX7150_WAIT_HOTPLUG\n");\r
- break;\r
- case ANX7150_READ_PARSE_EDID:\r
- dev_info(hdmi->dev, "system state: ANX7150_READ_PARSE_EDID\n");\r
- break;\r
- case ANX7150_WAIT_RX_SENSE:\r
- dev_info(hdmi->dev, "system state: ANX7150_WAIT_RX_SENSE\n");\r
- break;\r
- case ANX7150_CONFIG_VIDEO:\r
- dev_info(hdmi->dev, "system state: ANX7150_CONFIG_VIDEO\n");\r
- break;\r
- case ANX7150_CONFIG_AUDIO:\r
- dev_info(hdmi->dev, "system state: ANX7150_CONFIG_AUDIO\n");\r
- break;\r
- case ANX7150_CONFIG_PACKETS:\r
- dev_info(hdmi->dev, "system state: ANX7150_CONFIG_PACKETS\n");\r
- break;\r
- case ANX7150_HDCP_AUTHENTICATION:\r
- dev_info(hdmi->dev, "system state: ANX7150_HDCP_AUTHENTICATION\n");\r
- break;\r
- case ANX7150_RESET_LINK:\r
- dev_info(hdmi->dev, "system state: ANX7150_RESET_LINK\n");\r
- break;\r
- case ANX7150_PLAY_BACK:\r
- dev_info(hdmi->dev, "system state: ANX7150_PLAY_BACK\n");\r
- break;\r
- default:\r
- dev_info(hdmi->dev, "system state: ANX7150 unknown state\n");\r
- break;\r
- }\r
- return;\r
-}\r
-\r
-static void anx7150_variable_initial(struct hdmi *hdmi)\r
-{\r
- int i;\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
- \r
- anx7150_set_system_state(hdmi, ANX7150_INITIAL);\r
- \r
- anx->anx7150_hdcp_auth_en = 0;\r
- anx->anx7150_ksv_srm_pass =0;\r
- anx->anx7150_srm_checked = 0;\r
- anx->anx7150_hdcp_auth_pass = 0;\r
- anx->anx7150_avmute_enable = 1;\r
- anx->anx7150_hdcp_auth_fail_counter =0;\r
- anx->anx7150_hdcp_encryption = 0;\r
- anx->anx7150_send_blue_screen = 0;\r
- anx->anx7150_hdcp_init_done = 0;\r
- anx->anx7150_hdcp_wait_100ms_needed = 1;\r
- anx->anx7150_auth_fully_pass = 0;\r
- anx->timer_slot = 0;\r
- /***************for video config***************/\r
- anx->anx7150_video_timing_id = 0;\r
- anx->anx7150_in_pix_rpt = 0;\r
- anx->anx7150_tx_pix_rpt = 0;\r
- anx->anx7150_new_csc = 0;\r
- anx->anx7150_new_vid_id = 0;\r
- anx->anx7150_new_hw_interface = 0;\r
- /*****************end of video config**********/\r
-\r
- /********************for edid parse************/\r
- anx->edid.is_HDMI = 0;\r
- anx->edid.ycbcr422_supported = 0;\r
- anx->edid.ycbcr444_supported = 0;\r
- anx->edid.supported_720p_60Hz = 0;\r
- anx->edid.supported_720p_50Hz = 0;\r
- anx->edid.supported_576p_50Hz = 0;\r
- anx->edid.supported_576i_50Hz = 0;\r
- anx->edid.supported_1080i_60Hz = 0;\r
- anx->edid.supported_1080i_50Hz = 0;\r
- anx->edid.supported_640x480p_60Hz = 0;\r
- anx->edid.supported_720x480p_60Hz = 0;\r
- anx->edid.supported_720x480i_60Hz = 0;\r
- anx->edid.edid_errcode = 0;\r
- anx->edid.SpeakerFormat = 0;\r
- for (i = 0; i < 8; i ++)\r
- {\r
- anx->edid.AudioChannel[i] = 0;\r
- anx->edid.AudioFormat[i] = 0;\r
- anx->edid.AudioFs[i] = 0;\r
- anx->edid.AudioLength[i] = 0;\r
- }\r
- /********************end of edid****************/\r
-\r
- anx->packets_config.packets_need_config = 0x03; //new avi infoframe\r
- anx->packets_config.avi_info.type = 0x82;\r
- anx->packets_config.avi_info.version = 0x02;\r
- anx->packets_config.avi_info.length = 0x0d;\r
- anx->packets_config.avi_info.pb_uint8[1] = 0x21;//YCbCr422\r
- anx->packets_config.avi_info.pb_uint8[2] = 0x08;\r
- anx->packets_config.avi_info.pb_uint8[3] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[4] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[5] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[6] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[7] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[8] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[9] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[10] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[11] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[12] = 0x00;\r
- anx->packets_config.avi_info.pb_uint8[13] = 0x00;\r
-\r
- // audio infoframe\r
- anx->packets_config.audio_info.type = 0x84;\r
- anx->packets_config.audio_info.version = 0x01;\r
- anx->packets_config.audio_info.length = 0x0a;\r
- anx->packets_config.audio_info.pb_uint8[1] = 0x00; //zy 061123 for ATC\r
- anx->packets_config.audio_info.pb_uint8[2] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[3] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[4] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[5] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[6] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[7] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[8] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[9] = 0x00;\r
- anx->packets_config.audio_info.pb_uint8[10] = 0x00;\r
-\r
- anx->anx7150_int_done = 0;\r
-}\r
-\r
-\r
-static void anx7150_hw_interface_variable_initial(struct hdmi *hdmi)\r
-{\r
- unsigned char c;\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
- \r
- anx->anx7150_video_format_config = 0x00;\r
- anx->anx7150_rgborycbcr = 0x00;\r
- anx->anx7150_ddr_edge = ANX7150_IDCK_EDGE_DDR;\r
-\r
- c = 0;\r
- c = (ANX7150_I2S_CH0_ENABLE << 2) | (ANX7150_I2S_CH1_ENABLE << 3) |\r
- (ANX7150_I2S_CH2_ENABLE << 4) | (ANX7150_I2S_CH3_ENABLE << 5);\r
- \r
- anx->audio_config.audio_type = ANX7150_AUD_HW_INTERFACE; // input I2S\r
- anx->audio_config.down_sample = 0x00;\r
- anx->audio_config.i2s_config.audio_channel = c;//0x04;\r
- anx->audio_config.i2s_config.Channel_status1 =0x00;\r
- anx->audio_config.i2s_config.Channel_status1 = 0x00;\r
- anx->audio_config.i2s_config.Channel_status2 = 0x00;\r
- anx->audio_config.i2s_config.Channel_status3 = 0x00;\r
- anx->audio_config.i2s_config.Channel_status4 = 0x00;//0x02;//48k\r
- anx->audio_config.i2s_config.Channel_status5 = ANX7150_I2S_WORD_LENGTH;//0x0b;\r
- anx->audio_config.audio_layout = 0x00;\r
-\r
- c = (ANX7150_I2S_SHIFT_CTRL << 3) | (ANX7150_I2S_DIR_CTRL << 2) |\r
- (ANX7150_I2S_WS_POL << 1) | ANX7150_I2S_JUST_CTRL;\r
- anx->audio_config.i2s_config.i2s_format = c;//0x00;\r
-\r
- anx->freq_mclk= ANX7150_MCLK_Fs_RELATION;//set the relation of MCLK and WS\r
- anx->anx7150_audio_clock_edge = ANX7150_AUD_CLK_EDGE;\r
- return;\r
-}\r
-static int anx7150_hardware_initial(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
- char c = 0;\r
- \r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_CTRL2_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- mdelay(10);\r
-\r
- c &= (~0x01);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL2_REG, &c);\r
- \r
- //Power on I2C\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (ANX7150_SYS_CTRL3_I2C_PWON);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL3_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL2_REG, &c);\r
- c= 0x00;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SRST_REG, &c);\r
-\r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xbf);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //Power on Audio capture and Video capture module clock\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_PD_REG, &c);\r
- c |= (0x06);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_PD_REG, &c);\r
-\r
- //Enable auto set clock range for video PLL\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_CHIP_CTRL_REG, &c);\r
- c &= (0x00);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_CHIP_CTRL_REG, &c);\r
-\r
- //Set registers value of Blue Screen when HDCP authentication failed--RGB mode,green field\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, (c | 0x80));\r
-\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_PLL_CTRL0_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_PLL_CTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
- c |= (0x08);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_PLL_TX_AMP, &c);//jack wen\r
- c |= (0x01);\r
-\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_PLL_TX_AMP, &c); //TMDS swing\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_PLL_CTRL1_REG, &c); //Added for PLL unlock issue in high temperature - Feiw\r
- //if (ANX7150_AUD_HW_INTERFACE == 0x02) //jack wen, spdif\r
-\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_I2S_CTRL_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xef);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_I2S_CTRL_REG, &c);\r
-\r
- c = 0xc7;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, 0xE1, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL1_REG, &c);//power down HDCP, 090630\r
-\r
- rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_CTRL3_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xef);\r
- rc = anx7150_i2c_write_p0_reg(hdmi->client, ANX7150_SYS_CTRL3_REG, &c);//power down all, 090630\r
-\r
- //anx7150_set_system_state(hdmi, ANX7150_WAIT_HOTPLUG);\r
- return rc;\r
-}\r
-\r
-static int anx7150_initial(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
- anx7150_variable_initial(hdmi);\r
- anx7150_hw_interface_variable_initial(hdmi);\r
-\r
- rc = anx7150_hardware_initial(hdmi);\r
- return rc;\r
-}\r
-static void anx7150_set_hdcp_state(struct hdmi* hdmi)\r
-{\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- anx->hdcp_on = hdmi->hdcp_on;\r
- return;\r
-}\r
-int anx7150_system_init(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
-\r
- if((rc = anx7150_detect_device(hdmi)) < 0)\r
- {\r
- dev_err(hdmi->dev, "anx7150 api detectdevice err!\n");\r
- return rc;\r
- }\r
- anx7150_set_audio_fs(hdmi);\r
- \r
- if((rc = anx7150_initial(hdmi)) < 0)\r
- {\r
- dev_err(hdmi->dev, "anx7150 initial err!\n");\r
- return rc;\r
- }\r
- anx7150_set_hdcp_state(hdmi);\r
-\r
- return 0;\r
-}\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-static u8 anx7150_detect_device(struct hdmi *hdmi)\r
-{\r
- int i, rc = 0;\r
- char d1, d2;\r
- \r
- for (i=0; i<10; i++)\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_DEV_IDL_REG, &d1)) < 0)\r
- continue;\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_DEV_IDH_REG, &d2)) < 0)\r
- continue;\r
- if (d1 == 0x50 && d2 == 0x71)\r
- {\r
- dev_info(hdmi->dev, "anx7150 detected!\n");\r
- return 1;\r
- }\r
- }\r
- \r
- dev_info(hdmi->dev, "anx7150 not detected");\r
- return 0;\r
-}\r
-static u8 anx7150_get_system_state(struct anx7150_pdata *anx)\r
-{\r
- return anx->anx7150_system_state;\r
-}\r
-static u8 anx7150_get_hpd(struct i2c_client *client)\r
-{\r
- char c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_CTRL3_REG, &c)) < 0)\r
- return rc;\r
- if(c & ANX7150_SYS_CTRL3_PWON_ALL)\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_SYS_STATE_REG, &c)) < 0)\r
- return rc;\r
- return (c & ANX7150_SYS_STATE_HP)? 1:0;\r
- }\r
- else\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(hdmi->client, ANX7150_INTR_STATE_REG, &c)) < 0)\r
- return rc;\r
- return (c)? 1:0;\r
- }\r
-}\r
-static u8 anx7150_interrupt_process(struct hdmi *hdmi, int state)\r
-{\r
- int hot_plug;\r
- int rc;\r
-\r
- hot_plug = anx7150_get_hpd(hdmi->client);\r
-}\r
-\r
-int anx7150_display_on_hw(struct hdmi *hdmi)\r
-{\r
- u8 state;\r
- struct anx7150_pdata *anx = hdmi_get_privdata(hdmi);\r
-\r
- anx->anx7150_detect = anx7150_detect_device(hdmi);\r
- if(anx->anx7150_detect < 0)\r
- {\r
- return -EIO;\r
- }\r
-\r
- state = anx7150_get_system_state(anx);\r
- if(hdmi->display_on == 0 && hdmi->auto_switch == 0)\r
- {\r
- if(state > WAIT_HDMI_ENABLE)\r
- state = INITIAL;\r
- }\r
- if(hdmi->param_conf == 1)\r
- {\r
- if(state > WAIT_HDMI_ENABLE)\r
- state = WAIT_HDMI_ENABLE;\r
- hdmi->param_conf = 0;\r
- }\r
-\r
- state = anx7150_interrupt_process();\r
- \r
-}\r
-\r
-\r
+++ /dev/null
-#include <linux/hdmi.h>
-
-int hdmi_codec_set_audio_fs(unsigned char audio_fs)
-{
- return 0;
-}
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/delay.h>\r
-#include <linux/module.h>\r
-#include <linux/err.h>\r
-\r
-#include <linux/hdmi.h>\r
-\r
-struct class *hdmi_class;\r
-struct hdmi_id_ref_info {\r
- struct hdmi *hdmi;\r
- int id;\r
- int ref;\r
-}ref_info[HDMI_MAX_ID];\r
-#ifdef CONFIG_SYSFS\r
-\r
-extern int hdmi_create_attrs(struct hdmi *hdmi);\r
-extern void hdmi_remove_attrs(struct hdmi *hdmi);\r
-\r
-#else\r
-\r
-static inline int hdmi_create_attrs(struct hdmi *hdmi)\r
-{ return 0; }\r
-static inline void hdmi_remove_attrs(struct hdmi *hdmi) {}\r
-\r
-#endif /* CONFIG_SYSFS */\r
-\r
-void *hdmi_get_privdata(struct hdmi *hdmi)\r
-{\r
- return hdmi->priv;\r
-}\r
-void hdmi_set_privdata(struct hdmi *hdmi, void *data)\r
-{\r
- hdmi->priv = data;\r
- return;\r
-}\r
-\r
-void hdmi_changed(struct hdmi *hdmi, int plug)\r
-{\r
- hdmi_dbg(hdmi->dev, "%s\n", __FUNCTION__);\r
- hdmi->plug = plug;\r
- schedule_work(&hdmi->changed_work);\r
-}\r
-\r
-static void hdmi_changed_work(struct work_struct *work)\r
-{\r
- struct hdmi *hdmi = container_of(work, struct hdmi,\r
- changed_work);\r
-\r
- hdmi_dbg(hdmi->dev, "%s\n", __FUNCTION__);\r
-\r
- kobject_uevent(&hdmi->dev->kobj, KOBJ_CHANGE);\r
-}\r
-\r
-int hdmi_register(struct device *parent, struct hdmi *hdmi)\r
-{\r
- int rc = 0, i;\r
- char name[8];\r
-\r
- for(i = 0; i < HDMI_MAX_ID; i++) \r
- {\r
- if(ref_info[i].ref == 0)\r
- {\r
- ref_info[i].ref = 1;\r
- hdmi->id = i;\r
- break;\r
- }\r
- }\r
- if(i == HDMI_MAX_ID)\r
- return -EINVAL;\r
- sprintf(name, "hdmi-%d", hdmi->id);\r
- \r
- hdmi->dev = device_create(hdmi_class, parent, 0,\r
- "%s", name);\r
- if (IS_ERR(hdmi->dev)) {\r
- rc = PTR_ERR(hdmi->dev);\r
- goto dev_create_failed;\r
- }\r
-\r
- dev_set_drvdata(hdmi->dev, hdmi);\r
- ref_info[i].hdmi = hdmi;\r
-\r
- INIT_WORK(&hdmi->changed_work, hdmi_changed_work);\r
-\r
- rc = hdmi_create_attrs(hdmi);\r
- if (rc)\r
- goto create_attrs_failed;\r
-\r
- //hdmi_changed(hdmi, 0);\r
-\r
- goto success;\r
-\r
-create_attrs_failed:\r
- device_unregister(hdmi->dev);\r
-dev_create_failed:\r
-success:\r
- return rc;\r
-}\r
-void hdmi_unregister(struct hdmi *hdmi)\r
-{\r
- int id;\r
-\r
- if(!hdmi)\r
- return;\r
- id = hdmi->id;\r
- flush_scheduled_work();\r
- hdmi_remove_attrs(hdmi);\r
- device_unregister(hdmi->dev);\r
- ref_info[id].ref = 0;\r
- ref_info[id].hdmi = NULL;\r
-}\r
-struct hdmi *get_hdmi_struct(int nr)\r
-{\r
- if(ref_info[nr].ref == 0)\r
- return NULL;\r
- else\r
- return ref_info[nr].hdmi;\r
-}\r
-static int __init hdmi_class_init(void)\r
-{\r
- int i;\r
- \r
- hdmi_class = class_create(THIS_MODULE, "hdmi");\r
-\r
- if (IS_ERR(hdmi_class))\r
- return PTR_ERR(hdmi_class);\r
- for(i = 0; i < HDMI_MAX_ID; i++) {\r
- ref_info[i].id = i;\r
- ref_info[i].ref = 0;\r
- ref_info[i].hdmi = NULL;\r
- }\r
- return 0;\r
-}\r
-\r
-static void __exit hdmi_class_exit(void)\r
-{\r
- class_destroy(hdmi_class);\r
-}\r
-EXPORT_SYMBOL(hdmi_changed);\r
-EXPORT_SYMBOL(hdmi_register);\r
-EXPORT_SYMBOL(hdmi_unregister);\r
-EXPORT_SYMBOL(get_hdmi_struct);\r
-\r
-subsys_initcall(hdmi_class_init);\r
-module_exit(hdmi_class_exit);\r
-\r
+++ /dev/null
-#include <linux/console.h>
-#include <linux/fb.h>
-
-#include <linux/completion.h>
-#include "../../display/screen/screen.h"
-#include <linux/hdmi.h>
-#include "../../rk29_fb.h"
-
-
-/* Base */
-#define LCD_ACLK 500000000// 312000000
-
-#define OUT_TYPE SCREEN_HDMI
-#define OUT_FACE OUT_P888
-#define DCLK_POL 1
-#define SWAP_RB 0
-
-/* 720p@60Hz Timing */
-#define OUT_CLK 74250000
-#define H_PW 40
-#define H_BP 220
-#define H_VD 1280
-#define H_FP 110
-#define V_PW 5
-#define V_BP 20
-#define V_VD 720
-#define V_FP 5
-
-/* 720p@50Hz Timing */
-#define OUT_CLK2 74250000
-#define H_PW2 40
-#define H_BP2 220
-#define H_VD2 1280
-#define H_FP2 440
-#define V_PW2 5
-#define V_BP2 20
-#define V_VD2 720
-#define V_FP2 5
-
-/* 576p@50Hz Timing */
-#define OUT_CLK3 27000000
-#define H_PW3 64
-#define H_BP3 68
-#define H_VD3 720
-#define H_FP3 12
-#define V_PW3 5
-#define V_BP3 39
-#define V_VD3 576
-#define V_FP3 5
-
-/* 1080p@50Hz Timing */
-#define OUT_CLK4 148500000
-#define H_PW4 44
-#define H_BP4 148
-#define H_VD4 1920
-#define H_FP4 528
-#define V_PW4 5
-#define V_BP4 35
-#define V_VD4 1080
-#define V_FP4 5
-
-
-extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable );
-
-static int anx7150_init(void)
-{
- return 0;
-}
-
-static int anx7150_standby(u8 enable)
-{
- return 0;
-}
-
-static void hdmi_set_info(struct rk29fb_screen *screen)
-{
- struct rk29fb_screen *screen2 = screen + 1;
- struct rk29fb_screen *screen3 = screen + 2;
- struct rk29fb_screen *screen4 = screen + 3;
-
- /* ****************** 720p@60Hz ******************* */
- /* screen type & face */
- screen->type = OUT_TYPE;
- screen->face = OUT_FACE;
-
- /* Screen size */
- screen->x_res = H_VD;
- screen->y_res = V_VD;
-
- /* Timing */
- screen->pixclock = OUT_CLK;
- screen4->lcdc_aclk = LCD_ACLK;
- screen->left_margin = H_BP;
- screen->right_margin = H_FP;
- screen->hsync_len = H_PW;
- screen->upper_margin = V_BP;
- screen->lower_margin = V_FP;
- screen->vsync_len = V_PW;
-
- /* Pin polarity */
- screen->pin_hsync = 0;
- screen->pin_vsync = 0;
- screen->pin_den = 0;
- screen->pin_dclk = DCLK_POL;
-
- /* Swap rule */
- screen->swap_rb = SWAP_RB;
- screen->swap_rg = 0;
- screen->swap_gb = 0;
- screen->swap_delta = 0;
- screen->swap_dumy = 0;
-
- /* Operation function*/
- screen->init = anx7150_init;
- screen->standby = anx7150_standby;
-
-
- /* ****************** 720p@50Hz ******************* */
- /* screen type & face */
- screen2->type = OUT_TYPE;
- screen2->face = OUT_FACE;
-
- /* Screen size */
- screen2->x_res = H_VD2;
- screen2->y_res = V_VD2;
-
- /* Timing */
- screen2->pixclock = OUT_CLK2;
- screen2->lcdc_aclk = LCD_ACLK;
- screen2->left_margin = H_BP2;
- screen2->right_margin = H_FP2;
- screen2->hsync_len = H_PW2;
- screen2->upper_margin = V_BP2;
- screen2->lower_margin = V_FP2;
- screen2->vsync_len = V_PW2;
-
- /* Pin polarity */
- screen2->pin_hsync = 0;
- screen2->pin_vsync = 0;
- screen2->pin_den = 0;
- screen2->pin_dclk = DCLK_POL;
-
- /* Swap rule */
- screen2->swap_rb = SWAP_RB;
- screen2->swap_rg = 0;
- screen2->swap_gb = 0;
- screen2->swap_delta = 0;
- screen2->swap_dumy = 0;
-
- /* Operation function*/
- screen2->init = anx7150_init;
- screen2->standby = anx7150_standby;
-
- /* ****************** 576p@50Hz ******************* */
- /* screen type & face */
- screen3->type = OUT_TYPE;
- screen3->face = OUT_FACE;
-
- /* Screen size */
- screen3->x_res = H_VD3;
- screen3->y_res = V_VD3;
-
- /* Timing */
- screen3->pixclock = OUT_CLK3;
- screen3->lcdc_aclk = LCD_ACLK;
- screen3->left_margin = H_BP3;
- screen3->right_margin = H_FP3;
- screen3->hsync_len = H_PW3;
- screen3->upper_margin = V_BP3;
- screen3->lower_margin = V_FP3;
- screen3->vsync_len = V_PW3;
-
- /* Pin polarity */
- screen3->pin_hsync = 0;
- screen3->pin_vsync = 0;
- screen3->pin_den = 0;
- screen3->pin_dclk = DCLK_POL;
-
- /* Swap rule */
- screen3->swap_rb = SWAP_RB;
- screen3->swap_rg = 0;
- screen3->swap_gb = 0;
- screen3->swap_delta = 0;
- screen3->swap_dumy = 0;
-
- /* Operation function*/
- screen3->init = anx7150_init;
- screen3->standby = anx7150_standby;
- /* ****************** 1080p@50Hz ******************* */
- /* screen type & face */
- screen4->type = OUT_TYPE;
- screen4->face = OUT_FACE;
-
- /* Screen size */
- screen4->x_res = H_VD4;
- screen4->y_res = V_VD4;
-
- /* Timing */
- screen4->pixclock = OUT_CLK4;
- screen4->lcdc_aclk = LCD_ACLK;
- screen4->left_margin = H_BP4;
- screen4->right_margin = H_FP4;
- screen4->hsync_len = H_PW4;
- screen4->upper_margin = V_BP4;
- screen4->lower_margin = V_FP4;
- screen4->vsync_len = V_PW4;
-
- /* Pin polarity */
- screen4->pin_hsync = 0;
- screen4->pin_vsync = 0;
- screen4->pin_den = 0;
- screen4->pin_dclk = DCLK_POL;
-
- /* Swap rule */
- screen4->swap_rb = SWAP_RB;
- screen4->swap_rg = 0;
- screen4->swap_gb = 0;
- screen4->swap_delta = 0;
- screen4->swap_dumy = 0;
-
- /* Operation function*/
- screen4->init = anx7150_init;
- screen4->standby = anx7150_standby;
-}
-
-int hdmi_switch_fb(struct hdmi *hdmi, int type)
-{
- int rc = 0;
- struct rk29fb_screen hdmi_info[4];
-
- hdmi_set_info(&hdmi_info[0]);
-
- switch(hdmi->resolution)
- {
- case HDMI_1280x720p_50Hz:
- rc = FB_Switch_Screen(&hdmi_info[1], type);
- break;
- case HDMI_1280x720p_60Hz:
- rc = FB_Switch_Screen(&hdmi_info[0], type);
- break;
- case HDMI_720x576p_50Hz:
- rc = FB_Switch_Screen(&hdmi_info[2], type);
- break;
- case HDMI_1920x1080p_50Hz:
- rc = FB_Switch_Screen(&hdmi_info[3], type);
- break;
- default:
- rc = FB_Switch_Screen(&hdmi_info[1], type);
- break;
- }
- if(hdmi->wait == 1) {
- complete(&hdmi->complete);
- hdmi->wait = 0;
- }
- return rc;
-}
-int hdmi_resolution_changed(struct hdmi *hdmi, int xres, int yres, int video_on)
-{
- int ret = 0;
- if(hdmi->display_on == 0|| hdmi->plug == 0)
- return ret;
- if(xres > 1280 && hdmi->resolution != HDMI_1920x1080p_50Hz)
- {
- hdmi->resolution = HDMI_1920x1080p_50Hz;
- hdmi->display_on = 1;
- hdmi->hdmi_set_param(hdmi);
- ret = 1;
- }
-
-
- else if(xres >1024 && xres <= 1280 && hdmi->resolution != HDMI_1280x720p_50Hz){
- hdmi->resolution = HDMI_1280x720p_50Hz;
- hdmi->display_on = 1;
- hdmi->hdmi_set_param(hdmi);
- ret = 1;
- }
- /*
- else {
- if(hdmi->display_on == 1)
- hdmi->hdmi_display_off(hdmi);
- }*/
- return ret;
-}
-
-int hdmi_get_default_resolution(void *screen)
-{
- struct rk29fb_screen hdmi_info[4];
-
- hdmi_set_info(&hdmi_info[0]);
- memcpy((struct rk29fb_screen*)screen, &hdmi_info[HDMI_DEFAULT_RESOLUTION], sizeof(struct rk29fb_screen));
- return 0;
-}
-
-
-EXPORT_SYMBOL(hdmi_resolution_changed);
+++ /dev/null
-#include <linux/ctype.h>\r
-#include <linux/hdmi.h>\r
-#include <linux/string.h>\r
-\r
-\r
-static ssize_t hdmi_show_state_attrs(struct device *dev,\r
- struct device_attribute *attr,\r
- char *buf) \r
-{\r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
-\r
- return sprintf(buf, "display_on=%d\n"\r
- "plug=%d\n"\r
- "--------------------------\n"\r
- "resolution support:\n"\r
- "0 -- 1280x720p_50Hz\n"\r
- "1 -- 1280x720p_60Hz\n"\r
- "2 -- 720x576p_50Hz\n"\r
- "3 -- 1920x1080p_50Hz\n"\r
- "--------------------------\n"\r
- "auto_switch=%d\n"\r
- "hdcp_on=%d\n"\r
- "audio_fs=%d\n"\r
- "resolution=%d\n", \r
- hdmi->display_on,hdmi->plug,\r
- hdmi->auto_switch, hdmi->hdcp_on,\r
- hdmi->audio_fs, hdmi->resolution);\r
-}\r
-static ssize_t hdmi_restore_state_attrs(struct device *dev, \r
- struct device_attribute *attr,\r
- const char *buf, size_t size)\r
-{\r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
- char *p;\r
- const char *q;\r
- int auto_switch = -1, hdcp_on = -1, audio_fs = -1, resolution = -1;\r
- \r
- q = buf;\r
- do\r
- {\r
- if((p = strstr(q, "auto_switch=")) != NULL)\r
- {\r
- q = p + 12;\r
- if((sscanf(q, "%d", &auto_switch) == 1) &&\r
- (auto_switch == 0 || auto_switch == 1))\r
- hdmi->auto_switch = auto_switch;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- return -EINVAL;\r
- }\r
- }\r
- else if((p = strstr(q, "hdcp_on=")) != NULL)\r
- {\r
- q = p + 8;\r
- if((sscanf(q, "%d", &hdcp_on) == 1) &&\r
- (hdcp_on == 0 || hdcp_on == 1))\r
- hdmi->hdcp_on = hdcp_on;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- return -EINVAL;\r
- }\r
- }\r
- else if((p = strstr(q, "audio_fs=")) != NULL)\r
- {\r
- q = p + 9;\r
- if((sscanf(q, "%d", &audio_fs) == 1) &&\r
- (audio_fs >= 0))\r
- hdmi->audio_fs = audio_fs;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- return -EINVAL;\r
- }\r
- }\r
- else if((p = strstr(q, "resolution=")) != NULL)\r
- {\r
- q = p + 11;\r
- if((sscanf(q, "%d", &resolution) == 1) &&\r
- (resolution >= 0))\r
- hdmi->resolution = resolution;\r
- else\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- return -EINVAL;\r
- }\r
- }\r
- else\r
- break;\r
- \r
- }while(*q != 0);\r
- if(auto_switch == -1 &&\r
- hdcp_on == -1 &&\r
- audio_fs == -1 &&\r
- resolution == -1)\r
- {\r
- dev_err(dev, "failed to set hdmi configuration\n");\r
- return -EINVAL;\r
- }\r
- if(hdmi->hdmi_set_param)\r
- hdmi->hdmi_set_param(hdmi);\r
- return size;\r
-}\r
-\r
-static ssize_t hdmi_show_switch_attrs(struct device *dev,\r
- struct device_attribute *attr,\r
- char *buf) \r
-{ \r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
-\r
- return sprintf(buf, "%d\n", hdmi->display_on);\r
-}\r
-static ssize_t hdmi_restore_switch_attrs(struct device *dev, \r
- struct device_attribute *attr,\r
- const char *buf, size_t size)\r
-{\r
- int display_on = 0;\r
- struct hdmi *hdmi = dev_get_drvdata(dev);\r
- \r
- sscanf(buf, "%d", &display_on);\r
-\r
- if(hdmi->hdmi_display_on && display_on == 1)\r
- hdmi->hdmi_display_on(hdmi);\r
- else if(hdmi->hdmi_display_off && display_on == 0)\r
- hdmi->hdmi_display_off(hdmi);\r
-\r
- return size;\r
-}\r
-static struct device_attribute hdmi_attrs[] = {\r
- __ATTR(state, 0664, hdmi_show_state_attrs, hdmi_restore_state_attrs),\r
- __ATTR(enable, 0664, hdmi_show_switch_attrs, hdmi_restore_switch_attrs),\r
-};\r
-\r
-int hdmi_create_attrs(struct hdmi *hdmi)\r
-{\r
- int rc = 0;\r
- int i;\r
-\r
- for (i = 0; i < ARRAY_SIZE(hdmi_attrs); i++) {\r
- rc = device_create_file(hdmi->dev, &hdmi_attrs[i]);\r
- if (rc)\r
- goto create_failed;\r
- }\r
-\r
- goto succeed;\r
-\r
-create_failed:\r
- while (i--)\r
- device_remove_file(hdmi->dev, &hdmi_attrs[i]);\r
-succeed:\r
- return rc;\r
-}\r
-\r
-void hdmi_remove_attrs(struct hdmi *hdmi)\r
-{\r
- int i;\r
-\r
- for (i = 0; i < ARRAY_SIZE(hdmi_attrs); i++)\r
- device_remove_file(hdmi->dev, &hdmi_attrs[i]);\r
-}\r
-\r
-\r
--- /dev/null
+#include <linux/ctype.h>\r
+#include <linux/hdmi.h>\r
+#include <linux/string.h>\r
+\r
+int debug_en = 1;\r
+static ssize_t hdmi_show_state_attrs(struct device *dev,\r
+ struct device_attribute *attr,\r
+ char *buf) \r
+{\r
+ struct hdmi *hdmi = dev_get_drvdata(dev);\r
+\r
+ return sprintf(buf, "display_on=%d\n"\r
+ "plug=%d\n"\r
+ "dual_disp=%d\n"\r
+ "video_mode=%d\n"\r
+ "mode=%d\n"\r
+ "hdcp_on=%d\n"\r
+ "audio_fs=%d\n"\r
+ "scale=%d\n"\r
+ "scale_set=%d\n"\r
+ "resolution=%d\n"\r
+ "--------------------------\n"\r
+ "resolution support:\n"\r
+ "HDMI_1920x1080p_50Hz 0\n"\r
+ "HDMI_1920x1080p_60Hz 1\n"\r
+ "HDMI_1280x720p_50Hz 2\n"\r
+ "HDMI_1280x720p_60Hz 3\n"\r
+ "HDMI_720x576p_50Hz_4x3 4\n"\r
+ "HDMI_720x576p_50Hz_16x9 5\n"\r
+ "HDMI_720x480p_60Hz_4x3 6\n"\r
+ "HDMI_720x480p_60Hz_16x9 7\n"\r
+ "--------------------------\n", \r
+ hdmi->display_on,hdmi->ops->hdmi_precent(hdmi),\r
+ hdmi->dual_disp,fb_get_video_mode(), hdmi->mode, hdmi->hdcp_on,\r
+ hdmi->audio_fs, (hdmi->ops->hdmi_precent(hdmi) && hdmi->display_on)?hdmi->scale:100, \r
+ hdmi->scale_set,\r
+ hdmi->resolution);\r
+}\r
+static ssize_t hdmi_restore_state_attrs(struct device *dev, \r
+ struct device_attribute *attr,\r
+ const char *buf, size_t size)\r
+{\r
+ int ret = 0;\r
+ struct hdmi *hdmi = dev_get_drvdata(dev);\r
+ char *p;\r
+ const char *q;\r
+ int set_param = 0, tmp = 0;\r
+\r
+ if(hdmi->mode == DISP_ON_LCD)\r
+ {\r
+ dev_err(dev, "display on lcd, do not set parameter!\n");\r
+ ret = -EINVAL;\r
+ goto exit;\r
+ }\r
+\r
+ q = buf;\r
+ do\r
+ {\r
+ if((p = strstr(q, "mode=")) != NULL)\r
+ {\r
+ q = p + 5;\r
+#if 0\r
+ if((sscanf(q, "%d", &tmp) == 1) && (tmp >= 0 && tmp <= 3))\r
+ {\r
+ if(tmp != hdmi->mode)\r
+ {\r
+ set_param |= 1;\r
+ hdmi->mode = tmp;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ dev_err(dev, "failed to set hdmi configuration\n");\r
+ ret = -EINVAL;\r
+ goto exit;\r
+ }\r
+#endif\r
+ }\r
+\r
+ else if((p = strstr(q, "hdcp_on=")) != NULL)\r
+ {\r
+ q = p + 8;\r
+#if 0\r
+ if((sscanf(q, "%d", &tmp) == 1) && (tmp == 0 || tmp ==1))\r
+ {\r
+ if(tmp != hdmi->hdcp_on)\r
+ {\r
+ set_param |= 1;\r
+ hdmi->hdcp_on = tmp;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ dev_err(dev, "failed to set hdmi configuration\n");\r
+ ret = -EINVAL;\r
+ goto exit;\r
+ }\r
+#endif\r
+ }\r
+\r
+\r
+ else if((p = strstr(q, "scale_set=")) != NULL)\r
+ {\r
+ q = p + 10;\r
+ if((sscanf(q, "%d", &tmp) == 1) && (tmp >=MIN_SCALE && tmp <= 100))\r
+ {\r
+ hdmi->scale_set = tmp;\r
+ hdmi_dbg(dev, "set scale = %d\n", tmp);\r
+ hdmi->scale = tmp;\r
+ }\r
+ else\r
+ {\r
+ dev_err(dev, "failed to set hdmi configuration\n");\r
+ ret = -EINVAL;\r
+ goto exit;\r
+ }\r
+ }\r
+ else if((p = strstr(q, "resolution=")) != NULL)\r
+ {\r
+ q = p + 11;\r
+ if((sscanf(q, "%d", &tmp) == 1) && (tmp >= 0))\r
+ {\r
+ if(hdmi->resolution != tmp)\r
+ {\r
+ set_param |= 1;\r
+ hdmi_dbg(dev, "set resolution = %d\n", tmp);\r
+ hdmi->resolution = tmp;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ dev_err(dev, "failed to set hdmi configuration\n");\r
+ ret = -EINVAL;\r
+ goto exit;\r
+ }\r
+ }\r
+ else\r
+ break;\r
+ \r
+ }while(*q != 0);\r
+ if(hdmi->ops->set_param && set_param != 0)\r
+ {\r
+ mutex_lock(&hdmi->lock);\r
+ ret = hdmi->ops->set_param(hdmi);\r
+ mutex_unlock(&hdmi->lock);\r
+ }\r
+exit:\r
+ if(ret < 0)\r
+ dev_err(dev, "hdmi_restore_state_attrs err\n");\r
+ return size;\r
+}\r
+\r
+static ssize_t hdmi_show_switch_attrs(struct device *dev,\r
+ struct device_attribute *attr,\r
+ char *buf) \r
+{ \r
+ struct hdmi *hdmi = dev_get_drvdata(dev);\r
+\r
+ return sprintf(buf, "%d\n", hdmi->display_on);\r
+}\r
+static ssize_t hdmi_restore_switch_attrs(struct device *dev, \r
+ struct device_attribute *attr,\r
+ const char *buf, size_t size)\r
+{\r
+ int display_on = 0;\r
+ struct hdmi *hdmi = dev_get_drvdata(dev);\r
+ \r
+ sscanf(buf, "%d", &display_on);\r
+ hdmi_dbg(dev, "hdmi %s\n", (display_on)?"enable":"disable");\r
+ if(display_on ^ hdmi->display_on)\r
+ {\r
+ hdmi->display_on = display_on;\r
+ hdmi_changed(hdmi, 1);\r
+ }\r
+ return size;\r
+}\r
+static ssize_t hdmi_show_debug_attrs(struct device *dev,\r
+ struct device_attribute *attr,\r
+ char *buf) \r
+{ \r
+ return sprintf(buf, "%d\n", debug_en);\r
+}\r
+static ssize_t hdmi_restore_debug_attrs(struct device *dev, \r
+ struct device_attribute *attr,\r
+ const char *buf, size_t size)\r
+{\r
+ int tmp;\r
+ \r
+ sscanf(buf, "%d", &tmp);\r
+ \r
+ if(tmp != 0 && tmp != 1)\r
+ dev_err(dev, "hdmi_restore_debug_attrs err\n");\r
+ else\r
+ debug_en = tmp;\r
+ return size;\r
+}\r
+static ssize_t hdmi_restore_init_attrs(struct device *dev, \r
+ struct device_attribute *attr,\r
+ const char *buf, size_t size)\r
+{\r
+ int enable = HDMI_DISABLE, scale = 100, resolution = HDMI_DEFAULT_RESOLUTION;\r
+ struct hdmi *hdmi = dev_get_drvdata(dev);\r
+\r
+ sscanf(buf, "%d %d %d\n", &enable, &scale, &resolution);\r
+ \r
+ hdmi_dbg(dev, "hdmi init, set param: enable = %d, scale = %d, resolution = %d\n",\r
+ enable, scale, resolution);\r
+\r
+ hdmi->display_on = enable;\r
+ hdmi->resolution = resolution;\r
+ hdmi->scale_set = scale;\r
+ \r
+ if(hdmi->ops->hdmi_precent(hdmi) && hdmi->display_on)\r
+ hdmi->scale = scale;\r
+\r
+ if(hdmi->ops->init)\r
+ hdmi->ops->init(hdmi);\r
+ return size;\r
+}\r
+static struct device_attribute hdmi_attrs[] = {\r
+ __ATTR(state, 0777, hdmi_show_state_attrs, hdmi_restore_state_attrs),\r
+ __ATTR(enable, 0777, hdmi_show_switch_attrs, hdmi_restore_switch_attrs),\r
+ __ATTR(debug, 0777, hdmi_show_debug_attrs, hdmi_restore_debug_attrs),\r
+ __ATTR(init, 0777, NULL, hdmi_restore_init_attrs),\r
+};\r
+\r
+int hdmi_create_attrs(struct hdmi *hdmi)\r
+{\r
+ int rc = 0;\r
+ int i;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(hdmi_attrs); i++) {\r
+ rc = device_create_file(hdmi->dev, &hdmi_attrs[i]);\r
+ if (rc)\r
+ goto create_failed;\r
+ }\r
+\r
+ goto succeed;\r
+\r
+create_failed:\r
+ while (i--)\r
+ device_remove_file(hdmi->dev, &hdmi_attrs[i]);\r
+succeed:\r
+ return rc;\r
+}\r
+\r
+void hdmi_remove_attrs(struct hdmi *hdmi)\r
+{\r
+ int i;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(hdmi_attrs); i++)\r
+ device_remove_file(hdmi->dev, &hdmi_attrs[i]);\r
+}\r
+\r
+\r
return 0;
}
#endif
-
+#ifdef CONFIG_FB_SCALING_OSD
+static int hdmi_get_fbscale(void)
+{
+#ifdef CONFIG_HDMI
+ return hdmi_get_scale();
+#else
+ return 100;
+#endif
+}
+#endif
+static void hdmi_set_fbscale(struct fb_info *info)
+{
+#ifdef CONFIG_HDMI
+ struct rk29fb_inf *inf = dev_get_drvdata(info->device);
+ struct rk29fb_screen *screen = inf->cur_screen;
+ struct win0_par *par = info->par;
+ int scale;
+
+ scale = hdmi_get_scale();
+ if(scale == 100)
+ return;
+ par->xpos += screen->x_res * (100-scale) / 200;
+ par->ypos += screen->y_res * (100-scale) / 200;
+ par->xsize = par->xsize *scale /100;
+ par->ysize = par->ysize *scale /100;
+#endif
+}
static int win0_blank(int blank_mode, struct fb_info *info)
{
struct rk29fb_inf *inf = dev_get_drvdata(info->device);
struct fb_var_screeninfo *var = &info->var;
struct fb_fix_screeninfo *fix = &info->fix;
struct win0_par *par = info->par;
-
- u32 xact = var->xres; /* visible resolution */
- u32 yact = var->yres;
- u32 xvir = var->xres_virtual; /* virtual resolution */
- u32 yvir = var->yres_virtual;
+ u32 xact, yact, xvir, yvir, xpos, ypos, ScaleYrgbX,ScaleYrgbY, ScaleCbrX, ScaleCbrY, y_addr,uv_addr;
+ hdmi_set_fbscale(info);
+ xact = var->xres; /* visible resolution */
+ yact = var->yres;
+ xvir = var->xres_virtual; /* virtual resolution */
+ yvir = var->yres_virtual;
//u32 xact_st = var->xoffset; /* offset from virtual to visible */
//u32 yact_st = var->yoffset; /* resolution */
- u32 xpos = par->xpos;
- u32 ypos = par->ypos;
+ xpos = par->xpos;
+ ypos = par->ypos;
- u32 ScaleYrgbX=0x1000,ScaleYrgbY=0x1000;
- u32 ScaleCbrX=0x1000, ScaleCbrY=0x1000;
+ ScaleYrgbX=0x1000;
+ ScaleYrgbY=0x1000;
+ ScaleCbrX=0x1000;
+ ScaleCbrY=0x1000;
- u32 y_addr = 0; //user alloc buf addr y
- u32 uv_addr = 0;
+ y_addr = 0; //user alloc buf addr y
+ uv_addr = 0;
fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__);
struct rk29fb_screen *screen = inf->cur_screen;
struct win0_par *par = info->par;
struct fb_var_screeninfo *var = &info->var;
-
+ u32 addr;
+ u16 xres_virtual,xpos,ypos;
+ u8 trspval,trspmode;
+ if(((screen->x_res != var->xres) || (screen->y_res != var->yres))
+ && !((screen->x_res>1280) && (var->bits_per_pixel == 32)))
+ {
+ hdmi_set_fbscale(info);
+ }else if(((screen->x_res==1920) ))
+ {
+ if(hdmi_get_scale() < 100)
+ par->ypos -=screen->y_res * (100-hdmi_get_scale()) / 200;
+ }
//u32 offset=0, addr=0, map_size=0, smem_len=0;
- u32 addr=0;
- u16 xres_virtual = 0; //virtual screen size
+ addr=0;
+ xres_virtual = 0; //virtual screen size
//u16 xpos_virtual = var->xoffset; //visiable offset in virtual screen
//u16 ypos_virtual = var->yoffset;
- u16 xpos = par->xpos; //visiable offset in panel
- u16 ypos = par->ypos;
+ xpos = par->xpos; //visiable offset in panel
+ ypos = par->ypos;
- u8 trspmode = TRSP_CLOSE;
- u8 trspval = 0;
+ trspmode = TRSP_CLOSE;
+ trspval = 0;
//fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__);
if(((screen->x_res != var->xres) || (screen->y_res != var->yres))
&& !((screen->x_res>1280) && (var->bits_per_pixel == 32)))
{
- addr = fix->mmio_start + par->y_offset;
- xres_virtual = screen->x_res; //virtual screen size
+ addr = fix->mmio_start + par->y_offset* hdmi_get_fbscale()/100;
+ xres_virtual = screen->x_res* hdmi_get_fbscale()/100; //virtual screen size
}
else
#endif
if(((screen->x_res != var->xres) || (screen->y_res != var->yres))
&& !((screen->x_res>1280) && (var->bits_per_pixel == 32)))
{
- addr = fix1->mmio_start + par->y_offset;
+ addr = fix1->mmio_start + par->y_offset* hdmi_get_fbscale()/100;
}
else
#endif
ipp_req.src0.w = var->xres;
ipp_req.src0.h = var->yres;
- ipp_req.dst0.YrgbMst = fix->mmio_start + dstoffset;
- ipp_req.dst0.w = screen->x_res;
- ipp_req.dst0.h = screen->y_res;
+ ipp_req.dst0.YrgbMst = fix->mmio_start + dstoffset* hdmi_get_fbscale()/100;
+ ipp_req.dst0.w = screen->x_res* hdmi_get_fbscale()/100;
+ ipp_req.dst0.h = screen->y_res* hdmi_get_fbscale()/100;
ipp_req.src_vir_w = ipp_req.src0.w;
ipp_req.dst_vir_w = ipp_req.dst0.w;
#ifdef CONFIG_FB_SCALING_OSD
struct fb_fix_screeninfo *fix = &info->fix;
struct rk29_ipp_req ipp_req;
- u32 dstoffset = 0
+ u32 dstoffset = 0;
#endif
//fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__);
ipp_req.src0.w = var->xres;
ipp_req.src0.h = var->yres;
- ipp_req.dst0.YrgbMst = fix->mmio_start + dstoffset;
- ipp_req.dst0.w = screen->x_res;
- ipp_req.dst0.h = screen->y_res;
+ ipp_req.dst0.YrgbMst = fix->mmio_start + dstoffset* hdmi_get_fbscale()/100;
+ ipp_req.dst0.w = screen->x_res* hdmi_get_fbscale()/100;
+ ipp_req.dst0.h = screen->y_res* hdmi_get_fbscale()/100;
ipp_req.src_vir_w = ipp_req.src0.w;
ipp_req.dst_vir_w = ipp_req.dst0.w;
u16 xlcd = screen->x_res; //size of panel
u16 ylcd = screen->y_res;
u16 yres = 0;
-#ifdef CONFIG_HDMI
+#if 0
struct hdmi *hdmi = get_hdmi_struct(0);
#endif
{
return -EINVAL; // multiple of scale down or scale up can't exceed 8
}
-#ifdef CONFIG_HDMI
+#if 0
if(inf->video_mode == 1) {
if(hdmi_resolution_changed(hdmi,var->xres,var->yres, 1) == 1)
{
//.fb_cursor = rk29_set_cursor,
};
+int fb_get_video_mode(void)
+{
+ struct rk29fb_inf *inf;
+ if(!g_pdev)
+ return 0;
+ inf = platform_get_drvdata(g_pdev);
+ return inf->video_mode;
+}
/*
enable: 1, switch to tv or hdmi; 0, switch to lcd
*/
+++ /dev/null
-/* include/linux/hdmi.h\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License version 2 as\r
- * published by the Free Software Foundation.\r
- *\r
-*/\r
-\r
-#ifndef __LINUX_HDMI_CORE_H\r
-#define __LINUX_HDMI_CORE_H\r
-\r
-#include <linux/device.h>\r
-#include <linux/workqueue.h>\r
-#include <linux/i2c.h>\r
-#include <linux/completion.h>\r
-#include <linux/wakelock.h>\r
-\r
-\r
-#ifdef CONFIG_HDMI_DEBUG\r
-#define hdmi_dbg(dev, format, arg...) \\r
- dev_printk(KERN_INFO , dev , format , ## arg)\r
-#else\r
-#define hdmi_dbg(dev, format, arg...) \r
-#endif\r
-\r
-\r
-\r
-typedef int BOOL;\r
-\r
-#define TRUE 1\r
-#define FALSE 0\r
-#define HDMI_DISABLE 0\r
-#define HDMI_ENABLE 1\r
-/* resolution */\r
-#define HDMI_1280x720p_50Hz 0\r
-#define HDMI_1280x720p_60Hz 1\r
-#define HDMI_720x576p_50Hz_4x3 2\r
-#define HDMI_720x576p_50Hz_16x9 3\r
-#define HDMI_720x480p_60Hz_4x3 4\r
-#define HDMI_720x480p_60Hz_16x9 5\r
-#define HDMI_1920x1080p_50Hz 6\r
-#define HDMI_1920x1080p_60Hz 7\r
-\r
-/* HDMI default resolution */\r
-#define HDMI_DEFAULT_RESOLUTION HDMI_1280x720p_50Hz\r
-/* I2S Fs */\r
-#define HDMI_I2S_Fs_44100 0\r
-#define HDMI_I2S_Fs_48000 2\r
-/* I2S default sample rate */\r
-#define HDMI_I2S_DEFAULT_Fs HDMI_I2S_Fs_44100\r
-\r
-\r
-#define HDMI_MAX_ID 32\r
-struct hdmi;\r
-struct hdmi_ops{\r
- int (*display_on)(struct hdmi *);\r
- int (*display_off)(struct hdmi *);\r
- int (*set_param)(struct hdmi *);\r
- int (*hdmi_precent)(struct hdmi *);\r
- int (*insert)(struct hdmi *);\r
- int (*remove)(struct hdmi *);\r
- int (*power_off)(struct hdmi *);\r
- int (*shutdown)(struct hdmi *);\r
-};\r
-struct hdmi {\r
- int id;\r
- int wait;\r
- BOOL display_on;\r
- BOOL plug;\r
- BOOL auto_switch;\r
- BOOL hdcp_on;\r
- BOOL param_conf;\r
-\r
- u8 resolution;\r
- u8 audio_fs;\r
-\r
- int hdmi_stay_awake;\r
-\r
- struct device *dev;\r
- struct delayed_work changed_work;\r
- struct completion complete;\r
- const struct hdmi_ops *ops;\r
-\r
- unsigned long priv[0] ____cacheline_aligned;\r
-};\r
-extern int hdmi_is_insert(void);\r
-extern void *hdmi_priv(struct hdmi *hdmi);\r
-extern struct hdmi *hdmi_register(int extra, struct device *parent);\r
-extern void hdmi_unregister(struct hdmi *hdmi);\r
-extern void hdmi_changed(struct hdmi *hdmi, int msec);\r
-extern int hdmi_suspend(struct hdmi *hdmi);\r
-extern int hdmi_resume(struct hdmi *hdmi);\r
-\r
-extern int hdmi_codec_set_audio_fs(unsigned char audio_fs);\r
-extern int hdmi_fb_set_resolution(unsigned char resolution);\r
-\r
-extern int hdmi_switch_fb(struct hdmi *hdmi, int type);\r
-extern int hdmi_resolution_changed(struct hdmi *hdmi, int xres, int yres, int video_on);\r
-\r
-extern struct hdmi *get_hdmi_struct(int nr);\r
-\r
-extern int hdmi_get_default_resolution(void *screen);\r
-extern void hdmi_set_spk(int on);\r
-extern void hdmi_set_backlight(int on);\r
-\r
-#endif\r
#include <linux/workqueue.h>\r
#include <linux/i2c.h>\r
#include <linux/completion.h>\r
+#include <linux/wakelock.h>\r
\r
+extern int debug_en;\r
\r
-#ifdef CONFIG_HDMI_DEBUG\r
#define hdmi_dbg(dev, format, arg...) \\r
- dev_printk(KERN_INFO , dev , format , ## arg)\r
-#else\r
-#define hdmi_dbg(dev, format, arg...) \r
-#endif\r
+do{\\r
+ if(debug_en == 1) \\r
+ dev_printk(KERN_INFO , dev , format , ## arg);\\r
+}while(0)\r
\r
\r
\r
\r
#define TRUE 1\r
#define FALSE 0\r
+#define HDMI_DISABLE 0\r
+#define HDMI_ENABLE 1\r
+\r
+#define MIN_SCALE 80\r
+/* mouse event */\r
+#define MOUSE_NONE 0x00\r
+#define MOUSE_LEFT_PRESS 0x01\r
+#define MOUSE_RIGHT_PRESS 0x02\r
+#define MOUSE_MIDDLE_PRESS 0x04\r
+#define HDMI_MOUSE_EVENT MOUSE_NONE \r
+/* mode */\r
+#define DISP_ON_LCD 0\r
+#define DISP_ON_HDMI 1\r
+#define DISP_ON_LCD_AND_HDMI 2\r
+/* dual display */\r
+#ifdef CONFIG_HDMI_DUAL_DISP\r
+#define DUAL_DISP_CAP HDMI_ENABLE \r
+#define HDMI_DEFAULT_MODE DISP_ON_LCD_AND_HDMI\r
+#else\r
+#define DUAL_DISP_CAP HDMI_DISABLE \r
+#define HDMI_DEFAULT_MODE DISP_ON_HDMI\r
+#endif\r
/* resolution */\r
-#define HDMI_1280x720p_50Hz 0\r
-#define HDMI_1280x720p_60Hz 1\r
-#define HDMI_720x576p_50Hz 2\r
-#define HDMI_1920x1080p_50Hz 3\r
+#define HDMI_1920x1080p_50Hz 0\r
+#define HDMI_1920x1080p_60Hz 1\r
+#define HDMI_1280x720p_50Hz 2\r
+#define HDMI_1280x720p_60Hz 3\r
+#define HDMI_720x576p_50Hz_4x3 4\r
+#define HDMI_720x576p_50Hz_16x9 5\r
+#define HDMI_720x480p_60Hz_4x3 6\r
+#define HDMI_720x480p_60Hz_16x9 7\r
+\r
/* HDMI default resolution */\r
-#define HDMI_DEFAULT_RESOLUTION HDMI_1280x720p_50Hz\r
+#define HDMI_DEFAULT_RESOLUTION HDMI_1920x1080p_50Hz\r
/* I2S Fs */\r
#define HDMI_I2S_Fs_44100 0\r
#define HDMI_I2S_Fs_48000 2\r
\r
\r
#define HDMI_MAX_ID 32\r
-\r
-\r
+struct hdmi;\r
+struct hdmi_ops{\r
+ int (*set_param)(struct hdmi *);\r
+ int (*hdmi_precent)(struct hdmi *);\r
+ int (*insert)(struct hdmi *);\r
+ int (*remove)(struct hdmi *);\r
+ int (*init)(struct hdmi*);\r
+};\r
struct hdmi {\r
- struct device *dev;\r
- struct work_struct changed_work;\r
int id;\r
int wait;\r
BOOL display_on;\r
BOOL plug;\r
- BOOL auto_switch;\r
BOOL hdcp_on;\r
BOOL param_conf;\r
\r
u8 resolution;\r
+ u8 scale;\r
+ u8 scale_set;\r
u8 audio_fs;\r
-\r
- void *priv;\r
-\r
+ int mode;\r
+ int dual_disp;\r
+ struct timer_list timer;\r
+ struct mutex lock;\r
+ struct device *dev;\r
+ struct delayed_work work;\r
struct completion complete;\r
+ const struct hdmi_ops *ops;\r
\r
- int (*hdmi_display_on)(struct hdmi *);\r
- int (*hdmi_display_off)(struct hdmi *);\r
- int (*hdmi_set_param)(struct hdmi *);\r
- int (*hdmi_core_init)(struct hdmi *);\r
+ unsigned long priv[0] ____cacheline_aligned;\r
};\r
-\r
-extern void *hdmi_get_privdata(struct hdmi *hdmi);\r
-extern void hdmi_set_privdata(struct hdmi *hdmi, void *data);\r
-extern int hdmi_register(struct device *parent, struct hdmi *hdmi);\r
+extern int hdmi_is_insert(void);\r
+extern void *hdmi_priv(struct hdmi *hdmi);\r
+extern struct hdmi *hdmi_register(int extra, struct device *parent);\r
extern void hdmi_unregister(struct hdmi *hdmi);\r
-extern void hdmi_changed(struct hdmi *hdmi, int plug);\r
-\r
-extern int hdmi_codec_set_audio_fs(unsigned char audio_fs);\r
-extern int hdmi_fb_set_resolution(unsigned char resolution);\r
+extern void hdmi_changed(struct hdmi *hdmi, int msec);\r
\r
extern int hdmi_switch_fb(struct hdmi *hdmi, int type);\r
-extern int hdmi_resolution_changed(struct hdmi *hdmi, int xres, int yres, int video_on);\r
-\r
+extern void hdmi_suspend(struct hdmi *hdmi);\r
+extern void hdmi_resume(struct hdmi *hdmi);\r
extern struct hdmi *get_hdmi_struct(int nr);\r
\r
-extern int hdmi_get_default_resolution(void *screen);\r
-\r
+extern void hdmi_set_spk(int on);\r
+extern void hdmi_set_backlight(int on);\r
+extern int hdmi_get_scale(void);\r
+extern int hdmi_set_scale(int event, char *data, int len);\r
+extern int fb_get_video_mode(void);\r
+extern int display_on_hdmi(void);\r
#endif\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff