davinci: Move interrupt ctlr info to SoC infrastructure

Use the SoC infrastructure to hold the interrupt controller
information (i.e., base address, default priorities,
interrupt controller type, and the number of IRQs).

The interrupt controller base, although initially put
in the soc_info structure's intc_base field, is eventually
put in the global 'davinci_intc_base' so the low-level
interrupt code can access it without a dereference.

These changes enable the SoC default irq priorities to be
put in the SoC-specific files, and the interrupt controller
to be at any base address.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 2e5b888e6ca66b652dc0624e2265ae1c360a7428..d72d517d090cdfce10e9430ed997dc78e83ed1c5 100644 (file)
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -22,6 +22,8 @@
 struct davinci_soc_info davinci_soc_info;
 EXPORT_SYMBOL(davinci_soc_info);
 
+void __iomem *davinci_intc_base;
+
 static struct davinci_id * __init davinci_get_id(u32 jtag_id)
 {
        int i;
@@ -84,6 +86,7 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
                        goto err;
        }
 
+       davinci_intc_base = davinci_soc_info.intc_base;
        return;
 
 err:

diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f735ed9d2d10913231da45f8ed9c3f2ac5131597..e8c01ffe818a021cd2c4b30379d9a107c56075ea 100644 (file)
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -470,6 +470,71 @@ EVT_CFG(DM355,  EVT26_MMC0_RX,           2,    1,    0,     false)
 #endif
 };
 
+static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+       [IRQ_DM355_CCDC_VDINT0]         = 2,
+       [IRQ_DM355_CCDC_VDINT1]         = 6,
+       [IRQ_DM355_CCDC_VDINT2]         = 6,
+       [IRQ_DM355_IPIPE_HST]           = 6,
+       [IRQ_DM355_H3AINT]              = 6,
+       [IRQ_DM355_IPIPE_SDR]           = 6,
+       [IRQ_DM355_IPIPEIFINT]          = 6,
+       [IRQ_DM355_OSDINT]              = 7,
+       [IRQ_DM355_VENCINT]             = 6,
+       [IRQ_ASQINT]                    = 6,
+       [IRQ_IMXINT]                    = 6,
+       [IRQ_USBINT]                    = 4,
+       [IRQ_DM355_RTOINT]              = 4,
+       [IRQ_DM355_UARTINT2]            = 7,
+       [IRQ_DM355_TINT6]               = 7,
+       [IRQ_CCINT0]                    = 5,    /* dma */
+       [IRQ_CCERRINT]                  = 5,    /* dma */
+       [IRQ_TCERRINT0]                 = 5,    /* dma */
+       [IRQ_TCERRINT]                  = 5,    /* dma */
+       [IRQ_DM355_SPINT2_1]            = 7,
+       [IRQ_DM355_TINT7]               = 4,
+       [IRQ_DM355_SDIOINT0]            = 7,
+       [IRQ_MBXINT]                    = 7,
+       [IRQ_MBRINT]                    = 7,
+       [IRQ_MMCINT]                    = 7,
+       [IRQ_DM355_MMCINT1]             = 7,
+       [IRQ_DM355_PWMINT3]             = 7,
+       [IRQ_DDRINT]                    = 7,
+       [IRQ_AEMIFINT]                  = 7,
+       [IRQ_DM355_SDIOINT1]            = 4,
+       [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
+       [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
+       [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
+       [IRQ_TINT1_TINT34]              = 7,    /* system tick */
+       [IRQ_PWMINT0]                   = 7,
+       [IRQ_PWMINT1]                   = 7,
+       [IRQ_PWMINT2]                   = 7,
+       [IRQ_I2C]                       = 3,
+       [IRQ_UARTINT0]                  = 3,
+       [IRQ_UARTINT1]                  = 3,
+       [IRQ_DM355_SPINT0_0]            = 3,
+       [IRQ_DM355_SPINT0_1]            = 3,
+       [IRQ_DM355_GPIO0]               = 3,
+       [IRQ_DM355_GPIO1]               = 7,
+       [IRQ_DM355_GPIO2]               = 4,
+       [IRQ_DM355_GPIO3]               = 4,
+       [IRQ_DM355_GPIO4]               = 7,
+       [IRQ_DM355_GPIO5]               = 7,
+       [IRQ_DM355_GPIO6]               = 7,
+       [IRQ_DM355_GPIO7]               = 7,
+       [IRQ_DM355_GPIO8]               = 7,
+       [IRQ_DM355_GPIO9]               = 7,
+       [IRQ_DM355_GPIOBNK0]            = 7,
+       [IRQ_DM355_GPIOBNK1]            = 7,
+       [IRQ_DM355_GPIOBNK2]            = 7,
+       [IRQ_DM355_GPIOBNK3]            = 7,
+       [IRQ_DM355_GPIOBNK4]            = 7,
+       [IRQ_DM355_GPIOBNK5]            = 7,
+       [IRQ_DM355_GPIOBNK6]            = 7,
+       [IRQ_COMMTX]                    = 7,
+       [IRQ_COMMRX]                    = 7,
+       [IRQ_EMUINT]                    = 7,
+};
+
 /*----------------------------------------------------------------------*/
 
 static const s8 dma_chan_dm355_no_event[] = {
@@ -563,6 +628,10 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
        .pinmux_pins            = dm355_pins,
        .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
+       .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+       .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+       .intc_irq_prios         = dm355_default_priorities,
+       .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 };
 
 void __init dm355_init(void)

diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index b7c17dd6795bbe722e341317ffbb36010e2fd51d..5c6a7b175786c7668f8d39f10060df4abc914514 100644 (file)
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -390,6 +390,74 @@ MUX_CFG(DM644X, LFLDEN,            0,   25,    1,    1,     false)
 #endif
 };
 
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+       [IRQ_VDINT0]            = 2,
+       [IRQ_VDINT1]            = 6,
+       [IRQ_VDINT2]            = 6,
+       [IRQ_HISTINT]           = 6,
+       [IRQ_H3AINT]            = 6,
+       [IRQ_PRVUINT]           = 6,
+       [IRQ_RSZINT]            = 6,
+       [7]                     = 7,
+       [IRQ_VENCINT]           = 6,
+       [IRQ_ASQINT]            = 6,
+       [IRQ_IMXINT]            = 6,
+       [IRQ_VLCDINT]           = 6,
+       [IRQ_USBINT]            = 4,
+       [IRQ_EMACINT]           = 4,
+       [14]                    = 7,
+       [15]                    = 7,
+       [IRQ_CCINT0]            = 5,    /* dma */
+       [IRQ_CCERRINT]          = 5,    /* dma */
+       [IRQ_TCERRINT0]         = 5,    /* dma */
+       [IRQ_TCERRINT]          = 5,    /* dma */
+       [IRQ_PSCIN]             = 7,
+       [21]                    = 7,
+       [IRQ_IDE]               = 4,
+       [23]                    = 7,
+       [IRQ_MBXINT]            = 7,
+       [IRQ_MBRINT]            = 7,
+       [IRQ_MMCINT]            = 7,
+       [IRQ_SDIOINT]           = 7,
+       [28]                    = 7,
+       [IRQ_DDRINT]            = 7,
+       [IRQ_AEMIFINT]          = 7,
+       [IRQ_VLQINT]            = 4,
+       [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
+       [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
+       [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
+       [IRQ_TINT1_TINT34]      = 7,    /* system tick */
+       [IRQ_PWMINT0]           = 7,
+       [IRQ_PWMINT1]           = 7,
+       [IRQ_PWMINT2]           = 7,
+       [IRQ_I2C]               = 3,
+       [IRQ_UARTINT0]          = 3,
+       [IRQ_UARTINT1]          = 3,
+       [IRQ_UARTINT2]          = 3,
+       [IRQ_SPINT0]            = 3,
+       [IRQ_SPINT1]            = 3,
+       [45]                    = 7,
+       [IRQ_DSP2ARM0]          = 4,
+       [IRQ_DSP2ARM1]          = 4,
+       [IRQ_GPIO0]             = 7,
+       [IRQ_GPIO1]             = 7,
+       [IRQ_GPIO2]             = 7,
+       [IRQ_GPIO3]             = 7,
+       [IRQ_GPIO4]             = 7,
+       [IRQ_GPIO5]             = 7,
+       [IRQ_GPIO6]             = 7,
+       [IRQ_GPIO7]             = 7,
+       [IRQ_GPIOBNK0]          = 7,
+       [IRQ_GPIOBNK1]          = 7,
+       [IRQ_GPIOBNK2]          = 7,
+       [IRQ_GPIOBNK3]          = 7,
+       [IRQ_GPIOBNK4]          = 7,
+       [IRQ_COMMTX]            = 7,
+       [IRQ_COMMRX]            = 7,
+       [IRQ_EMUINT]            = 7,
+};
+
 /*----------------------------------------------------------------------*/
 
 static const s8 dma_chan_dm644x_no_event[] = {
@@ -503,6 +571,10 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
        .pinmux_pins            = dm644x_pins,
        .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
+       .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+       .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+       .intc_irq_prios         = dm644x_default_priorities,
+       .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 };
 
 void __init dm644x_init(void)

diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 299d8d9d26e0af55f933808b807a088d3cdc62a3..beb522e8a1a501c647447ef94d47cfedf003b88d 100644 (file)
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -358,6 +358,73 @@ MUX_CFG(DM646X, PTSIMUX_SERIAL,            0,   16,    3,    3,     true)
 #endif
 };
 
+static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+       [IRQ_DM646X_VP_VERTINT0]        = 7,
+       [IRQ_DM646X_VP_VERTINT1]        = 7,
+       [IRQ_DM646X_VP_VERTINT2]        = 7,
+       [IRQ_DM646X_VP_VERTINT3]        = 7,
+       [IRQ_DM646X_VP_ERRINT]          = 7,
+       [IRQ_DM646X_RESERVED_1]         = 7,
+       [IRQ_DM646X_RESERVED_2]         = 7,
+       [IRQ_DM646X_WDINT]              = 7,
+       [IRQ_DM646X_CRGENINT0]          = 7,
+       [IRQ_DM646X_CRGENINT1]          = 7,
+       [IRQ_DM646X_TSIFINT0]           = 7,
+       [IRQ_DM646X_TSIFINT1]           = 7,
+       [IRQ_DM646X_VDCEINT]            = 7,
+       [IRQ_DM646X_USBINT]             = 7,
+       [IRQ_DM646X_USBDMAINT]          = 7,
+       [IRQ_DM646X_PCIINT]             = 7,
+       [IRQ_CCINT0]                    = 7,    /* dma */
+       [IRQ_CCERRINT]                  = 7,    /* dma */
+       [IRQ_TCERRINT0]                 = 7,    /* dma */
+       [IRQ_TCERRINT]                  = 7,    /* dma */
+       [IRQ_DM646X_TCERRINT2]          = 7,
+       [IRQ_DM646X_TCERRINT3]          = 7,
+       [IRQ_DM646X_IDE]                = 7,
+       [IRQ_DM646X_HPIINT]             = 7,
+       [IRQ_DM646X_EMACRXTHINT]        = 7,
+       [IRQ_DM646X_EMACRXINT]          = 7,
+       [IRQ_DM646X_EMACTXINT]          = 7,
+       [IRQ_DM646X_EMACMISCINT]        = 7,
+       [IRQ_DM646X_MCASP0TXINT]        = 7,
+       [IRQ_DM646X_MCASP0RXINT]        = 7,
+       [IRQ_AEMIFINT]                  = 7,
+       [IRQ_DM646X_RESERVED_3]         = 7,
+       [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
+       [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
+       [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
+       [IRQ_TINT1_TINT34]              = 7,    /* system tick */
+       [IRQ_PWMINT0]                   = 7,
+       [IRQ_PWMINT1]                   = 7,
+       [IRQ_DM646X_VLQINT]             = 7,
+       [IRQ_I2C]                       = 7,
+       [IRQ_UARTINT0]                  = 7,
+       [IRQ_UARTINT1]                  = 7,
+       [IRQ_DM646X_UARTINT2]           = 7,
+       [IRQ_DM646X_SPINT0]             = 7,
+       [IRQ_DM646X_SPINT1]             = 7,
+       [IRQ_DM646X_DSP2ARMINT]         = 7,
+       [IRQ_DM646X_RESERVED_4]         = 7,
+       [IRQ_DM646X_PSCINT]             = 7,
+       [IRQ_DM646X_GPIO0]              = 7,
+       [IRQ_DM646X_GPIO1]              = 7,
+       [IRQ_DM646X_GPIO2]              = 7,
+       [IRQ_DM646X_GPIO3]              = 7,
+       [IRQ_DM646X_GPIO4]              = 7,
+       [IRQ_DM646X_GPIO5]              = 7,
+       [IRQ_DM646X_GPIO6]              = 7,
+       [IRQ_DM646X_GPIO7]              = 7,
+       [IRQ_DM646X_GPIOBNK0]           = 7,
+       [IRQ_DM646X_GPIOBNK1]           = 7,
+       [IRQ_DM646X_GPIOBNK2]           = 7,
+       [IRQ_DM646X_DDRINT]             = 7,
+       [IRQ_DM646X_AEMIFINT]           = 7,
+       [IRQ_COMMTX]                    = 7,
+       [IRQ_COMMRX]                    = 7,
+       [IRQ_EMUINT]                    = 7,
+};
+
 /*----------------------------------------------------------------------*/
 
 static const s8 dma_chan_dm646x_no_event[] = {
@@ -483,6 +550,10 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
        .pinmux_pins            = dm646x_pins,
        .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
+       .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+       .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+       .intc_irq_prios         = dm646x_default_priorities,
+       .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 };
 
 void __init dm646x_init(void)

diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index c00d375946d1a06b66aeed3b4a1d1ea40db2eefa..838ae13595a4e0b6ccc5f29fb88b50a5b16a47f5 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,6 +17,7 @@ struct sys_timer;
 extern struct sys_timer davinci_timer;
 
 extern void davinci_irq_init(void);
+extern void __iomem *davinci_intc_base;
 
 /* parameters describe VBUS sourcing for host mode */
 extern void setup_usb(unsigned mA, unsigned potpgt_msec);
@@ -39,6 +40,10 @@ struct davinci_soc_info {
        void __iomem                    *pinmux_base;
        const struct mux_config         *pinmux_pins;
        unsigned long                   pinmux_pins_num;
+       void __iomem                    *intc_base;
+       int                             intc_type;
+       u8                              *intc_irq_prios;
+       unsigned long                   intc_irq_num;
 };
 
 extern struct davinci_soc_info davinci_soc_info;

diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 0ebb445450500a290ac89c1ed21616a5cd430513..ed78851fe4aee13186008ac19d0eb10c27f13f22 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -15,7 +15,8 @@
                .endm
 
                .macro  get_irqnr_preamble, base, tmp
-               ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
+               ldr \base, =davinci_intc_base
+               ldr \base, [\base]
                .endm
 
                .macro  arch_ret_to_user, tmp1, tmp2

diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 18066074c9959a5498f88d9313a913c2089b42ac..bc5d6aaa69a3ed86e52c4aa55742ac6b8747d06e 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -30,6 +30,9 @@
 /* Base address */
 #define DAVINCI_ARM_INTC_BASE 0x01C48000
 
+#define DAVINCI_INTC_TYPE_AINTC                0
+#define DAVINCI_INTC_TYPE_CP_INTC      1
+
 /* Interrupt lines */
 #define IRQ_VDINT0       0
 #define IRQ_VDINT1       1

diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5a324c90e291f4c0ce88d4fef865654d4ab51498..af92ffee84714067f3e4ef543762ec758bf98a52 100644 (file)
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -26,6 +26,7 @@
 
 #include <mach/hardware.h>
 #include <mach/cputype.h>
+#include <mach/common.h>
 #include <asm/mach/irq.h>
 
 #define IRQ_BIT(irq)           ((irq) & 0x1f)
@@ -41,18 +42,14 @@
 #define IRQ_INTPRI0_REG_OFFSET 0x0030
 #define IRQ_INTPRI7_REG_OFFSET 0x004C
 
-const u8 *davinci_def_priorities;
-
-#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
-
 static inline unsigned int davinci_irq_readl(int offset)
 {
-       return __raw_readl(INTC_BASE + offset);
+       return __raw_readl(davinci_intc_base + offset);
 }
 
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-       __raw_writel(value, INTC_BASE + offset);
+       __raw_writel(value, davinci_intc_base + offset);
 }
 
 /* Disable interrupt */
@@ -113,217 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
        .unmask = davinci_unmask_irq,
 };
 
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
-       [IRQ_VDINT0]            = 2,
-       [IRQ_VDINT1]            = 6,
-       [IRQ_VDINT2]            = 6,
-       [IRQ_HISTINT]           = 6,
-       [IRQ_H3AINT]            = 6,
-       [IRQ_PRVUINT]           = 6,
-       [IRQ_RSZINT]            = 6,
-       [7]                     = 7,
-       [IRQ_VENCINT]           = 6,
-       [IRQ_ASQINT]            = 6,
-       [IRQ_IMXINT]            = 6,
-       [IRQ_VLCDINT]           = 6,
-       [IRQ_USBINT]            = 4,
-       [IRQ_EMACINT]           = 4,
-       [14]                    = 7,
-       [15]                    = 7,
-       [IRQ_CCINT0]            = 5,    /* dma */
-       [IRQ_CCERRINT]          = 5,    /* dma */
-       [IRQ_TCERRINT0]         = 5,    /* dma */
-       [IRQ_TCERRINT]          = 5,    /* dma */
-       [IRQ_PSCIN]             = 7,
-       [21]                    = 7,
-       [IRQ_IDE]               = 4,
-       [23]                    = 7,
-       [IRQ_MBXINT]            = 7,
-       [IRQ_MBRINT]            = 7,
-       [IRQ_MMCINT]            = 7,
-       [IRQ_SDIOINT]           = 7,
-       [28]                    = 7,
-       [IRQ_DDRINT]            = 7,
-       [IRQ_AEMIFINT]          = 7,
-       [IRQ_VLQINT]            = 4,
-       [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
-       [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
-       [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
-       [IRQ_TINT1_TINT34]      = 7,    /* system tick */
-       [IRQ_PWMINT0]           = 7,
-       [IRQ_PWMINT1]           = 7,
-       [IRQ_PWMINT2]           = 7,
-       [IRQ_I2C]               = 3,
-       [IRQ_UARTINT0]          = 3,
-       [IRQ_UARTINT1]          = 3,
-       [IRQ_UARTINT2]          = 3,
-       [IRQ_SPINT0]            = 3,
-       [IRQ_SPINT1]            = 3,
-       [45]                    = 7,
-       [IRQ_DSP2ARM0]          = 4,
-       [IRQ_DSP2ARM1]          = 4,
-       [IRQ_GPIO0]             = 7,
-       [IRQ_GPIO1]             = 7,
-       [IRQ_GPIO2]             = 7,
-       [IRQ_GPIO3]             = 7,
-       [IRQ_GPIO4]             = 7,
-       [IRQ_GPIO5]             = 7,
-       [IRQ_GPIO6]             = 7,
-       [IRQ_GPIO7]             = 7,
-       [IRQ_GPIOBNK0]          = 7,
-       [IRQ_GPIOBNK1]          = 7,
-       [IRQ_GPIOBNK2]          = 7,
-       [IRQ_GPIOBNK3]          = 7,
-       [IRQ_GPIOBNK4]          = 7,
-       [IRQ_COMMTX]            = 7,
-       [IRQ_COMMRX]            = 7,
-       [IRQ_EMUINT]            = 7,
-};
-
-static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
-       [IRQ_DM646X_VP_VERTINT0]        = 7,
-       [IRQ_DM646X_VP_VERTINT1]        = 7,
-       [IRQ_DM646X_VP_VERTINT2]        = 7,
-       [IRQ_DM646X_VP_VERTINT3]        = 7,
-       [IRQ_DM646X_VP_ERRINT]          = 7,
-       [IRQ_DM646X_RESERVED_1]         = 7,
-       [IRQ_DM646X_RESERVED_2]         = 7,
-       [IRQ_DM646X_WDINT]              = 7,
-       [IRQ_DM646X_CRGENINT0]          = 7,
-       [IRQ_DM646X_CRGENINT1]          = 7,
-       [IRQ_DM646X_TSIFINT0]           = 7,
-       [IRQ_DM646X_TSIFINT1]           = 7,
-       [IRQ_DM646X_VDCEINT]            = 7,
-       [IRQ_DM646X_USBINT]             = 7,
-       [IRQ_DM646X_USBDMAINT]          = 7,
-       [IRQ_DM646X_PCIINT]             = 7,
-       [IRQ_CCINT0]                    = 7,    /* dma */
-       [IRQ_CCERRINT]                  = 7,    /* dma */
-       [IRQ_TCERRINT0]                 = 7,    /* dma */
-       [IRQ_TCERRINT]                  = 7,    /* dma */
-       [IRQ_DM646X_TCERRINT2]          = 7,
-       [IRQ_DM646X_TCERRINT3]          = 7,
-       [IRQ_DM646X_IDE]                = 7,
-       [IRQ_DM646X_HPIINT]             = 7,
-       [IRQ_DM646X_EMACRXTHINT]        = 7,
-       [IRQ_DM646X_EMACRXINT]          = 7,
-       [IRQ_DM646X_EMACTXINT]          = 7,
-       [IRQ_DM646X_EMACMISCINT]        = 7,
-       [IRQ_DM646X_MCASP0TXINT]        = 7,
-       [IRQ_DM646X_MCASP0RXINT]        = 7,
-       [IRQ_AEMIFINT]                  = 7,
-       [IRQ_DM646X_RESERVED_3]         = 7,
-       [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
-       [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
-       [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
-       [IRQ_TINT1_TINT34]              = 7,    /* system tick */
-       [IRQ_PWMINT0]                   = 7,
-       [IRQ_PWMINT1]                   = 7,
-       [IRQ_DM646X_VLQINT]             = 7,
-       [IRQ_I2C]                       = 7,
-       [IRQ_UARTINT0]                  = 7,
-       [IRQ_UARTINT1]                  = 7,
-       [IRQ_DM646X_UARTINT2]           = 7,
-       [IRQ_DM646X_SPINT0]             = 7,
-       [IRQ_DM646X_SPINT1]             = 7,
-       [IRQ_DM646X_DSP2ARMINT]         = 7,
-       [IRQ_DM646X_RESERVED_4]         = 7,
-       [IRQ_DM646X_PSCINT]             = 7,
-       [IRQ_DM646X_GPIO0]              = 7,
-       [IRQ_DM646X_GPIO1]              = 7,
-       [IRQ_DM646X_GPIO2]              = 7,
-       [IRQ_DM646X_GPIO3]              = 7,
-       [IRQ_DM646X_GPIO4]              = 7,
-       [IRQ_DM646X_GPIO5]              = 7,
-       [IRQ_DM646X_GPIO6]              = 7,
-       [IRQ_DM646X_GPIO7]              = 7,
-       [IRQ_DM646X_GPIOBNK0]           = 7,
-       [IRQ_DM646X_GPIOBNK1]           = 7,
-       [IRQ_DM646X_GPIOBNK2]           = 7,
-       [IRQ_DM646X_DDRINT]             = 7,
-       [IRQ_DM646X_AEMIFINT]           = 7,
-       [IRQ_COMMTX]                    = 7,
-       [IRQ_COMMRX]                    = 7,
-       [IRQ_EMUINT]                    = 7,
-};
-
-static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
-       [IRQ_DM355_CCDC_VDINT0]         = 2,
-       [IRQ_DM355_CCDC_VDINT1]         = 6,
-       [IRQ_DM355_CCDC_VDINT2]         = 6,
-       [IRQ_DM355_IPIPE_HST]           = 6,
-       [IRQ_DM355_H3AINT]              = 6,
-       [IRQ_DM355_IPIPE_SDR]           = 6,
-       [IRQ_DM355_IPIPEIFINT]          = 6,
-       [IRQ_DM355_OSDINT]              = 7,
-       [IRQ_DM355_VENCINT]             = 6,
-       [IRQ_ASQINT]                    = 6,
-       [IRQ_IMXINT]                    = 6,
-       [IRQ_USBINT]                    = 4,
-       [IRQ_DM355_RTOINT]              = 4,
-       [IRQ_DM355_UARTINT2]            = 7,
-       [IRQ_DM355_TINT6]               = 7,
-       [IRQ_CCINT0]                    = 5,    /* dma */
-       [IRQ_CCERRINT]                  = 5,    /* dma */
-       [IRQ_TCERRINT0]                 = 5,    /* dma */
-       [IRQ_TCERRINT]                  = 5,    /* dma */
-       [IRQ_DM355_SPINT2_1]            = 7,
-       [IRQ_DM355_TINT7]               = 4,
-       [IRQ_DM355_SDIOINT0]            = 7,
-       [IRQ_MBXINT]                    = 7,
-       [IRQ_MBRINT]                    = 7,
-       [IRQ_MMCINT]                    = 7,
-       [IRQ_DM355_MMCINT1]             = 7,
-       [IRQ_DM355_PWMINT3]             = 7,
-       [IRQ_DDRINT]                    = 7,
-       [IRQ_AEMIFINT]                  = 7,
-       [IRQ_DM355_SDIOINT1]            = 4,
-       [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
-       [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
-       [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
-       [IRQ_TINT1_TINT34]              = 7,    /* system tick */
-       [IRQ_PWMINT0]                   = 7,
-       [IRQ_PWMINT1]                   = 7,
-       [IRQ_PWMINT2]                   = 7,
-       [IRQ_I2C]                       = 3,
-       [IRQ_UARTINT0]                  = 3,
-       [IRQ_UARTINT1]                  = 3,
-       [IRQ_DM355_SPINT0_0]            = 3,
-       [IRQ_DM355_SPINT0_1]            = 3,
-       [IRQ_DM355_GPIO0]               = 3,
-       [IRQ_DM355_GPIO1]               = 7,
-       [IRQ_DM355_GPIO2]               = 4,
-       [IRQ_DM355_GPIO3]               = 4,
-       [IRQ_DM355_GPIO4]               = 7,
-       [IRQ_DM355_GPIO5]               = 7,
-       [IRQ_DM355_GPIO6]               = 7,
-       [IRQ_DM355_GPIO7]               = 7,
-       [IRQ_DM355_GPIO8]               = 7,
-       [IRQ_DM355_GPIO9]               = 7,
-       [IRQ_DM355_GPIOBNK0]            = 7,
-       [IRQ_DM355_GPIOBNK1]            = 7,
-       [IRQ_DM355_GPIOBNK2]            = 7,
-       [IRQ_DM355_GPIOBNK3]            = 7,
-       [IRQ_DM355_GPIOBNK4]            = 7,
-       [IRQ_DM355_GPIOBNK5]            = 7,
-       [IRQ_DM355_GPIOBNK6]            = 7,
-       [IRQ_COMMTX]                    = 7,
-       [IRQ_COMMRX]                    = 7,
-       [IRQ_EMUINT]                    = 7,
-};
-
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
        unsigned i;
-
-       if (cpu_is_davinci_dm644x())
-               davinci_def_priorities = dm644x_default_priorities;
-       else if (cpu_is_davinci_dm646x())
-               davinci_def_priorities = dm646x_default_priorities;
-       else if (cpu_is_davinci_dm355())
-               davinci_def_priorities = dm355_default_priorities;
+       const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 
        /* Clear all interrupt requests */
        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);