[SPARC64]: Fix _PAGE_EXEC_4U check in sun4u I-TLB miss handler.
authorDavid S. Miller <davem@sunset.davemloft.net>
Mon, 28 May 2007 03:24:47 +0000 (20:24 -0700)
committerDavid S. Miller <davem@sunset.davemloft.net>
Tue, 29 May 2007 09:50:15 +0000 (02:50 -0700)
It was using an immediate _PAGE_EXEC_4U value in an 'and'
instruction to perform the test.  This doesn't work because
the immediate field is signed 13-bit, this the mask being
tested against the PTE was 0x1000 sign-extended to 32-bits
instead of just plain 0x1000.

Signed-off-by: David S. Miller <davem@davemloft.net>
arch/sparc64/kernel/itlb_miss.S

index ad46e2024f4b7400f1c6c44176fa3a0c7c3d970f..5a8377b54955b3ff57ff82414575a237b1c0d787 100644 (file)
 /* ITLB ** ICACHE line 2: TSB compare and TLB load     */
        bne,pn  %xcc, tsb_miss_itlb             ! Miss
         mov    FAULT_CODE_ITLB, %g3
-       andcc   %g5, _PAGE_EXEC_4U, %g0         ! Executable?
+       sethi   %hi(_PAGE_EXEC_4U), %g4
+       andcc   %g5, %g4, %g0                   ! Executable?
        be,pn   %xcc, tsb_do_fault
         nop                                    ! Delay slot, fill me
        stxa    %g5, [%g0] ASI_ITLB_DATA_IN     ! Load TLB
        retry                                   ! Trap done
-       nop
 
 /* ITLB ** ICACHE line 3:                              */
        nop