#include "mipi_dsi.h"
#include "rk32_mipi_dsi.h"
#include <linux/rockchip/iomap.h>
+#include <linux/rockchip/cpu.h>
+
#endif
#ifdef CONFIG_RK32_MIPI_DSI
#define MIPI_DBG(x...) //printk(KERN_INFO x)
#endif
static int rk32_dsi_read_reg(struct dsi *dsi, u16 reg, u32 *pval)
{
- *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
+ if(cpu_is_rk3288())
+ *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
+ else if(cpu_is_rk312x()){
+ if(reg >= MIPI_DSI_HOST_OFFSET)
+ *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
+ else if(reg >= MIPI_DSI_PHY_OFFSET)
+ *pval = __raw_readl(dsi->phy.membase + (reg - MIPI_DSI_PHY_OFFSET));
+ }
return 0;
}
static int rk32_dsi_write_reg(struct dsi *dsi, u16 reg, u32 *pval)
{
- __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
+ if(cpu_is_rk3288())
+ __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
+ else if(cpu_is_rk312x()){
+ if(reg >= MIPI_DSI_HOST_OFFSET)
+ __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
+ else if(reg >= MIPI_DSI_PHY_OFFSET)
+ __raw_writel(*pval, dsi->phy.membase + (reg - MIPI_DSI_PHY_OFFSET));
+ }
return 0;
}
return 0;
}
+static void rk312x_mipi_dsi_set_hs_clk(struct dsi *dsi)
+{
+ rk32_dsi_set_bits(dsi, dsi->phy.prediv, reg_prediv);
+ rk32_dsi_set_bits(dsi, dsi->phy.fbdiv & 0xff, reg_fbdiv);
+ rk32_dsi_set_bits(dsi, (dsi->phy.fbdiv >> 8) & 0x01, reg_fbdiv_8);
+}
+
+static int rk312x_phy_power_up(struct dsi *dsi)
+{
+ //enable ref clock
+ #ifdef CONFIG_RK_3288_DSI_UBOOT
+ rk32_mipi_dsi_clk_enable(dsi);
+ #else
+ rk312x_mipi_dsi_set_hs_clk(dsi);
+ clk_prepare_enable(dsi->phy.refclk);
+ clk_prepare_enable(dsi->dsi_pclk);
+ //clk_prepare_enable(dsi->dsi_pd);
+ #endif
+ udelay(10);
+
+ rk32_dsi_set_bits(dsi, 0xe4, DPHY_REGISTER1);
+ switch(dsi->host.lane) {
+ case 4:
+ rk32_dsi_set_bits(dsi, 1, lane_en_3);
+ case 3:
+ rk32_dsi_set_bits(dsi, 1, lane_en_2);
+ case 2:
+ rk32_dsi_set_bits(dsi, 1, lane_en_1);
+ case 1:
+ rk32_dsi_set_bits(dsi, 1, lane_en_0);
+ rk32_dsi_set_bits(dsi, 1, lane_en_ck);
+ break;
+ default:
+ break;
+ }
+
+ rk32_dsi_set_bits(dsi, 0xe0, DPHY_REGISTER1);
+ udelay(10);
+
+ rk32_dsi_set_bits(dsi, 0x1e, DPHY_REGISTER20);
+ rk32_dsi_set_bits(dsi, 0x1f, DPHY_REGISTER20);
+
+ rk32_dsi_set_bits(dsi, 1, phy_enableclk);
+
+ return 0;
+}
+
+static int rk_phy_power_up(struct dsi *dsi)
+{
+ if(cpu_is_rk3288())
+ rk32_phy_power_up(dsi);
+ else if(cpu_is_rk312x())
+ rk312x_phy_power_up(dsi);
+ return 0;
+}
static int rk32_phy_power_down(struct dsi *dsi)
{
return 0;
}
+static int rk312x_phy_power_down(struct dsi *dsi)
+{
+ #ifdef CONFIG_RK_3288_DSI_UBOOT
+ rk32_mipi_dsi_clk_disable(dsi);
+ #else
+
+ rk32_dsi_set_bits(dsi, 0x01, DPHY_REGISTER0);
+ rk32_dsi_set_bits(dsi, 0xe3, DPHY_REGISTER1);
+
+ clk_disable_unprepare(dsi->phy.refclk);
+ clk_disable_unprepare(dsi->dsi_pclk);
+ // clk_disable_unprepare(dsi->dsi_pd);
+ #endif
+ return 0;
+}
+
+static int rk_phy_power_down(struct dsi *dsi)
+{
+ if(cpu_is_rk3288())
+ rk32_phy_power_down(dsi);
+ else if(cpu_is_rk312x())
+ rk312x_phy_power_down(dsi);
+ return 0;
+}
+
static int rk32_phy_init(struct dsi *dsi)
{
u32 val = 0 , ddr_clk = 0, fbdiv = 0, prediv = 0;
return 0;
}
+static int rk321x_mipi_dsi_phy_set_gotp(struct dsi *dsi, u32 offset, int n)
+{
+ u32 val = 0, temp = 0, Tlpx = 0;
+ u32 ddr_clk = dsi->phy.ddr_clk;
+ u32 Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
+ u32 Tsys_clk = dsi->phy.Tsys_clk;
+ u32 Ttxclkesc = dsi->phy.Ttxclkesc;
+
+ switch(offset) {
+ case DPHY_CLOCK_OFFSET:
+ MIPI_DBG("******set DPHY_CLOCK_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE0_OFFSET:
+ MIPI_DBG("******set DPHY_LANE0_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE1_OFFSET:
+ MIPI_DBG("******set DPHY_LANE1_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE2_OFFSET:
+ MIPI_DBG("******set DPHY_LANE2_OFFSET gotp******\n");
+ break;
+ case DPHY_LANE3_OFFSET:
+ MIPI_DBG("******set DPHY_LANE3_OFFSET gotp******\n");
+ break;
+ default:
+ break;
+ }
+
+ if(ddr_clk < 110 * MHz)
+ val = 0;
+ else if(ddr_clk < 150 * MHz)
+ val = 1;
+ else if(ddr_clk < 200 * MHz)
+ val = 2;
+ else if(ddr_clk < 250 * MHz)
+ val = 3;
+ else if(ddr_clk < 300 * MHz)
+ val = 4;
+ else if(ddr_clk < 400 * MHz)
+ val = 5;
+ else if(ddr_clk < 500 * MHz)
+ val = 6;
+ else if(ddr_clk < 600 * MHz)
+ val = 7;
+ else if(ddr_clk < 700 * MHz)
+ val = 8;
+ else if(ddr_clk < 800 * MHz)
+ val = 9;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 10;
+ rk32_dsi_set_bits(dsi, val, reg_ths_settle + offset);
+
+ if(ddr_clk < 110 * MHz)
+ val = 0x20;
+ else if(ddr_clk < 150 * MHz)
+ val = 0x06;
+ else if(ddr_clk < 200 * MHz)
+ val = 0x18;
+ else if(ddr_clk < 250 * MHz)
+ val = 0x05;
+ else if(ddr_clk < 300 * MHz)
+ val = 0x51;
+ else if(ddr_clk < 400 * MHz)
+ val = 0x64;
+ else if(ddr_clk < 500 * MHz)
+ val = 0x59;
+ else if(ddr_clk < 600 * MHz)
+ val = 0x6a;
+ else if(ddr_clk < 700 * MHz)
+ val = 0x3e;
+ else if(ddr_clk < 800 * MHz)
+ val = 0x21;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 0x09;
+ rk32_dsi_set_bits(dsi, val, reg_hs_ths_prepare + offset);
+
+ if(offset != DPHY_CLOCK_OFFSET) {
+
+ if(ddr_clk < 110 * MHz)
+ val = 2;
+ else if(ddr_clk < 150 * MHz)
+ val = 3;
+ else if(ddr_clk < 200 * MHz)
+ val = 4;
+ else if(ddr_clk < 250 * MHz)
+ val = 5;
+ else if(ddr_clk < 300 * MHz)
+ val = 6;
+ else if(ddr_clk < 400 * MHz)
+ val = 7;
+ else if(ddr_clk < 500 * MHz)
+ val = 7;
+ else if(ddr_clk < 600 * MHz)
+ val = 8;
+ else if(ddr_clk < 700 * MHz)
+ val = 8;
+ else if(ddr_clk < 800 * MHz)
+ val = 9;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 9;
+ } else {
+
+ if(ddr_clk < 110 * MHz)
+ val = 0x16;
+ else if(ddr_clk < 150 * MHz)
+ val = 0x16;
+ else if(ddr_clk < 200 * MHz)
+ val = 0x17;
+ else if(ddr_clk < 250 * MHz)
+ val = 0x17;
+ else if(ddr_clk < 300 * MHz)
+ val = 0x18;
+ else if(ddr_clk < 400 * MHz)
+ val = 0x19;
+ else if(ddr_clk < 500 * MHz)
+ val = 0x1b;
+ else if(ddr_clk < 600 * MHz)
+ val = 0x1d;
+ else if(ddr_clk < 700 * MHz)
+ val = 0x1e;
+ else if(ddr_clk < 800 * MHz)
+ val = 0x1f;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 0x20;
+ }
+ rk32_dsi_set_bits(dsi, val, reg_hs_the_zero + offset);
+
+ if(ddr_clk < 110 * MHz)
+ val = 0x22;
+ else if(ddr_clk < 150 * MHz)
+ val = 0x45;
+ else if(ddr_clk < 200 * MHz)
+ val = 0x0b;
+ else if(ddr_clk < 250 * MHz)
+ val = 0x16;
+ else if(ddr_clk < 300 * MHz)
+ val = 0x2c;
+ else if(ddr_clk < 400 * MHz)
+ val = 0x33;
+ else if(ddr_clk < 500 * MHz)
+ val = 0x4e;
+ else if(ddr_clk < 600 * MHz)
+ val = 0x3a;
+ else if(ddr_clk < 700 * MHz)
+ val = 0x6a;
+ else if(ddr_clk < 800 * MHz)
+ val = 0x29;
+ else if(ddr_clk <= 1000 * MHz)
+ val = 0x21; //0x27
+
+ rk32_dsi_set_bits(dsi, val, reg_hs_ths_trail + offset);
+ val = 120000 / Ttxbyte_clk + 1;
+ MIPI_DBG("reg_hs_ths_exit: %d, %d\n", val, val*Ttxbyte_clk/1000);
+ rk32_dsi_set_bits(dsi, val, reg_hs_ths_exit + offset);
+
+ if(offset == DPHY_CLOCK_OFFSET) {
+ val = (60000 + 52*dsi->phy.UI) / Ttxbyte_clk + 1;
+ MIPI_DBG("reg_hs_tclk_post: %d, %d\n", val, val*Ttxbyte_clk/1000);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tclk_post + offset);
+ val = 10*dsi->phy.UI / Ttxbyte_clk + 1;
+ MIPI_DBG("reg_hs_tclk_pre: %d, %d\n", val, val*Ttxbyte_clk/1000);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tclk_pre + offset);
+ }
+
+ val = 1010000000 / Tsys_clk + 1;
+ MIPI_DBG("reg_hs_twakup: %d, %d\n", val, val*Tsys_clk/1000);
+ if(val > 0x3ff) {
+ val = 0x2ff;
+ MIPI_DBG("val is too large, 0x3ff is the largest\n");
+ }
+ temp = (val >> 8) & 0x03;
+ val &= 0xff;
+ rk32_dsi_set_bits(dsi, temp, reg_hs_twakup_h + offset);
+ rk32_dsi_set_bits(dsi, val, reg_hs_twakup_l + offset);
+
+ if(Ttxclkesc > 50000) {
+ val = 2*Ttxclkesc;
+ MIPI_DBG("Ttxclkesc:%d\n", Ttxclkesc);
+ }
+ val = val / Ttxbyte_clk;
+ Tlpx = val*Ttxbyte_clk;
+ MIPI_DBG("reg_hs_tlpx: %d, %d\n", val, Tlpx);
+ val -= 2;
+ rk32_dsi_set_bits(dsi, val, reg_hs_tlpx + offset);
+
+ Tlpx = 2*Ttxclkesc;
+ val = 4*Tlpx / Ttxclkesc;
+ MIPI_DBG("reg_hs_tta_go: %d, %d\n", val, val*Ttxclkesc);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tta_go + offset);
+ val = 3 * Tlpx / 2 / Ttxclkesc;
+ MIPI_DBG("reg_hs_tta_sure: %d, %d\n", val, val*Ttxclkesc);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tta_sure + offset);
+ val = 5 * Tlpx / Ttxclkesc;
+ MIPI_DBG("reg_hs_tta_wait: %d, %d\n", val, val*Ttxclkesc);
+ rk32_dsi_set_bits(dsi, val, reg_hs_tta_wait + offset);
+ return 0;
+}
+
+static int rk312x_phy_init(struct dsi *dsi, int n)
+{
+ //DPHY init
+ rk32_dsi_set_bits(dsi, 0x11, DSI_DPHY_BITS(0x06<<2, 32, 0));
+ rk32_dsi_set_bits(dsi, 0x11, DSI_DPHY_BITS(0x07<<2, 32, 0));
+ rk32_dsi_set_bits(dsi, 0xcc, DSI_DPHY_BITS(0x09<<2, 32, 0));
+#if 0
+ dsi_set_bits(0x4e, DSI_DPHY_BITS(0x08<<2, 32, 0));
+ dsi_set_bits(0x84, DSI_DPHY_BITS(0x0a<<2, 32, 0));
+#endif
+
+ /*reg1[4] 0: enable a function of "pll phase for serial data being captured
+ inside analog part"
+ 1: disable it
+ we disable it here because reg5[6:4] is not compatible with the HS speed.
+ */
+
+ if(dsi->phy.ddr_clk >= 800*MHz) {
+ rk32_dsi_set_bits(dsi, 0x30, DSI_DPHY_BITS(0x05<<2, 32, 0));
+ } else {
+ rk32_dsi_set_bits(dsi, 1, reg_da_ppfc);
+ }
+
+ switch(dsi->host.lane) {
+ case 4:
+ rk321x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE3_OFFSET, n);
+ case 3:
+ rk321x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE2_OFFSET, n);
+ case 2:
+ rk321x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE1_OFFSET, n);
+ case 1:
+ rk321x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE0_OFFSET, n);
+ rk321x_mipi_dsi_phy_set_gotp(dsi, DPHY_CLOCK_OFFSET, n);
+ break;
+ default:
+ break;
+ }
+ return 0;
+
+}
+
+static int rk_phy_init(struct dsi *dsi)
+{
+ if(cpu_is_rk3288())
+ rk32_phy_init(dsi);
+ else if(cpu_is_rk312x())
+ rk312x_phy_init(dsi, 4);
+ return 0;
+}
static int rk32_mipi_dsi_host_power_up(struct dsi *dsi)
{
return ret;
}
+
+
+
static int rk32_mipi_dsi_host_power_down(struct dsi *dsi)
{
rk32_mipi_dsi_enable_video_mode(dsi, 0);
return 0;
}
+
+
static int rk32_mipi_dsi_host_init(struct dsi *dsi)
{
u32 val = 0, bytes_px = 0;
dsi->phy.Ttxbyte_clk);
MIPI_DBG("txclkesc:%d, Ttxclkesc:%d\n", dsi->phy.txclkesc, dsi->phy.Ttxclkesc);
- rk32_phy_power_up(dsi);
+ rk_phy_power_up(dsi);
rk32_mipi_dsi_host_power_up(dsi);
- rk32_phy_init(dsi);
+ rk_phy_init(dsi);
rk32_mipi_dsi_host_init(dsi);
return 0;
return -1;
rk32_mipi_dsi_host_power_down(dsi);
- rk32_phy_power_down(dsi);
+ rk_phy_power_down(dsi);
MIPI_TRACE("%s:%d\n", __func__, __LINE__);
return 0;
rk_fb_get_prmry_screen(dsi0->screen.screen);
dsi0->screen.lcdc_id = dsi0->screen.screen->lcdc_id;
- rk32_init_phy_mode(dsi0->screen.lcdc_id);
+ rk_init_phy_mode(dsi0->screen.lcdc_id);
dsi_init(0, 0);
if (rk_mipi_get_dsi_num() ==2)
writel_relaxed(val1, RK_GRF_VIRT + RK3288_GRF_SOC_CON14);
}
}
+
+static void rk_init_phy_mode(int lcdc_id)
+{
+ if(cpu_is_rk3288())
+ rk32_init_phy_mode(lcdc_id);
+
+}
#ifdef CONFIG_RK_3288_DSI_UBOOT
#ifdef CONFIG_OF_LIBFDT
int rk_dsi_host_parse_dt(const void *blob, struct dsi *dsi)
struct mipi_dsi_ops *ops;
struct rk_screen *screen;
struct mipi_dsi_screen *dsi_screen;
- struct resource *res_host;
+ struct resource *res_host, *res_phy;
dsi = devm_kzalloc(&pdev->dev, sizeof(struct dsi), GFP_KERNEL);
if(!dsi) {
return -ENOMEM;
}
- res_host = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
- if (!dsi->host.membase){
- dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
- return -ENOMEM;
+ if(cpu_is_rk3288()){
+ res_host = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
+ if (!dsi->host.membase){
+ dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
+ return -ENOMEM;
+ }
+ }else if(cpu_is_rk312x()){
+ res_host = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mipi_dsi_host");
+ dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
+ if (!dsi->host.membase){
+ dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
+ return -ENOMEM;
+ }
+ res_phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mipi_dsi_phy");
+ dsi->phy.membase = devm_request_and_ioremap(&pdev->dev, res_host);
+ if (!dsi->phy.membase){
+ dev_err(&pdev->dev, "get resource mipi phy membase fail!\n");
+ return -ENOMEM;
+ }
}
dsi->phy.refclk = devm_clk_get(&pdev->dev, "clk_mipi_24m");
dev_err(&pdev->dev, "get clk_mipi_24m clock fail\n");
return PTR_ERR(dsi->phy.refclk);
}
-
+
dsi->dsi_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
if (unlikely(IS_ERR(dsi->dsi_pclk))) {
dev_err(&pdev->dev, "get pclk_mipi_dsi clock fail\n");
return PTR_ERR(dsi->dsi_pclk);
}
-
- dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
- if (unlikely(IS_ERR(dsi->dsi_pd))) {
- dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
- return PTR_ERR(dsi->dsi_pd);
+ if(cpu_is_rk3288()){
+ dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
+ if (unlikely(IS_ERR(dsi->dsi_pd))) {
+ dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
+ return PTR_ERR(dsi->dsi_pd);
+ }
}
-
dsi->host.irq = platform_get_irq(pdev, 0);
if (dsi->host.irq < 0) {
dev_err(&pdev->dev, "no irq resource?\n");
if(support_uboot_display()){
clk_prepare_enable(dsi->phy.refclk);
clk_prepare_enable(dsi->dsi_pclk);
- clk_prepare_enable(dsi->dsi_pd);
+ if(cpu_is_rk3288())
+ clk_prepare_enable(dsi->dsi_pd);
udelay(10);
}
dev_info(&pdev->dev,"rk mipi_dsi probe success!\n");
#else
#include <linux/rockchip/grf.h>
#endif
+#define MIPI_DSI_PHY_OFFSET 0x0C00
+#define MIPI_DSI_PHY_SIZE 0x34c
+
#define MIPI_DSI_HOST_OFFSET 0x1000
//function bits definition register addr | bits | offest
#define BITS_OFFSET(a) (a)
#define DSI_HOST_BITS(addr, bits, bit_offset) (REG_ADDR((addr)+MIPI_DSI_HOST_OFFSET) \
| REG_BITS(bits) | BITS_OFFSET(bit_offset))
+#define DSI_DPHY_BITS(addr, bits, bit_offset) (REG_ADDR((addr)+MIPI_DSI_PHY_OFFSET) \
+ | REG_BITS(bits) | BITS_OFFSET(bit_offset))
//DWC_DSI_VERSION_0x3133302A
#define VERSION DSI_HOST_BITS(0x000, 32, 0)
#define code_hstxdatalanepreparestatetime 0x71
#define code_hstxdatalanehszerostatetime 0x72
+//rk312x MIPI DSI DPHY REGISTERS
+#define DPHY_REGISTER0 DSI_DPHY_BITS(0x00, 32, 0)
+#define DPHY_REGISTER1 DSI_DPHY_BITS(0x04, 32, 0)
+#define DPHY_REGISTER3 DSI_DPHY_BITS(0x0c, 32, 0)
+#define DPHY_REGISTER4 DSI_DPHY_BITS(0x10, 32, 0)
+#define DPHY_REGISTER20 DSI_DPHY_BITS(0X80, 32, 0)
+
+#define lane_en_ck DSI_DPHY_BITS(0x00, 1, 6)
+#define lane_en_3 DSI_DPHY_BITS(0x00, 1, 5)
+#define lane_en_2 DSI_DPHY_BITS(0x00, 1, 4)
+#define lane_en_1 DSI_DPHY_BITS(0x00, 1, 3)
+#define lane_en_0 DSI_DPHY_BITS(0x00, 1, 2)
+
+#define reg_da_ppfc DSI_DPHY_BITS(0x04, 1, 4)
+#define reg_da_syncrst DSI_DPHY_BITS(0x04, 1, 2)
+#define reg_da_ldopd DSI_DPHY_BITS(0x04, 1, 1)
+#define reg_da_pllpd DSI_DPHY_BITS(0x04, 1, 0)
+
+#define reg_fbdiv_8 DSI_DPHY_BITS(0x0c, 1, 5)
+#define reg_prediv DSI_DPHY_BITS(0x0c, 5, 0)
+#define reg_fbdiv DSI_DPHY_BITS(0x10, 8, 0)
+
+#define reg_dig_rstn DSI_DPHY_BITS(0X80, 1, 0)
+
+#define DPHY_CLOCK_OFFSET REG_ADDR(0X0100)
+#define DPHY_LANE0_OFFSET REG_ADDR(0X0180)
+#define DPHY_LANE1_OFFSET REG_ADDR(0X0200)
+#define DPHY_LANE2_OFFSET REG_ADDR(0X0280)
+#define DPHY_LANE3_OFFSET REG_ADDR(0X0300)
+
+#define reg_ths_settle DSI_DPHY_BITS(0x0000, 4, 0)
+#define reg_hs_tlpx DSI_DPHY_BITS(0x0014, 6, 0)
+#define reg_hs_ths_prepare DSI_DPHY_BITS(0x0018, 7, 0)
+#define reg_hs_the_zero DSI_DPHY_BITS(0x001c, 6, 0)
+#define reg_hs_ths_trail DSI_DPHY_BITS(0x0020, 7, 0)
+#define reg_hs_ths_exit DSI_DPHY_BITS(0x0024, 5, 0)
+#define reg_hs_tclk_post DSI_DPHY_BITS(0x0028, 4, 0)
+#define reserved DSI_DPHY_BITS(0x002c, 1, 0)
+#define reg_hs_twakup_h DSI_DPHY_BITS(0x0030, 2, 0)
+#define reg_hs_twakup_l DSI_DPHY_BITS(0x0034, 8, 0)
+#define reg_hs_tclk_pre DSI_DPHY_BITS(0x0038, 4, 0)
+#define reg_hs_tta_go DSI_DPHY_BITS(0x0040, 6, 0)
+#define reg_hs_tta_sure DSI_DPHY_BITS(0x0044, 6, 0)
+#define reg_hs_tta_wait DSI_DPHY_BITS(0x0048, 6, 0)
+//end of rk312x MIPI DSI DPHY REGISTERS
//global operation timing parameter
struct gotp_m {
static int rk32_mipi_power_down_DDR(void);
static int rk32_mipi_power_up_DDR(void);
static void rk32_init_phy_mode(int lcdc_id);
+static void rk_init_phy_mode(int lcdc_id);
#endif /* end of RK32_MIPI_DSI_H */
projects / firefly-linux-kernel-4.4.55.git / commitdiff