misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h
index 4c6b74df2ae3a8d73a096bd8e80f207519d263d7..a08f6cc7f702c7bea2224e8d69d19c1ddb97dfa9 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -188,12 +188,12 @@ namespace llvm {
     MachineBasicBlock *BB;
 
     /// The beginning of the range to be scheduled.
-    MachineBasicBlock::iterator Begin;
+    MachineBasicBlock::iterator RegionBegin;
 
     /// The end of the range to be scheduled.
-    MachineBasicBlock::iterator End;
+    MachineBasicBlock::iterator RegionEnd;
 
-    /// The index in BB of End.
+    /// The index in BB of RegionEnd.
     unsigned EndIndex;
 
     /// After calling BuildSchedGraph, each machine instruction in the current
@@ -240,10 +240,10 @@ namespace llvm {
     virtual ~ScheduleDAGInstrs() {}
 
     /// begin - Return an iterator to the top of the current scheduling region.
-    MachineBasicBlock::iterator begin() const { return Begin; }
+    MachineBasicBlock::iterator begin() const { return RegionBegin; }
 
     /// end - Return an iterator to the bottom of the current scheduling region.
-    MachineBasicBlock::iterator end() const { return End; }
+    MachineBasicBlock::iterator end() const { return RegionEnd; }
 
     /// newSUnit - Creates a new SUnit and return a ptr to it.
     SUnit *newSUnit(MachineInstr *MI);

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index dc0c098a795ab6f885371fc52552a4e377fdfc3c..4f27274796b472568be26827334770eaecc1ca28 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -275,7 +275,7 @@ void ScheduleTopDownLive::schedule() {
       releaseNode(&(*I));
   }
 
-  MachineBasicBlock::iterator InsertPos = Begin;
+  MachineBasicBlock::iterator InsertPos = RegionBegin;
   while (SUnit *SU = pickNode()) {
     DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
 
@@ -286,8 +286,8 @@ void ScheduleTopDownLive::schedule() {
     else {
       BB->splice(InsertPos, BB, MI);
       LIS->handleMove(MI);
-      if (Begin == InsertPos)
-        Begin = MI;
+      if (RegionBegin == InsertPos)
+        RegionBegin = MI;
     }
 
     // Release dependent instructions for scheduling.

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 6bd270551bc54945a89084aa0ebe8a287c40483a..24d3e5ab0c9d4b4ad6d776f8084210a5dad9aa1c 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -365,8 +365,8 @@ void SchedulePostRATDList::schedule() {
 
   if (AntiDepBreak != NULL) {
     unsigned Broken =
-      AntiDepBreak->BreakAntiDependencies(SUnits, Begin, End, EndIndex,
-                                          DbgValues);
+      AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
+                                          EndIndex, DbgValues);
 
     if (Broken != 0) {
       // We made changes. Update the dependency graph.
@@ -761,24 +761,24 @@ void SchedulePostRATDList::ListScheduleTopDown() {
 
 // EmitSchedule - Emit the machine code in scheduled order.
 void SchedulePostRATDList::EmitSchedule() {
-  Begin = End;
+  RegionBegin = RegionEnd;
 
   // If first instruction was a DBG_VALUE then put it back.
   if (FirstDbgValue)
-    BB->splice(End, BB, FirstDbgValue);
+    BB->splice(RegionEnd, BB, FirstDbgValue);
 
   // Then re-insert them according to the given schedule.
   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     if (SUnit *SU = Sequence[i])
-      BB->splice(End, BB, SU->getInstr());
+      BB->splice(RegionEnd, BB, SU->getInstr());
     else
       // Null SUnit* is a noop.
-      TII->insertNoop(*BB, End);
+      TII->insertNoop(*BB, RegionEnd);
 
     // Update the Begin iterator, as the first instruction in the block
     // may have been scheduled later.
     if (i == 0)
-      Begin = prior(End);
+      RegionBegin = prior(RegionEnd);
   }
 
   // Reinsert any remaining debug_values.

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 09f2c5b5de912ad507d3dac8287e873fbe583fcf..ed066724374b0cef9b8737ac88cbda115a68ba8c 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -160,8 +160,8 @@ void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
                                     MachineBasicBlock::iterator end,
                                     unsigned endcount) {
   BB = bb;
-  Begin = begin;
-  End = end;
+  RegionBegin = begin;
+  RegionEnd = end;
   EndIndex = endcount;
 
   // Check to see if the scheduler cares about latencies.
@@ -185,7 +185,7 @@ void ScheduleDAGInstrs::exitRegion() {
 /// are too high to be hidden by the branch or when the liveout registers
 /// used by instructions in the fallthrough block.
 void ScheduleDAGInstrs::addSchedBarrierDeps() {
-  MachineInstr *ExitMI = End != BB->end() ? &*End : 0;
+  MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
   ExitSU.setInstr(ExitMI);
   bool AllDepKnown = ExitMI &&
     (ExitMI->isCall() || ExitMI->isBarrier());
@@ -477,7 +477,7 @@ void ScheduleDAGInstrs::initSUnits() {
   // which is contained within a basic block.
   SUnits.reserve(BB->size());
 
-  for (MachineBasicBlock::iterator I = Begin; I != End; ++I) {
+  for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
     MachineInstr *MI = I;
     if (MI->isDebugValue())
       continue;
@@ -535,7 +535,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA) {
 
   // Walk the list of instructions, from bottom moving up.
   MachineInstr *PrevMI = NULL;
-  for (MachineBasicBlock::iterator MII = End, MIE = Begin;
+  for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
        MII != MIE; --MII) {
     MachineInstr *MI = prior(MII);
     if (MI && PrevMI) {