Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...

* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (48 commits)
  x86/PCI: Prevent mmconfig memory corruption
  ACPI: Use GPE reference counting to support shared GPEs
  x86/PCI: use host bridge _CRS info by default on 2008 and newer machines
  PCI: augment bus resource table with a list
  PCI: add pci_bus_for_each_resource(), remove direct bus->resource[] refs
  PCI: read bridge windows before filling in subtractive decode resources
  PCI: split up pci_read_bridge_bases()
  PCIe PME: use pci_pcie_cap()
  PCI PM: Run-time callbacks for PCI bus type
  PCIe PME: use pci_is_pcie()
  PCI / ACPI / PM: Platform support for PCI PME wake-up
  ACPI / ACPICA: Multiple system notify handlers per device
  ACPI / PM: Add more run-time wake-up fields
  ACPI: Use GPE reference counting to support shared GPEs
  PCI PM: Make it possible to force using INTx for PCIe PME signaling
  PCI PM: PCIe PME root port service driver
  PCI PM: Add function for checking PME status of devices
  PCI: mark is_pcie obsolete
  PCI: set PCI_PREF_RANGE_TYPE_64 in pci_bridge_check_ranges
  PCI: pciehp: second try to get big range for pcie devices
  ...

diff --combined arch/parisc/kernel/pci.c
index 9e74bfe071dc0517ac7310f9d1223cb22c18c9a5,5179e5e6f8fb94cff2f31f280d3955cc2b5ed33b..38372e7cbb88f1d53372061e5e6e23684bcbc4a9
--- 1/arch/parisc/kernel/pci.c
--- 2/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@@ -18,6 -18,7 +18,6 @@@
  
  #include <asm/io.h>
  #include <asm/system.h>
 -#include <asm/cache.h>                /* for L1_CACHE_BYTES */
  #include <asm/superio.h>
  
  #define DEBUG_RESOURCES 0
@@@ -122,10 -123,6 +122,10 @@@ static int __init pcibios_init(void
        } else {
                printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
        }
 +
 +      /* Set the CLS for PCI as early as possible. */
 +      pci_cache_line_size = pci_dfl_cache_line_size;
 +
        return 0;
  }
  
@@@ -174,7 -171,7 +174,7 @@@ void pcibios_set_master(struct pci_dev 
        ** upper byte is PCI_LATENCY_TIMER.
        */
        pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
 -                              (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
 +                            (0x80 << 8) | pci_cache_line_size);
  }
  
  
@@@ -257,10 -254,10 +257,10 @@@ EXPORT_SYMBOL(pcibios_bus_to_resource)
   * Since we are just checking candidates, don't use any fields other
   * than res->start.
   */
- void pcibios_align_resource(void *data, struct resource *res,
+ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                resource_size_t size, resource_size_t alignment)
  {
-       resource_size_t mask, align;
+       resource_size_t mask, align, start = res->start;
  
        DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
                pci_name(((struct pci_dev *) data)),
@@@ -272,10 -269,10 +272,10 @@@
  
        /* Align to largest of MIN or input size */
        mask = max(alignment, align) - 1;
-       res->start += mask;
-       res->start &= ~mask;
+       start += mask;
+       start &= ~mask;
  
-       /* The caller updates the end field, we don't.  */
+       return start;
  }