#define RK30_L2MEM_SIZE SZ_512K
#define RK30_IMEM_PHYS 0x10080000
#define RK30_IMEM_BASE IOMEM(0xFEF00000)
+#define RK30_IMEM_NONCACHED RK30_IO_TO_VIRT0(RK30_IMEM_PHYS)
#define RK30_IMEM_SIZE SZ_64K
#define RK30_GPU_PHYS 0x10090000
#define RK30_GPU_SIZE SZ_64K
RK30_DEVICE(PWM23),
RK30_DEVICE(DDR_PCTL),
RK30_DEVICE(DDR_PUBL),
+#ifdef CONFIG_RK_SRAM_DMA
+ {
+ .virtual = (unsigned long) RK30_IMEM_NONCACHED,
+ .pfn = __phys_to_pfn(RK30_IMEM_PHYS),
+ .length = RK30_IMEM_SIZE,
+ .type = MT_MEMORY_NONCACHED,
+ },
+#endif
};
void __init rk30_map_common_io(void)
SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 2,
.channels_max = 8,
+#ifdef CONFIG_RK_SRAM_DMA
+ .buffer_bytes_max = 48*1024,
+#else
.buffer_bytes_max = 128*1024,
+#endif
.period_bytes_min = 64, ///PAGE_SIZE,
+#ifdef CONFIG_RK_SRAM_DMA
+ .period_bytes_max = 4096*4,
+#else
.period_bytes_max = 2048*4,///PAGE_SIZE*2,
+#endif
.periods_min = 3,///2,
.periods_max = 128,
.fifo_size = 16,
.mmap = rockchip_pcm_mmap,
};
+#ifdef CONFIG_ARCH_RK30
+#define SRAM_DMA_PHYS (dma_addr_t)(RK30_IMEM_PHYS + 16*1024)
+#define SRAM_DMA_START (RK30_IMEM_NONCACHED + 16*1024)
+#endif
+
static int rockchip_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
struct snd_pcm_substream *substream = pcm->streams[stream].substream;
buf->dev.type = SNDRV_DMA_TYPE_DEV;
buf->dev.dev = pcm->card->dev;
buf->private_data = NULL;
+#ifdef CONFIG_RK_SRAM_DMA
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ buf->area = SRAM_DMA_START;
+ buf->addr = SRAM_DMA_PHYS;
+ } else
+#endif
buf->area = dma_alloc_writecombine(pcm->card->dev, size,
&buf->addr, GFP_KERNEL);
if (!buf->area)