UPSTREAM: clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
 commit 535ebd428aeb07c3327947281306f2943f2c9faa)

Change-Id: I26364fdba8cdfe36c8b9ba767b4226c9ac6ff118

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 1a6f0741c4b7890676e89f168597361248135fb2..63d0c2ad4816162642d8b87a21906ff081e9767a 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
        .core_reg = RK3368_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
-       .mux_core_shift = 15,
+       .mux_core_shift = 7,
 };
 
 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {