ath9k_hw: make antenna diversity modules chip specific
authorMohammed Shafi Shajakhan <mshajakhan@atheros.com>
Fri, 13 May 2011 14:59:04 +0000 (20:29 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 16 May 2011 18:10:42 +0000 (14:10 -0400)
this is necessary to support Antenna diversity and combining in new chip
sets such as AR9485, previously Antenna diversity support is available
only in AR9285

Cc: Gabriel Tseng <Gabriel.Tseng@Atheros.com>
Cc: Senthilkumar Balasubramanian <Senthilkumar.Balasubramanian@Atheros.com>
Signed-off-by: Mohammed Shafi Shajakhan <mshajakhan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9002_phy.c
drivers/net/wireless/ath/ath9k/hw-ops.h
drivers/net/wireless/ath/ath9k/hw.h

index 7d68d61e406b435a067d9b8ba47866ea850ee490..b4a0c1d3b1156593516824bc53826ccf7ae23ad3 100644 (file)
@@ -517,23 +517,7 @@ static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
        }
 }
 
-void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
-{
-       struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-
-       priv_ops->set_rf_regs = NULL;
-       priv_ops->rf_alloc_ext_banks = NULL;
-       priv_ops->rf_free_ext_banks = NULL;
-       priv_ops->rf_set_freq = ar9002_hw_set_channel;
-       priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
-       priv_ops->olc_init = ar9002_olc_init;
-       priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
-       priv_ops->do_getnf = ar9002_hw_do_getnf;
-
-       ar9002_hw_set_nf_limits(ah);
-}
-
-void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
                                   struct ath_hw_antcomb_conf *antconf)
 {
        u32 regval;
@@ -546,9 +530,8 @@ void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
        antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
                                  AR_PHY_9285_FAST_DIV_BIAS_S;
 }
-EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);
 
-void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
                                   struct ath_hw_antcomb_conf *antconf)
 {
        u32 regval;
@@ -566,4 +549,23 @@ void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
 
        REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
 }
-EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);
+
+void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
+{
+       struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+       struct ath_hw_ops *ops = ath9k_hw_ops(ah);
+
+       priv_ops->set_rf_regs = NULL;
+       priv_ops->rf_alloc_ext_banks = NULL;
+       priv_ops->rf_free_ext_banks = NULL;
+       priv_ops->rf_set_freq = ar9002_hw_set_channel;
+       priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
+       priv_ops->olc_init = ar9002_olc_init;
+       priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
+       priv_ops->do_getnf = ar9002_hw_do_getnf;
+
+       ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
+       ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
+
+       ar9002_hw_set_nf_limits(ah);
+}
index 99f8334d1dfe9930a1ae479affe7b78e2b3e4d6b..8b8f0445aef817fc2395bdb5c33a90847cc3e415 100644 (file)
@@ -121,6 +121,18 @@ static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
        ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
 }
 
+static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+               struct ath_hw_antcomb_conf *antconf)
+{
+       ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf);
+}
+
+static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+               struct ath_hw_antcomb_conf *antconf)
+{
+       ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
+}
+
 /* Private hardware call ops */
 
 /* PHY ops */
index b2248bba25a202cd60bba8557e72fc4140e286fb..67cca10bf4c9b3b97fa334f3677e9cf901a7f6dd 100644 (file)
@@ -629,6 +629,11 @@ struct ath_hw_ops {
        void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
        void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
        void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
+       void (*antdiv_comb_conf_get)(struct ath_hw *ah,
+                       struct ath_hw_antcomb_conf *antconf);
+       void (*antdiv_comb_conf_set)(struct ath_hw *ah,
+                       struct ath_hw_antcomb_conf *antconf);
+
 };
 
 struct ath_nf_limits {
@@ -904,10 +909,6 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
-void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
-                                  struct ath_hw_antcomb_conf *antconf);
-void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
-                                  struct ath_hw_antcomb_conf *antconf);
 
 /* General Operation */
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);