Teach the x86 backend about the register constraints of its addressing mode.

Patch by Evan Cheng

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24423 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 1bb2fecbb828fe48543d6811d08d64753aadaca3..40b2481ab4ac35e1fa69cc381397fe57173320e3 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -17,8 +17,9 @@
 //
 
 class X86MemOperand<ValueType Ty> : Operand<Ty> {
-  let NumMIOperands = 4;
   let PrintMethod = "printMemoryOperand";
+  let NumMIOperands = 4;
+  let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
 }
 def SSECC : Operand<i8> {
   let PrintMethod = "printSSECC";