Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78151 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 63a391a319ac9203d6966b577c64eda74a0c7fb2..860ae9e39a0dcac8f7ab60a3229a09d1883d2dab 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -106,6 +106,23 @@ void LiveIntervals::releaseMemory() {
   }
 }
 
+static bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg,
+                                   const TargetInstrInfo *tii_) {
+  unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+  if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+      Reg == SrcReg)
+    return true;
+
+  if ((MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+       MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
+      MI->getOperand(2).getReg() == Reg)
+    return true;
+  if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
+      MI->getOperand(1).getReg() == Reg)
+    return true;
+  return false;
+}
+
 /// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
 /// there is one implicit_def for each use. Add isUndef marker to
 /// implicit_def defs and their uses.
@@ -132,7 +149,7 @@ void LiveIntervals::processImplicitDefs() {
       bool ChangedToImpDef = false;
       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
         MachineOperand& MO = MI->getOperand(i);
-        if (!MO.isReg() || !MO.isUse())
+        if (!MO.isReg() || !MO.isUse() || MO.isUndef())
           continue;
         unsigned Reg = MO.getReg();
         if (!Reg)
@@ -140,9 +157,7 @@ void LiveIntervals::processImplicitDefs() {
         if (!ImpDefRegs.count(Reg))
           continue;
         // Use is a copy, just turn it into an implicit_def.
-        unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-        if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
-            Reg == SrcReg) {
+        if (CanTurnIntoImplicitDef(MI, Reg, tii_)) {
           bool isKill = MO.isKill();
           MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
           for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
@@ -154,8 +169,15 @@ void LiveIntervals::processImplicitDefs() {
         }
 
         MO.setIsUndef();
-        if (MO.isKill() || MI->isRegTiedToDefOperand(i))
+        if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
+          // Make sure other uses of 
+          for (unsigned j = i+1; j != e; ++j) {
+            MachineOperand &MOJ = MI->getOperand(j);
+            if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
+              MOJ.setIsUndef();
+          }
           ImpDefRegs.erase(Reg);
+        }
       }
 
       if (ChangedToImpDef) {

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 2a12063af97ca1ab881361de2ab5c60ea8c0b9a6..6c5052a06863b7881cc0f52d45b316100a8c6093 100644 (file)
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -119,6 +119,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
          "Extract supperg source must be a physical register");
   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
          "Extract destination must be in a physical register");
+  assert(SrcReg && "invalid subregister index for register");
 
   DOUT << "subreg: CONVERTING: " << *MI;
 

diff --git a/test/CodeGen/Blackfin/printf2.ll b/test/CodeGen/Blackfin/printf2.ll
index 6f402d547e3615be436641d1c4ca61450e451e9b..47c682da6f435614f82b1007c6ce725e74afba74 100644 (file)
--- a/test/CodeGen/Blackfin/printf2.ll
+++ b/test/CodeGen/Blackfin/printf2.ll
@@ -1,7 +1,4 @@
 ; RUN: llvm-as < %s | llc -march=bfin
-; XFAIL: *
-; Assertion failed: (isUsed(Reg) && "Using an undefined register!"),
-; function forward, file RegisterScavenging.cpp, line 182.
 
 declare i32 @printf(i8*, ...)