#define VPU_REG_DEC_PP_GATE_BIT (1<<8)\r
\r
#if defined(CONFIG_VCODEC_MMU)\r
-static u8 addr_tbl_vpu_dec[] = {\r
- 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
+static u8 addr_tbl_vpu_h264dec[] = {\r
+ 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
+};\r
+\r
+static u8 addr_tbl_vpu_vp8dec[] = {\r
+ 10,12,13, 14, 18, 19, 27, 40\r
+};\r
+\r
+static u8 addr_tbl_vpu_vp6dec[] = {\r
+ 12, 13, 14, 18, 27, 40\r
+};\r
+\r
+static u8 addr_tbl_vpu_vc1dec[] = {\r
+ 12, 13, 14, 15, 16, 17, 27, 41\r
+};\r
+\r
+static u8 addr_tbl_vpu_jpegdec[] = {\r
+ 12, 40, 66, 67\r
+};\r
+\r
+static u8 addr_tbl_vpu_defaultdec[] = {\r
+ 12, 13, 14, 15, 16, 17, 40, 41\r
};\r
\r
static u8 addr_tbl_vpu_enc[] = {\r
- 5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
+ 5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
};\r
\r
static u8 addr_tbl_hevc_dec[] = {\r
- 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
+ 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
};\r
#endif\r
\r
+enum VPU_DEC_FMT {\r
+ VPU_DEC_FMT_H264,\r
+ VPU_DEC_FMT_MPEG4,\r
+ VPU_DEC_FMT_H263,\r
+ VPU_DEC_FMT_JPEG,\r
+ VPU_DEC_FMT_VC1,\r
+ VPU_DEC_FMT_MPEG2,\r
+ VPU_DEC_FMT_MPEG1,\r
+ VPU_DEC_FMT_VP6,\r
+ VPU_DEC_FMT_RV,\r
+ VPU_DEC_FMT_VP7,\r
+ VPU_DEC_FMT_VP8,\r
+ VPU_DEC_FMT_AVS,\r
+ VPU_DEC_FMT_SVC,\r
+ VPU_DEC_FMT_VC2,\r
+ VPU_DEC_FMT_MVC,\r
+ VPU_DEC_FMT_THEORA,\r
+ VPU_DEC_FMT_RES\r
+};\r
+\r
/**\r
* struct for process session which connect to vpu\r
*\r
struct list_head session_link; /* link to vpu service session */\r
struct list_head status_link; /* link to register set list */\r
unsigned long size;\r
-#if defined(CONFIG_VCODEC_MMU) \r
- struct list_head mem_region_list;\r
-#endif \r
+#if defined(CONFIG_VCODEC_MMU)\r
+ struct list_head mem_region_list;\r
+#endif\r
unsigned long *reg;\r
} vpu_reg;\r
\r
return (type > 0);\r
}\r
\r
-static inline bool reg_check_avc(vpu_reg *reg)\r
+static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
{\r
- unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
- return (type == 0);\r
+ enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
+ return type;\r
}\r
\r
static inline int reg_probe_width(vpu_reg *reg)\r
}\r
\r
#if defined(CONFIG_VCODEC_MMU)\r
-\r
static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
{\r
- int i;\r
- int usr_fd = 0;\r
- int offset = 0;\r
- \r
- if (tbl == NULL || size <= 0) {\r
- dev_err(pservice->dev, "input arguments invalidate\n");\r
- return -1;\r
- }\r
- \r
- vpu_service_power_on(pservice);\r
- \r
- for (i=0; i<size; i++) {\r
-#if 0\r
- if (copy_from_user(&usr_fd, ®->reg[addr_tbl_vpu_dec[i]], sizeof(usr_fd)))\r
- return -EFAULT;\r
-#else\r
- usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
- offset = reg->reg[tbl[i]] >> 10;\r
- \r
-#endif\r
- if (usr_fd != 0) {\r
- struct ion_handle *hdl;\r
- \r
- hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
- if (IS_ERR(hdl)) {\r
- dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
- return PTR_ERR(hdl);\r
- }\r
+ int i;\r
+ int usr_fd = 0;\r
+ int offset = 0;\r
\r
-#if 0\r
- {\r
- ion_phys_addr_t phy_addr;\r
- size_t len;\r
- ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
- \r
- reg->reg[tbl[i]] = phy_addr + offset;\r
- \r
- ion_free(pservice->ion_client, hdl);\r
- }\r
-#else \r
- {\r
- int ret;\r
- struct vcodec_mem_region *mem_region;\r
- mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
- \r
- if (mem_region == NULL) {\r
- dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
- ion_free(pservice->ion_client, hdl);\r
- return -1;\r
- }\r
- \r
- mem_region->hdl = hdl;\r
- \r
- ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
- if (ret < 0) {\r
- dev_err(pservice->dev, "ion map iommu failed\n");\r
- kfree(mem_region);\r
- ion_free(pservice->ion_client, hdl);\r
- return ret;\r
- }\r
- \r
- reg->reg[tbl[i]] = mem_region->iova + offset;\r
- INIT_LIST_HEAD(&mem_region->reg_lnk);\r
- list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);\r
- }\r
-#endif\r
- }\r
- }\r
- \r
- return 0;\r
+ if (tbl == NULL || size <= 0) {\r
+ dev_err(pservice->dev, "input arguments invalidate\n");\r
+ return -1;\r
+ }\r
+\r
+ vpu_service_power_on(pservice);\r
+\r
+ for (i = 0; i < size; i++) {\r
+ usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
+\r
+ if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID && (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {\r
+ /* special for vpu dec num 41 regitster */\r
+ offset = reg->reg[tbl[i]] >> 10 << 4;\r
+ } else {\r
+ offset = reg->reg[tbl[i]] >> 10;\r
+ }\r
+\r
+ if (usr_fd != 0) {\r
+ struct ion_handle *hdl;\r
+ int ret;\r
+ struct vcodec_mem_region *mem_region;\r
+\r
+ hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
+ if (IS_ERR(hdl)) {\r
+ dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
+ return PTR_ERR(hdl);\r
+ }\r
+\r
+ mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
+\r
+ if (mem_region == NULL) {\r
+ dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
+ ion_free(pservice->ion_client, hdl);\r
+ return -1;\r
+ }\r
+\r
+ mem_region->hdl = hdl;\r
+\r
+ ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
+ if (ret < 0) {\r
+ dev_err(pservice->dev, "ion map iommu failed\n");\r
+ kfree(mem_region);\r
+ ion_free(pservice->ion_client, hdl);\r
+ return ret;\r
+ }\r
+ reg->reg[tbl[i]] = mem_region->iova + offset;\r
+ INIT_LIST_HEAD(&mem_region->reg_lnk);\r
+ list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);\r
+ }\r
+ }\r
+ return 0;\r
}\r
\r
static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
{\r
- VPU_HW_ID hw_id;\r
- u8 *tbl;\r
- int size = 0;\r
- \r
- hw_id = pservice->hw_info->hw_id;\r
- \r
- if (hw_id == HEVC_ID) {\r
- tbl = addr_tbl_hevc_dec;\r
- size = sizeof(addr_tbl_hevc_dec);\r
- } else {\r
- if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
- tbl = addr_tbl_vpu_dec;\r
- size = sizeof(addr_tbl_vpu_dec);\r
- } else if (reg->type == VPU_ENC) {\r
- tbl = addr_tbl_vpu_enc;\r
- size = sizeof(addr_tbl_vpu_enc);\r
- }\r
- }\r
- \r
- if (size != 0) {\r
- return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
- } else {\r
- return -1;\r
- }\r
+ VPU_HW_ID hw_id;\r
+ u8 *tbl;\r
+ int size = 0;\r
+\r
+ hw_id = pservice->hw_info->hw_id;\r
+\r
+ if (hw_id == HEVC_ID) {\r
+ tbl = addr_tbl_hevc_dec;\r
+ size = sizeof(addr_tbl_hevc_dec);\r
+ } else {\r
+ if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
+ switch (reg_check_fmt(reg)) {\r
+ case VPU_DEC_FMT_H264:\r
+ {\r
+ tbl = addr_tbl_vpu_h264dec;\r
+ size = sizeof(addr_tbl_vpu_h264dec);\r
+ break;\r
+ }\r
+ case VPU_DEC_FMT_VP8:\r
+ case VPU_DEC_FMT_VP7:\r
+ {\r
+ tbl = addr_tbl_vpu_vp8dec;\r
+ size = sizeof(addr_tbl_vpu_vp8dec);\r
+ break;\r
+ }\r
+\r
+ case VPU_DEC_FMT_VP6:\r
+ {\r
+ tbl = addr_tbl_vpu_vp6dec;\r
+ size = sizeof(addr_tbl_vpu_vp6dec);\r
+ break;\r
+ }\r
+ case VPU_DEC_FMT_VC1:\r
+ {\r
+ tbl = addr_tbl_vpu_vc1dec;\r
+ size = sizeof(addr_tbl_vpu_vc1dec);\r
+ break;\r
+ }\r
+\r
+ case VPU_DEC_FMT_JPEG:\r
+ {\r
+ tbl = addr_tbl_vpu_jpegdec;\r
+ size = sizeof(addr_tbl_vpu_jpegdec);\r
+ break;\r
+ }\r
+ default:\r
+ tbl = addr_tbl_vpu_defaultdec;\r
+ size = sizeof(addr_tbl_vpu_defaultdec);\r
+ break;\r
+ }\r
+ } else if (reg->type == VPU_ENC) {\r
+ tbl = addr_tbl_vpu_enc;\r
+ size = sizeof(addr_tbl_vpu_enc);\r
+ }\r
+ }\r
+\r
+ if (size != 0) {\r
+ return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
+ } else {\r
+ return -1;\r
+ }\r
}\r
#endif\r
\r
INIT_LIST_HEAD(®->status_link);\r
\r
#if defined(CONFIG_VCODEC_MMU) \r
- INIT_LIST_HEAD(®->mem_region_list);\r
-#endif \r
+ INIT_LIST_HEAD(®->mem_region_list);\r
+#endif\r
\r
if (copy_from_user(®->reg[0], (void __user *)src, size)) {\r
pr_err("error: copy_from_user failed in reg_init\n");\r
}\r
\r
#if defined(CONFIG_VCODEC_MMU)\r
- if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
- pr_err("error: translate reg address failed\n");\r
- kfree(reg);\r
- return NULL;\r
- }\r
+ if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
+ pr_err("error: translate reg address failed\n");\r
+ kfree(reg);\r
+ return NULL;\r
+ }\r
#endif\r
\r
mutex_lock(&pservice->lock);\r
if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
if (reg_check_rmvb_wmv(reg)) {\r
reg->freq = VPU_FREQ_200M;\r
- } else if (reg_check_avc(reg)) {\r
- if (reg_probe_width(reg) > 3200) {\r
- // raise frequency for 4k avc.\r
- reg->freq = VPU_FREQ_500M;\r
- }\r
- } else {\r
+ } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
+ if (reg_probe_width(reg) > 3200) {\r
+ // raise frequency for 4k avc.\r
+ reg->freq = VPU_FREQ_500M;\r
+ }\r
+ } else {\r
if (reg_check_interlace(reg)) {\r
reg->freq = VPU_FREQ_400M;\r
}\r
\r
static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
{\r
-#if defined(CONFIG_VCODEC_MMU) \r
- struct vcodec_mem_region *mem_region = NULL, *n;\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ struct vcodec_mem_region *mem_region = NULL, *n;\r
#endif\r
- \r
- list_del_init(®->session_link);\r
- list_del_init(®->status_link);\r
- if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
- if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
- \r
+\r
+ list_del_init(®->session_link);\r
+ list_del_init(®->status_link);\r
+ if (reg == pservice->reg_codec)\r
+ pservice->reg_codec = NULL;\r
+ if (reg == pservice->reg_pproc)\r
+ pservice->reg_pproc = NULL;\r
+\r
#if defined(CONFIG_VCODEC_MMU)\r
- // release memory region attach to this registers table.\r
- list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {\r
- ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
- ion_free(pservice->ion_client, mem_region->hdl);\r
- list_del_init(&mem_region->reg_lnk);\r
- kfree(mem_region);\r
- }\r
-#endif \r
- \r
- kfree(reg);\r
+ // release memory region attach to this registers table.\r
+ list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {\r
+ ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
+ ion_free(pservice->ion_client, mem_region->hdl);\r
+ list_del_init(&mem_region->reg_lnk);\r
+ kfree(mem_region);\r
+ }\r
+#endif\r
+\r
+ kfree(reg);\r
}\r
\r
static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
{\r
- list_del_init(®->status_link);\r
+ list_del_init(®->status_link);\r
list_add_tail(®->status_link, &pservice->running);\r
\r
list_del_init(®->session_link);\r
int i;\r
u32 *dst = (u32 *)®->reg[0];\r
for (i = 0; i < count; i++)\r
- *dst++ = *src++;\r
+ *dst++ = *src++;\r
}\r
\r
static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
{\r
- int irq_reg = -1;\r
+ int irq_reg = -1;\r
list_del_init(®->status_link);\r
list_add_tail(®->status_link, &pservice->done);\r
\r
case VPU_ENC : {\r
pservice->reg_codec = NULL;\r
reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
- irq_reg = ENC_INTERRUPT_REGISTER;\r
+ irq_reg = ENC_INTERRUPT_REGISTER;\r
break;\r
}\r
case VPU_DEC : {\r
- int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
+ int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
pservice->reg_codec = NULL;\r
reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
- irq_reg = DEC_INTERRUPT_REGISTER;\r
+ irq_reg = DEC_INTERRUPT_REGISTER;\r
break;\r
}\r
case VPU_PP : {\r
}\r
}\r
\r
- if (irq_reg != -1) {\r
- reg->reg[irq_reg] = pservice->irq_status;\r
- }\r
+ if (irq_reg != -1) {\r
+ reg->reg[irq_reg] = pservice->irq_status;\r
+ }\r
\r
atomic_sub(1, ®->session->task_running);\r
atomic_sub(1, &pservice->total_running);\r
clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
//printk("default: 400M\n");\r
} break;\r
- case VPU_FREQ_500M : {\r
- clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
- } break;\r
- case VPU_FREQ_600M : {\r
- clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
- } break;\r
+ case VPU_FREQ_500M : {\r
+ clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
+ } break;\r
+ case VPU_FREQ_600M : {\r
+ clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
+ } break;\r
default : {\r
if (soc_is_rk2928g()) {\r
clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
case VPU_ENC : {\r
int enc_count = pservice->hw_info->enc_reg_num;\r
u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
-#if 0\r
- if (pservice->bug_dec_addr) {\r
-#if !defined(CONFIG_ARCH_RK319X)\r
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
-#endif\r
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
-#if !defined(CONFIG_ARCH_RK319X)\r
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
-#endif\r
- }\r
-#endif\r
+\r
pservice->reg_codec = reg;\r
\r
dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
\r
pservice->reg_codec = reg;\r
\r
- if (pservice->hw_info->hw_id != HEVC_ID) {\r
+ if (pservice->hw_info->hw_id != HEVC_ID) {\r
for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
dst[i] = src[i];\r
- } else {\r
- for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
+ } else {\r
+ for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
dst[i] = src[i];\r
- }\r
+ }\r
}\r
\r
dsb();\r
dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
}\r
\r
- dsb();\r
- dmb();\r
+ dsb();\r
+ dmb();\r
\r
#if VPU_SERVICE_SHOW_TIME\r
do_gettimeofday(&dec_start);\r
}\r
\r
#if HEVC_SIM_ENABLE\r
- if (pservice->hw_info->hw_id == HEVC_ID) {\r
- simulate_start(pservice);\r
- }\r
+ if (pservice->hw_info->hw_id == HEVC_ID) {\r
+ simulate_start(pservice);\r
+ }\r
#endif\r
}\r
\r
break;\r
}\r
case VPU_DEC : {\r
- int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
+ int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))\r
ret = -EFAULT;\r
break;\r
u32 enc_id = *tmp;\r
\r
#if HEVC_SIM_ENABLE\r
- /// temporary, hevc driver test.\r
- if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
- p->hw_info = &vpu_hw_set[2];\r
- return 0;\r
- }\r
+ /// temporary, hevc driver test.\r
+ if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
+ p->hw_info = &vpu_hw_set[2];\r
+ return 0;\r
+ }\r
#endif\r
\r
enc_id = (enc_id >> 16) & 0xFFFF;\r
pr_info("checking hw id %x\n", enc_id);\r
- p->hw_info = NULL;\r
+ p->hw_info = NULL;\r
for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
if (enc_id == vpu_hw_set[i].hw_id) {\r
p->hw_info = &vpu_hw_set[i];\r
\r
static int vpu_service_open(struct inode *inode, struct file *filp)\r
{\r
- struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
+ struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
if (NULL == session) {\r
pr_err("error: unable to allocate memory for vpu_session.");\r
\r
static int vpu_service_release(struct inode *inode, struct file *filp)\r
{\r
- struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
+ struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
int task_running;\r
vpu_session *session = (vpu_session *)filp->private_data;\r
if (NULL == session)\r
filp->private_data = NULL;\r
mutex_unlock(&pservice->lock);\r
\r
- pr_debug("dev closed\n");\r
+ pr_debug("dev closed\n");\r
return 0;\r
}\r
\r
#if HEVC_TEST_ENABLE\r
static int hevc_test_case0(vpu_service_info *pservice);\r
#endif\r
-#if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
+#if defined(CONFIG_ION_ROCKCHIP)\r
extern struct ion_client *rockchip_ion_client_create(const char * name);\r
#endif\r
static int vcodec_probe(struct platform_device *pdev)\r
&debug_vcodec_fops);\r
#endif\r
\r
-#if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
+#if defined(CONFIG_VCODEC_MMU)\r
pservice->ion_client = rockchip_ion_client_create("vpu");\r
if (IS_ERR(pservice->ion_client)) {\r
dev_err(&pdev->dev, "failed to create ion client for vcodec");\r