rk3066b/rk3168: add dvfs with no voltage difference support(uoc)
authorchenxing <chenxing@rock-chips.com>
Mon, 25 Mar 2013 11:11:05 +0000 (19:11 +0800)
committerchenxing <chenxing@rock-chips.com>
Mon, 25 Mar 2013 11:11:17 +0000 (19:11 +0800)
arch/arm/mach-rk30/Makefile
arch/arm/mach-rk30/dvfs-rk3066b.c [new file with mode: 0755]
arch/arm/plat-rk/Kconfig

index 004f995a7eb5e702c0e0fe55dbe6368629b90673..89af3efe91e2790f6e1052baa0e6ad80aceccbb5 100755 (executable)
@@ -24,7 +24,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_CPU_IDLE) += cpuidle.o
+ifeq ($(CONFIG_DVFS_WITH_UOC),y)
+obj-$(CONFIG_DVFS) += dvfs-rk3066b.o
+else
 obj-$(CONFIG_DVFS) += dvfs.o
+endif
 obj-$(CONFIG_RK30_I2C_INSRAM) += i2c_sram.o
 
 obj-$(CONFIG_ARCH_RK30XX) += board.o
diff --git a/arch/arm/mach-rk30/dvfs-rk3066b.c b/arch/arm/mach-rk30/dvfs-rk3066b.c
new file mode 100755 (executable)
index 0000000..0e068e2
--- /dev/null
@@ -0,0 +1,1041 @@
+/* arch/arm/mach-rk30/rk30_dvfs.c\r
+ *\r
+ * Copyright (C) 2012 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ */\r
+\r
+#include <linux/kernel.h>\r
+#include <linux/err.h>\r
+#include <linux/spinlock.h>\r
+#include <linux/list.h>\r
+#include <linux/slab.h>\r
+#include <linux/clk.h>\r
+#include <linux/cpufreq.h>\r
+#include <mach/dvfs.h>\r
+#include <mach/clock.h>\r
+#include <linux/regulator/consumer.h>\r
+#include <linux/delay.h>\r
+#include <linux/io.h>\r
+#include <linux/hrtimer.h>\r
+\r
+#include <mach/io.h>\r
+#include <mach/cru.h>\r
+#include <mach/grf-rk3066b.h>\r
+\r
+#define MHZ                    (1000 * 1000)\r
+#define KHZ                    (1000)\r
+#define CLK_LOOPS_JIFFY_REF 11996091ULL\r
+#define CLK_LOOPS_RATE_REF (1200) //Mhz\r
+#define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)\r
+struct clk *clk_cpu_div = NULL, *arm_pll_clk = NULL, *general_pll_clk = NULL;\r
+unsigned long lpj_24m;\r
+\r
+static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
+                                      unsigned long event, void *ptr)\r
+{\r
+        struct clk_notifier_data *noti_info;\r
+        struct clk *clk;\r
+        struct clk_node *dvfs_clk;\r
+        noti_info = (struct clk_notifier_data *)ptr;\r
+        clk = noti_info->clk;\r
+        dvfs_clk = clk->dvfs_info;\r
+\r
+        switch (event) {\r
+        case CLK_PRE_RATE_CHANGE:\r
+                DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
+                break;\r
+        case CLK_POST_RATE_CHANGE:\r
+                DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
+                break;\r
+        case CLK_ABORT_RATE_CHANGE:\r
+                DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
+                break;\r
+        case CLK_PRE_ENABLE:\r
+                DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
+                break;\r
+        case CLK_POST_ENABLE:\r
+                DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
+                break;\r
+        case CLK_ABORT_ENABLE:\r
+                DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
+                break;\r
+        case CLK_PRE_DISABLE:\r
+                DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
+                break;\r
+        case CLK_POST_DISABLE:\r
+                DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
+                dvfs_clk->set_freq = 0;\r
+                break;\r
+        case CLK_ABORT_DISABLE:\r
+                DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
+\r
+                break;\r
+        default:\r
+                break;\r
+        }\r
+        return 0;\r
+}\r
+\r
+static struct notifier_block rk_dvfs_clk_notifier = {\r
+        .notifier_call = rk_dvfs_clk_notifier_event,\r
+};\r
+\r
+static unsigned long dvfs_volt_arm_support_table[] = {\r
+        850 * 1000,\r
+        875 * 1000,\r
+        900 * 1000,\r
+        925 * 1000,\r
+        950 * 1000,\r
+        975 * 1000,\r
+        1000 * 1000,\r
+        1025 * 1000,\r
+        1050 * 1000,\r
+        1075 * 1000,\r
+        1100 * 1000,\r
+        1125 * 1000,\r
+        1150 * 1000,\r
+        1175 * 1000,\r
+        1200 * 1000,\r
+        1225 * 1000,\r
+        1250 * 1000,\r
+        1275 * 1000,\r
+        1300 * 1000,\r
+};\r
+static unsigned long dvfs_volt_log_support_table[] = {\r
+        850 * 1000,\r
+        875 * 1000,\r
+        900 * 1000,\r
+        925 * 1000,\r
+        950 * 1000,\r
+        975 * 1000,\r
+        1000 * 1000,\r
+        1025 * 1000,\r
+        1050 * 1000,\r
+        1075 * 1000,\r
+        1100 * 1000,\r
+        1125 * 1000,\r
+        1150 * 1000,\r
+        1175 * 1000,\r
+        1200 * 1000,\r
+        1225 * 1000,\r
+        1250 * 1000,\r
+        1275 * 1000,\r
+        1300 * 1000,\r
+};\r
+\r
+static struct clk_node *dvfs_clk_cpu;\r
+static struct vd_node vd_core;\r
+static struct vd_node vd_cpu;\r
+struct dvfs_volt_performance {\r
+        unsigned long  volt;\r
+        unsigned long  perf;   // Gate performance\r
+};\r
+\r
+struct gate_delay_table {\r
+        unsigned long arm_perf;\r
+        unsigned long log_perf;\r
+        unsigned long delay;\r
+};\r
+\r
+struct cycle_by_rate {\r
+        unsigned long rate_khz;\r
+        unsigned long cycle_ns;\r
+};\r
+/*\r
+ * 电压 dly_line 每增加0.1V的增量 每增加0.1V增加的比例 与1v对比增加的比例\r
+ * 1.00  128\r
+ * 1.10  157 29 1.23  1.23\r
+ * 1.20  184 27 1.17  1.44\r
+ * 1.30  209 25 1.14  1.63\r
+ * 1.40  231 22 1.11  1.80\r
+ * 1.50  251 20 1.09  1.96\r
+ * This table is calc form func:\r
+ * dly_line = 536 * volt - 116 * volt * volt - 292\r
+ * volt unit:          V\r
+ * dly_line unit:      Gate\r
+ *\r
+ * The table standard voltage is 1.0V, delay_line = 128(Gates)\r
+ * \r
+ * */\r
+\r
+#define VP_TABLE_END   (~0)\r
+static struct dvfs_volt_performance dvfs_vp_table[] = {\r
+        {.volt = 850 * 1000,           .perf = 350},   //623\r
+        {.volt = 875 * 1000,           .perf = 350},   //689\r
+        {.volt = 900 * 1000,           .perf = 350},   //753 make low arm freq uoc as small as posible\r
+        {.volt = 925 * 1000,           .perf = 450},   //817\r
+        {.volt = 950 * 1000,           .perf = 550},   //879\r
+        {.volt = 975 * 1000,           .perf = 650},   //940\r
+        {.volt = 1000 * 1000,          .perf = 750},\r
+        {.volt = 1025 * 1000,          .perf = 1100},\r
+        {.volt = 1050 * 1000,          .perf = 1125},\r
+        {.volt = 1075 * 1000,          .perf = 1173},\r
+        {.volt = 1100 * 1000,          .perf = 1230},\r
+        {.volt = 1125 * 1000,          .perf = 1283},\r
+        {.volt = 1150 * 1000,          .perf = 1336},\r
+        {.volt = 1175 * 1000,          .perf = 1388},\r
+        {.volt = 1200 * 1000,          .perf = 1440},\r
+        {.volt = 1225 * 1000,          .perf = 1620},  //1489\r
+        {.volt = 1250 * 1000,          .perf = 1660},  //1537\r
+        {.volt = 1275 * 1000,          .perf = 1700},  //1585\r
+        {.volt = 1300 * 1000,          .perf = 1720},  //1630 1.6Garm 600Mgpu, make uoc=2b'01\r
+        {.volt = 1325 * 1000,          .perf = 1740},  //1676\r
+        {.volt = 1350 * 1000,          .perf = 1760},  //1720\r
+        {.volt = 1375 * 1000,          .perf = 1780},  //1763\r
+        {.volt = 1400 * 1000,          .perf = 1800},\r
+        {.volt = 1425 * 1000,          .perf = 1846},\r
+        {.volt = 1450 * 1000,          .perf = 1885},\r
+        {.volt = 1475 * 1000,          .perf = 1924},\r
+        {.volt = 1500 * 1000,          .perf = 1960},\r
+        {.volt = VP_TABLE_END},\r
+};\r
+//>1.2V step = 50mV\r
+//ns (Magnified 10^6 times)\r
+#define VD_DELAY_ZOOM  (1000UL * 1000UL)\r
+#define VD_ARM_DELAY   1350000UL\r
+#define VD_LOG_DELAY   877500UL\r
+int uoc_val = 0;\r
+#define L2_HOLD        40UL    //located at 40%\r
+#define L2_SETUP       70UL    //located at 70%\r
+\r
+#define UOC_VAL_00     0UL\r
+#define UOC_VAL_01     165000UL        //0.9V(125`C):220000\r
+#define UOC_VAL_11     285000UL        //0.9V(125`C):380000\r
+#define UOC_VAL_MIN    100UL           //to work around get_delay=0\r
+\r
+#define SIZE_SUPPORT_ARM_VOLT  ARRAY_SIZE(dvfs_volt_arm_support_table)\r
+#define SIZE_SUPPORT_LOG_VOLT  ARRAY_SIZE(dvfs_volt_log_support_table)\r
+#define SIZE_VP_TABLE          ARRAY_SIZE(dvfs_vp_table)\r
+\r
+static struct gate_delay_table gate_delay[SIZE_VP_TABLE][SIZE_VP_TABLE];\r
+\r
+static unsigned long dvfs_get_perf_byvolt(unsigned long volt)\r
+{\r
+        int i = 0;\r
+        for (i = 0; dvfs_vp_table[i].volt != VP_TABLE_END; i++) {\r
+                if (volt <= dvfs_vp_table[i].volt)\r
+                        return dvfs_vp_table[i].perf;\r
+        }\r
+        return 0;\r
+}\r
+\r
+static unsigned long dvfs_get_gate_delay_per_volt(unsigned long arm_perf, unsigned long log_perf)\r
+{\r
+        unsigned long gate_arm_delay, gate_log_delay;\r
+        if (arm_perf == 0)\r
+                arm_perf = 1;\r
+        if (log_perf == 0)\r
+                log_perf = 1;\r
+        gate_arm_delay = VD_ARM_DELAY * 1000 / arm_perf;\r
+        gate_log_delay = VD_LOG_DELAY * 1000 / log_perf;\r
+\r
+        return (gate_arm_delay > gate_log_delay ? (gate_arm_delay - gate_log_delay) : 0);\r
+}\r
+\r
+static int dvfs_gate_delay_init(void)\r
+{\r
+\r
+        int i = 0, j = 0;\r
+        for (i = 0; i < SIZE_VP_TABLE - 1; i++)\r
+                for (j = 0; j < SIZE_VP_TABLE - 1; j++) {\r
+                        gate_delay[i][j].arm_perf = dvfs_vp_table[i].perf;\r
+                        gate_delay[i][j].log_perf = dvfs_vp_table[j].perf;\r
+                        gate_delay[i][j].delay = dvfs_get_gate_delay_per_volt(gate_delay[i][j].arm_perf,\r
+                                                 gate_delay[i][j].log_perf);\r
+\r
+                        DVFS_DBG("%s: arm_perf=%lu, log_perf=%lu, delay=%lu\n", __func__,\r
+                                       gate_delay[i][j].arm_perf, gate_delay[i][j].log_perf,\r
+                                       gate_delay[i][j].delay);\r
+                }\r
+        return 0;\r
+}\r
+\r
+static unsigned long dvfs_get_gate_delay(unsigned long arm_perf, unsigned long log_perf)\r
+{\r
+        int i = 0, j = 0;\r
+        for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
+                if (gate_delay[i][0].arm_perf == arm_perf)\r
+                        break;\r
+        }\r
+        for (j = 0; j < SIZE_VP_TABLE - 1; j++) {\r
+                if (gate_delay[i][j].log_perf == log_perf)\r
+                        break;\r
+        }\r
+\r
+        //DVFS_DBG("%s index_arm=%d, index_log=%d, delay=%lu\n", __func__, i, j, gate_delay[i][j].delay);\r
+        //DVFS_DBG("%s perf_arm=%d, perf_log=%d, delay=%lu\n",\r
+        //             __func__, gate_delay[i][j].arm_perf , gate_delay[i][j].log_perf , gate_delay[i][j].delay);\r
+        return gate_delay[i][j].delay;\r
+}\r
+struct uoc_val_xx2delay {\r
+        unsigned long volt;\r
+        unsigned long perf;\r
+        unsigned long uoc_val_01;\r
+        unsigned long uoc_val_11;\r
+};\r
+static struct uoc_val_xx2delay uoc_val_xx[SIZE_VP_TABLE];\r
+static int dvfs_uoc_val_delay_init(void)\r
+{\r
+        int i = 0;\r
+        for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
+                uoc_val_xx[i].volt = dvfs_vp_table[i].volt;\r
+                uoc_val_xx[i].perf = dvfs_vp_table[i].perf;\r
+                uoc_val_xx[i].uoc_val_01 = UOC_VAL_01 * 1000 / uoc_val_xx[i].perf;\r
+                uoc_val_xx[i].uoc_val_11 = UOC_VAL_11 * 1000 / uoc_val_xx[i].perf;\r
+               DVFS_DBG("%lu, %lu, %lu, %lu\n", uoc_val_xx[i].volt, uoc_val_xx[i].perf,\r
+                               uoc_val_xx[i].uoc_val_01, uoc_val_xx[i].uoc_val_11);\r
+       }\r
+        return 0;\r
+}\r
+static unsigned long dvfs_get_uoc_val_xx_by_volt(unsigned long uoc_val_xx_delay, unsigned long volt)\r
+{\r
+        int i = 0;\r
+        if (uoc_val_xx_delay == UOC_VAL_01) {\r
+                for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
+                        if (uoc_val_xx[i].volt == volt)\r
+                                return uoc_val_xx[i].uoc_val_01;\r
+                }\r
+\r
+        } else if (uoc_val_xx_delay == UOC_VAL_11) {\r
+                for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
+                        if (uoc_val_xx[i].volt == volt)\r
+                                return uoc_val_xx[i].uoc_val_11;\r
+                }\r
+\r
+        } else {\r
+                DVFS_ERR("%s UNKNOWN uoc_val_xx\n", __func__);\r
+        }\r
+        DVFS_ERR("%s can not find uoc_val_xx=%lu, with volt=%lu\n", __func__, uoc_val_xx_delay, volt);\r
+        return uoc_val_xx_delay;\r
+}\r
+#define SIZE_ARM_FREQ_TABLE    10\r
+static struct cycle_by_rate rate_cycle[SIZE_ARM_FREQ_TABLE];\r
+int size_dvfs_arm_table = 0;\r
+static int dvfs_with_uoc_init(void)\r
+{\r
+       struct cpufreq_frequency_table *arm_freq_table;\r
+       struct clk *cpu_clk;\r
+        int i = 0;\r
+       cpu_clk = clk_get(NULL, "cpu");\r
+       if (IS_ERR(cpu_clk))\r
+               return PTR_ERR(cpu_clk);\r
+\r
+       arm_freq_table = dvfs_get_freq_volt_table(cpu_clk);\r
+\r
+       lpj_24m = CLK_LOOPS_RECALC(24 * MHZ);\r
+       DVFS_DBG("24M=%lu cur_rate=%lu lpj=%lu\n", lpj_24m, arm_pll_clk->rate, loops_per_jiffy);\r
+        dvfs_gate_delay_init();\r
+        dvfs_uoc_val_delay_init();\r
+\r
+        for (i = 0; arm_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
+               if (i > SIZE_ARM_FREQ_TABLE - 1) {\r
+                       DVFS_WARNING("mach-rk30/dvfs.c:%s:%d: dvfs arm table to large, use only [%d] frequency\n",\r
+                                       __func__, __LINE__, SIZE_ARM_FREQ_TABLE);\r
+                       break;\r
+               }\r
+                rate_cycle[i].rate_khz = arm_freq_table[i].frequency;\r
+                rate_cycle[i].cycle_ns = (1000UL * VD_DELAY_ZOOM) / (rate_cycle[i].rate_khz / 1000);\r
+                DVFS_DBG("%s: rate=%lu, cycle_ns=%lu\n",\r
+                               __func__, rate_cycle[i].rate_khz, rate_cycle[i].cycle_ns);\r
+        }\r
+\r
+       size_dvfs_arm_table = i + 1;\r
+\r
+        return 0;\r
+}\r
+arch_initcall(dvfs_with_uoc_init);\r
+\r
+static unsigned long dvfs_get_cycle_by_rate(unsigned long rate_khz)\r
+{\r
+        int i = 0;\r
+        for (i = 0; i < size_dvfs_arm_table - 1; i++) {\r
+                if (rate_khz == rate_cycle[i].rate_khz)\r
+                        return rate_cycle[i].cycle_ns;\r
+        }\r
+        DVFS_ERR("%s, %d: can not find rate=%lu KHz in list\n", __func__, __LINE__, rate_khz);\r
+        return -1;\r
+}\r
+#define UOC_NEED_INCREASE_ARM  0\r
+#define UOC_NEED_INCREASE_LOG  1\r
+static unsigned long get_uoc_delay(unsigned long hold, unsigned long uoc_val_xx)\r
+{\r
+        // hold - uoc_val_11; make sure not smaller than UOC_VAL_MIN\r
+        return hold > uoc_val_xx ? (hold - uoc_val_xx) : UOC_VAL_MIN;\r
+}\r
+static unsigned long dvfs_recalc_volt(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new,\r
+                                      unsigned long arm_perf, unsigned long log_perf,\r
+                                      unsigned long hold, unsigned long setup, unsigned long flag)\r
+{\r
+        int i = 0;\r
+        unsigned long volt_arm = *p_volt_arm_new, volt_log = *p_volt_log_new;\r
+        unsigned long curr_delay = 0;\r
+        unsigned long uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, *p_volt_log_new);\r
+\r
+        if (flag == UOC_NEED_INCREASE_LOG) {\r
+                for (i = 0; i < ARRAY_SIZE(dvfs_volt_log_support_table); i++) {\r
+                        if (dvfs_volt_log_support_table[i] <= volt_log)\r
+                                continue;\r
+\r
+                        volt_log = dvfs_volt_log_support_table[i];\r
+                        log_perf = dvfs_get_perf_byvolt(volt_log);\r
+                        uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, volt_log);\r
+                        curr_delay = dvfs_get_gate_delay(arm_perf, log_perf);\r
+                        DVFS_DBG("\t%s line:%d get volt=%lu; arm_perf=%lu, log_perf=%lu, curr_delay=%lu\n",\r
+                                 __func__, __LINE__, dvfs_volt_log_support_table[i],\r
+                                 arm_perf, log_perf, curr_delay);\r
+                        if (curr_delay > get_uoc_delay(hold, uoc_val_11)) {\r
+                                *p_volt_log_new = volt_log;\r
+                                break;\r
+                        }\r
+                }\r
+        } else if (flag == UOC_NEED_INCREASE_ARM) {\r
+                for (i = 0; i < ARRAY_SIZE(dvfs_volt_arm_support_table); i++) {\r
+                        if (dvfs_volt_arm_support_table[i] <= volt_arm)\r
+                                continue;\r
+\r
+                        volt_arm = dvfs_volt_arm_support_table[i];\r
+                        arm_perf = dvfs_get_perf_byvolt(volt_arm);\r
+                        curr_delay = dvfs_get_gate_delay(arm_perf, log_perf);\r
+                        DVFS_DBG("\t%s line:%d get volt=%lu; arm_perf=%lu, log_perf=%lu, curr_delay=%lu\n",\r
+                                 __func__, __LINE__, dvfs_volt_log_support_table[i],\r
+                                 arm_perf, log_perf, curr_delay);\r
+                        if (curr_delay < setup) {\r
+                                *p_volt_arm_new = volt_arm;\r
+                                break;\r
+                        }\r
+                }\r
+\r
+        } else {\r
+                DVFS_ERR("Oops, some bugs here, %s Unknown flag:%08lx\n", __func__, flag);\r
+        }\r
+        return curr_delay;\r
+}\r
+\r
+static int dvfs_get_uoc_val(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new, unsigned long rate_khz)\r
+{\r
+        int uoc_val = 0;\r
+        unsigned long arm_perf = 0, log_perf = 0;\r
+        unsigned long cycle = 0, hold = 0, setup = 0;\r
+        unsigned long curr_delay = 0;  // arm slow than log\r
+        //unsigned long volt_arm_new = *p_volt_arm_new;\r
+        //unsigned long volt_log_new = *p_volt_log_new;\r
+        unsigned long uoc_val_01 , uoc_val_11;\r
+        //unsigned long rate_MHz;\r
+        //DVFS_DBG("enter %s\n", __func__);\r
+        arm_perf = dvfs_get_perf_byvolt(*p_volt_arm_new);\r
+        log_perf = dvfs_get_perf_byvolt(*p_volt_log_new);\r
+        uoc_val_01 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_01, *p_volt_log_new);\r
+        uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, *p_volt_log_new);\r
+        DVFS_DBG("%s volt:arm(%lu), log(%lu);\tget perf arm(%lu), log(%lu)\n", __func__,\r
+                 *p_volt_arm_new, *p_volt_log_new, arm_perf, log_perf);\r
+\r
+        // warning: this place may cause div 0 warning, DO NOT take place\r
+        // rate_MHz with (rate / DVFS_MHZ)\r
+        // rate_MHz = rate_khz / 1000;\r
+        // cycle = (1000UL * VD_DELAY_ZOOM) / (rate_khz / 1000); // ns = 1 / rate(GHz), Magnified 1000 times\r
+        cycle = dvfs_get_cycle_by_rate(rate_khz);\r
+\r
+        hold = cycle * L2_HOLD / 100UL;\r
+        setup = cycle * L2_SETUP / 100UL;\r
+\r
+        curr_delay = dvfs_get_gate_delay(arm_perf, log_perf);\r
+        DVFS_DBG("%s cycle=%lu, curr_delay=%lu, (hold=%lu, setup=%lu)\n",\r
+                 __func__, cycle, curr_delay, hold, setup);\r
+\r
+        if (curr_delay <= get_uoc_delay(hold, uoc_val_11)) {\r
+                DVFS_DBG("%s Need to increase log voltage\n", __func__);\r
+                curr_delay = dvfs_recalc_volt(p_volt_arm_new, p_volt_log_new, arm_perf, log_perf,\r
+                                              hold, setup, UOC_NEED_INCREASE_LOG);\r
+\r
+                log_perf = dvfs_get_perf_byvolt(*p_volt_log_new);\r
+                uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, *p_volt_log_new);\r
+\r
+        } else if (curr_delay >= setup) {\r
+                DVFS_DBG("%s Need to increase arm voltage\n", __func__);\r
+                curr_delay = dvfs_recalc_volt(p_volt_arm_new, p_volt_log_new, arm_perf, log_perf,\r
+                                              hold, setup, UOC_NEED_INCREASE_ARM);\r
+                arm_perf = dvfs_get_perf_byvolt(*p_volt_arm_new);\r
+                uoc_val_01 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_01, *p_volt_log_new);\r
+        }\r
+\r
+        DVFS_DBG("%s TARGET VOLT:arm(%lu), log(%lu);\tget perf arm(%lu), log(%lu)\n", __func__,\r
+                 *p_volt_arm_new, *p_volt_log_new, arm_perf, log_perf);\r
+        // update uoc_val_01/11 with new volt\r
+        //DVFS_DBG("%s cycle=%lu, hold-val11=%lu, hold-val01=%lu, (hold=%lu, setup=%lu), curr_delay=%lu\n",\r
+        //             __func__, cycle, get_uoc_delay(hold, uoc_val_11), get_uoc_delay(hold, uoc_val_01),\r
+        //             hold, setup, curr_delay);\r
+        if (curr_delay > hold && curr_delay < setup)\r
+                uoc_val = 0;\r
+        else if (curr_delay <= hold && curr_delay > get_uoc_delay(hold, uoc_val_01))\r
+                uoc_val = 1;\r
+        else if (curr_delay <= get_uoc_delay(hold, uoc_val_01) && curr_delay > get_uoc_delay(hold, uoc_val_11))\r
+                uoc_val = 3;\r
+\r
+        DVFS_DBG("%s curr_delay=%lu, uoc_val=%d\n", __func__, curr_delay, uoc_val);\r
+\r
+        return uoc_val;\r
+}\r
+static int dvfs_set_uoc_val(int uoc_val)\r
+{\r
+        DVFS_DBG("%s set UOC = %d\n", __func__, uoc_val);\r
+        writel_relaxed(\r
+                ((readl_relaxed(RK30_GRF_BASE + GRF_UOC3_CON0) | (3 << (12 + 16)))\r
+                 & (~(3 << 12))) | (uoc_val << 12), RK30_GRF_BASE + GRF_UOC3_CON0);\r
+\r
+        DVFS_DBG("read UOC=0x%08x\n", readl_relaxed(RK30_GRF_BASE + GRF_UOC3_CON0));\r
+        return 0;\r
+}\r
+\r
+static int target_set_rate(struct clk_node *dvfs_clk, unsigned long rate_new)\r
+{\r
+        int ret = 0;\r
+\r
+        if (dvfs_clk->clk_dvfs_target) {\r
+                ret = dvfs_clk->clk_dvfs_target(dvfs_clk->clk, rate_new, clk_set_rate_locked);\r
+        } else {\r
+                ret = clk_set_rate_locked(dvfs_clk->clk, rate_new);\r
+        }\r
+        if (!ret)\r
+                dvfs_clk->set_freq = rate_new / 1000;\r
+        return ret;\r
+\r
+}\r
+static int dvfs_balance_volt(unsigned long volt_arm_old, unsigned long volt_log_old)\r
+{\r
+        int ret = 0;\r
+        if (volt_arm_old > volt_log_old)\r
+                ret = dvfs_scale_volt_direct(&vd_core, volt_arm_old);\r
+        if (volt_arm_old < volt_log_old)\r
+                ret = dvfs_scale_volt_direct(&vd_cpu, volt_log_old);\r
+        if (ret)\r
+                DVFS_ERR("%s error, volt_arm_old=%lu, volt_log_old=%lu\n", __func__, volt_arm_old, volt_log_old);\r
+        return ret;\r
+}\r
+\r
+static int dvfs_scale_volt_rate_with_uoc(\r
+        unsigned long volt_arm_new, unsigned long volt_log_new,\r
+        unsigned long volt_arm_old, unsigned long volt_log_old,\r
+        unsigned long rate_arm_new)\r
+{\r
+        int uoc_val = 0;\r
+       unsigned int axi_div = 0x0;\r
+        unsigned long flags, lpj_save;\r
+        DVFS_DBG("Va_new=%lu uV, Vl_new=%lu uV;(was Va_old=%lu uV, Vl_old=%lu uV); Ra_new=%luHz\n",\r
+                 volt_arm_new, volt_log_new, volt_arm_old, volt_log_old,\r
+                 rate_arm_new);\r
+       axi_div = readl_relaxed(RK30_CRU_BASE + CRU_CLKSELS_CON(1));\r
+        uoc_val = dvfs_get_uoc_val(&volt_arm_new, &volt_log_new, rate_arm_new);\r
+        local_irq_save(flags);\r
+        lpj_save = loops_per_jiffy;\r
+\r
+        //arm slow mode\r
+        writel_relaxed(PLL_MODE_SLOW(APLL_ID), RK30_CRU_BASE + CRU_MODE_CON);\r
+        loops_per_jiffy = lpj_24m;\r
+       smp_wmb();\r
+\r
+        arm_pll_clk->rate = arm_pll_clk->recalc(arm_pll_clk);\r
+\r
+        //cpu_axi parent to apll\r
+        //writel_relaxed(0x00200000, RK30_CRU_BASE + CRU_CLKSELS_CON(0));\r
+        clk_set_parent_nolock(clk_cpu_div, arm_pll_clk);\r
+\r
+       //set axi/ahb/apb to 1:1:1\r
+       writel_relaxed(axi_div & (~(0x3 << 0)) & (~(0x3 << 8)) & (~(0x3 << 12)), RK30_CRU_BASE + CRU_CLKSELS_CON(1));\r
+\r
+        /*********************/\r
+        //balance voltage before set UOC bits\r
+        dvfs_balance_volt(volt_arm_old, volt_log_old);\r
+\r
+        //set UOC bits\r
+        dvfs_set_uoc_val(uoc_val);\r
+\r
+        //voltage up\r
+        dvfs_scale_volt_bystep(&vd_cpu, &vd_core, volt_arm_new, volt_log_new,\r
+                               100 * 1000, 100 * 1000,\r
+                               volt_arm_new > volt_log_new ? (volt_arm_new - volt_log_new) : 0,\r
+                               volt_log_new > volt_arm_new ? (volt_log_new - volt_arm_new) : 0);\r
+\r
+        /*********************/\r
+       //set axi/ahb/apb to default\r
+       writel_relaxed(axi_div, RK30_CRU_BASE + CRU_CLKSELS_CON(1));\r
+\r
+        //cpu_axi parent to gpll\r
+        //writel_relaxed(0x00200020, RK30_CRU_BASE + CRU_CLKSELS_CON(0));\r
+        clk_set_parent_nolock(clk_cpu_div, general_pll_clk);\r
+\r
+        //arm normal mode\r
+        writel_relaxed(PLL_MODE_NORM(APLL_ID), RK30_CRU_BASE + CRU_MODE_CON);\r
+        loops_per_jiffy = lpj_save;\r
+       smp_wmb();\r
+\r
+        arm_pll_clk->rate = arm_pll_clk->recalc(arm_pll_clk);\r
+\r
+        local_irq_restore(flags);\r
+\r
+        return 0;\r
+}\r
+\r
+int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
+{\r
+        struct clk_node *dvfs_clk;\r
+        int ret = 0;\r
+        int volt_new = 0, volt_dep_new = 0, volt_old = 0, volt_dep_old = 0;\r
+        struct cpufreq_frequency_table clk_fv;\r
+        unsigned long rate_new, rate_old;\r
+\r
+        if (!clk) {\r
+                DVFS_ERR("%s is not a clk\n", __func__);\r
+                return -1;\r
+        }\r
+        dvfs_clk = clk_get_dvfs_info(clk);\r
+       DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
+\r
+        if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
+                DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
+                return -1;\r
+        }\r
+\r
+        if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
+                /* It means the last time set voltage error */\r
+                ret = dvfs_reset_volt(dvfs_clk->vd);\r
+                if (ret < 0) {\r
+                        return -1;\r
+                }\r
+        }\r
+\r
+        /* Check limit rate */\r
+        if (rate_hz < dvfs_clk->min_rate) {\r
+                rate_hz = dvfs_clk->min_rate;\r
+        } else if (rate_hz > dvfs_clk->max_rate) {\r
+                rate_hz = dvfs_clk->max_rate;\r
+        }\r
+\r
+        /* need round rate */\r
+        volt_old = vd_cpu.cur_volt;\r
+        volt_dep_old = vd_core.cur_volt;\r
+\r
+        rate_old = clk_get_rate(clk);\r
+        rate_new = clk_round_rate_nolock(clk, rate_hz);\r
+        if(rate_new == rate_old)\r
+                return 0;\r
+\r
+        DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
+                 dvfs_clk->name, rate_hz, rate_new, rate_old);\r
+\r
+        /* find the clk corresponding voltage */\r
+        if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
+                DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
+                return -1;\r
+        }\r
+        dvfs_clk->set_volt = clk_fv.index;\r
+\r
+        // target\r
+        volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
+        volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
+\r
+        if (volt_dep_new <= 0)\r
+                goto fail_roll_back;\r
+\r
+        if (rate_new < rate_old)\r
+                target_set_rate(dvfs_clk, rate_new);\r
+\r
+        dvfs_scale_volt_rate_with_uoc(volt_new, volt_dep_new, volt_old, volt_dep_old,\r
+                                      rate_new / 1000);\r
+\r
+        if (rate_new > rate_old)\r
+                target_set_rate(dvfs_clk, rate_new);\r
+\r
+\r
+        DVFS_DBG("UOC VOLT OK\n");\r
+\r
+        return 0;\r
+fail_roll_back:\r
+        //dvfs_clk = clk_get_rate(dvfs_clk->clk);\r
+        return -1;\r
+}\r
+\r
+int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
+{\r
+        struct clk_node *dvfs_clk;\r
+        int ret = 0;\r
+        int volt_new = 0, volt_dep_new = 0, volt_old = 0, volt_dep_old = 0;\r
+        struct cpufreq_frequency_table clk_fv;\r
+        unsigned long rate_new, rate_old;\r
+\r
+        if (!clk) {\r
+                DVFS_ERR("%s is not a clk\n", __func__);\r
+                return -1;\r
+        }\r
+        dvfs_clk = clk_get_dvfs_info(clk);\r
+       DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
+\r
+        if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
+                DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
+                return -1;\r
+        }\r
+\r
+        if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
+                /* It means the last time set voltage error */\r
+                ret = dvfs_reset_volt(dvfs_clk->vd);\r
+                if (ret < 0) {\r
+                        return -1;\r
+                }\r
+        }\r
+\r
+        /* Check limit rate */\r
+        if (rate_hz < dvfs_clk->min_rate) {\r
+                rate_hz = dvfs_clk->min_rate;\r
+        } else if (rate_hz > dvfs_clk->max_rate) {\r
+                rate_hz = dvfs_clk->max_rate;\r
+        }\r
+\r
+        /* need round rate */\r
+        volt_old = vd_cpu.cur_volt;\r
+        volt_dep_old = vd_core.cur_volt;\r
+\r
+        rate_old = clk_get_rate(clk);\r
+        rate_new = clk_round_rate_nolock(clk, rate_hz);\r
+        if(rate_new == rate_old)\r
+                return 0;\r
+\r
+        DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
+                 dvfs_clk->name, rate_hz, rate_new, rate_old);\r
+\r
+        /* find the clk corresponding voltage */\r
+        if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
+                DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
+                return -1;\r
+        }\r
+        dvfs_clk->set_volt = clk_fv.index;\r
+\r
+        // target arm:volt_new/old, log:volt_dep_new/old\r
+        volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
+        volt_new = dvfs_vd_get_newvolt_bypd(&vd_cpu);\r
+\r
+        if (volt_dep_new <= 0)\r
+                goto fail_roll_back;\r
+\r
+        if (rate_new < rate_old)\r
+                target_set_rate(dvfs_clk, rate_new);\r
+\r
+        dvfs_scale_volt_rate_with_uoc(volt_new, volt_dep_new, volt_old, volt_dep_old,\r
+                                      dvfs_clk_cpu->set_freq);\r
+\r
+        if (rate_new > rate_old)\r
+                target_set_rate(dvfs_clk, rate_new);\r
+\r
+        DVFS_DBG("UOC VOLT OK\n");\r
+\r
+        return 0;\r
+fail_roll_back:\r
+        //dvfs_clk = clk_get_rate(dvfs_clk->clk);\r
+        return -1;\r
+}\r
+\r
+/*****************************init**************************/\r
+/**\r
+ * rate must be raising sequence\r
+ */\r
+static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
+        // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
+        // {.frequency = 126 * DVFS_KHZ, .index        = 970 * DVFS_MV},\r
+        // {.frequency = 252 * DVFS_KHZ, .index        = 1040 * DVFS_MV},\r
+        // {.frequency = 504 * DVFS_KHZ, .index        = 1050 * DVFS_MV},\r
+        {.frequency    = 816 * DVFS_KHZ, .index        = 1050 * DVFS_MV},\r
+        // {.frequency = 1008 * DVFS_KHZ, .index       = 1100 * DVFS_MV},\r
+        {.frequency    = CPUFREQ_TABLE_END},\r
+};\r
+\r
+static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
+        // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+        {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
+        {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
+        {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+        {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
+        {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
+        {.frequency = CPUFREQ_TABLE_END},\r
+};\r
+\r
+static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
+        {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+        {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
+        {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+        {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
+        {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
+        {.frequency = CPUFREQ_TABLE_END},\r
+};\r
+\r
+static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
+        {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
+        {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
+        {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
+        {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+        {.frequency = CPUFREQ_TABLE_END},\r
+};\r
+\r
+static struct cpufreq_frequency_table dep_cpu2core_table[] = {\r
+        // {.frequency = 252 * DVFS_KHZ, .index    = 1025 * DVFS_MV},\r
+        // {.frequency = 504 * DVFS_KHZ, .index    = 1025 * DVFS_MV},\r
+        {.frequency = 816 * DVFS_KHZ, .index    = 1050 * DVFS_MV},//logic 1.050V\r
+        // {.frequency = 1008 * DVFS_KHZ,.index    = 1050 * DVFS_MV},\r
+        // {.frequency = 1200 * DVFS_KHZ,.index    = 1050 * DVFS_MV},\r
+        // {.frequency = 1272 * DVFS_KHZ,.index    = 1050 * DVFS_MV},//logic 1.050V\r
+        // {.frequency = 1416 * DVFS_KHZ,.index    = 1100 * DVFS_MV},//logic 1.100V\r
+        // {.frequency = 1512 * DVFS_KHZ,.index    = 1125 * DVFS_MV},//logic 1.125V\r
+        // {.frequency = 1608 * DVFS_KHZ,.index    = 1175 * DVFS_MV},//logic 1.175V\r
+        {.frequency    = CPUFREQ_TABLE_END},\r
+};\r
+\r
+static struct vd_node vd_cpu = {\r
+        .name          = "vd_cpu",\r
+        .regulator_name        = "vdd_cpu",\r
+        .volt_set_flag         = DVFS_SET_VOLT_FAILURE,\r
+        .vd_dvfs_target        = dvfs_target_cpu,\r
+};\r
+\r
+static struct vd_node vd_core = {\r
+        .name          = "vd_core",\r
+        .regulator_name = "vdd_core",\r
+        .volt_set_flag         = DVFS_SET_VOLT_FAILURE,\r
+        .vd_dvfs_target        = dvfs_target_core,\r
+};\r
+\r
+static struct vd_node vd_rtc = {\r
+        .name          = "vd_rtc",\r
+        .regulator_name        = "vdd_rtc",\r
+        .volt_set_flag         = DVFS_SET_VOLT_FAILURE,\r
+        .vd_dvfs_target        = NULL,\r
+};\r
+\r
+static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
+\r
+static struct pd_node pd_a9_0 = {\r
+        .name                  = "pd_a9_0",\r
+        .vd                    = &vd_cpu,\r
+};\r
+static struct pd_node pd_a9_1 = {\r
+        .name                  = "pd_a9_1",\r
+        .vd                    = &vd_cpu,\r
+};\r
+static struct pd_node pd_debug = {\r
+        .name                  = "pd_debug",\r
+        .vd                    = &vd_cpu,\r
+};\r
+static struct pd_node pd_scu = {\r
+        .name                  = "pd_scu",\r
+        .vd                    = &vd_cpu,\r
+};\r
+static struct pd_node pd_video = {\r
+        .name                  = "pd_video",\r
+        .vd                    = &vd_core,\r
+};\r
+static struct pd_node pd_vio = {\r
+        .name                  = "pd_vio",\r
+        .vd                    = &vd_core,\r
+};\r
+static struct pd_node pd_gpu = {\r
+        .name                  = "pd_gpu",\r
+        .vd                    = &vd_core,\r
+};\r
+static struct pd_node pd_peri = {\r
+        .name                  = "pd_peri",\r
+        .vd                    = &vd_core,\r
+};\r
+static struct pd_node pd_cpu = {\r
+        .name                  = "pd_cpu",\r
+        .vd                    = &vd_core,\r
+};\r
+static struct pd_node pd_alive = {\r
+        .name                  = "pd_alive",\r
+        .vd                    = &vd_core,\r
+};\r
+static struct pd_node pd_rtc = {\r
+        .name                  = "pd_rtc",\r
+        .vd                    = &vd_rtc,\r
+};\r
+#define LOOKUP_PD(_ppd)        \\r
+{      \\r
+       .pd     = _ppd, \\r
+}\r
+static struct pd_node_lookup rk30_pds[] = {\r
+        LOOKUP_PD(&pd_a9_0),\r
+        LOOKUP_PD(&pd_a9_1),\r
+        LOOKUP_PD(&pd_debug),\r
+        LOOKUP_PD(&pd_scu),\r
+        LOOKUP_PD(&pd_video),\r
+        LOOKUP_PD(&pd_vio),\r
+        LOOKUP_PD(&pd_gpu),\r
+        LOOKUP_PD(&pd_peri),\r
+        LOOKUP_PD(&pd_cpu),\r
+        LOOKUP_PD(&pd_alive),\r
+        LOOKUP_PD(&pd_rtc),\r
+};\r
+\r
+#define CLK_PDS(_ppd) \\r
+{      \\r
+       .pd     = _ppd, \\r
+}\r
+\r
+static struct pds_list cpu_pds[] = {\r
+        CLK_PDS(&pd_a9_0),\r
+        CLK_PDS(&pd_a9_1),\r
+        CLK_PDS(NULL),\r
+};\r
+\r
+static struct pds_list ddr_pds[] = {\r
+        CLK_PDS(&pd_cpu),\r
+        CLK_PDS(NULL),\r
+};\r
+\r
+static struct pds_list gpu_pds[] = {\r
+        CLK_PDS(&pd_gpu),\r
+        CLK_PDS(NULL),\r
+};\r
+\r
+static struct pds_list aclk_periph_pds[] = {\r
+        CLK_PDS(&pd_peri),\r
+        CLK_PDS(NULL),\r
+};\r
+\r
+#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
+{ \\r
+       .name   = _clk_name, \\r
+       .pds = _ppds,\\r
+       .dvfs_table = _dvfs_table,      \\r
+       .dvfs_nb        = _dvfs_nb,     \\r
+}\r
+\r
+static struct clk_node rk30_clks[] = {\r
+        RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
+        RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
+        RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
+        RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
+};\r
+\r
+#define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \\r
+{ \\r
+       .clk_name       = _clk_name, \\r
+       .dep_vd         = _pvd,\\r
+       .dep_table      = _dep_table,   \\r
+}\r
+\r
+static struct depend_lookup rk30_depends[] = {\r
+#ifndef CONFIG_ARCH_RK3066B\r
+        RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
+#endif\r
+        //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
+        //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
+};\r
+static struct avs_ctr_st rk30_avs_ctr;\r
+\r
+int rk_dvfs_init(void)\r
+{\r
+        int i = 0;\r
+        for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
+                rk_regist_vd(rk30_vds[i]);\r
+        }\r
+        for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
+                rk_regist_pd(&rk30_pds[i]);\r
+        }\r
+        for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
+                rk_regist_clk(&rk30_clks[i]);\r
+        }\r
+        for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
+                rk_regist_depends(&rk30_depends[i]);\r
+        }\r
+        dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
+\r
+        clk_cpu_div = clk_get(NULL, "logic");\r
+        if (IS_ERR_OR_NULL(clk_cpu_div)) {\r
+                DVFS_ERR("%s get clk_cpu_div error\n", __func__);\r
+                return -1;\r
+        }\r
+\r
+        arm_pll_clk = clk_get(NULL, "arm_pll");\r
+        if (IS_ERR_OR_NULL(arm_pll_clk)) {\r
+                DVFS_ERR("%s get arm_pll_clk error\n", __func__);\r
+                return -1;\r
+        }\r
+\r
+        general_pll_clk = clk_get(NULL, "general_pll");\r
+        if (IS_ERR_OR_NULL(general_pll_clk)) {\r
+                DVFS_ERR("%s get general_pll_clk error\n", __func__);\r
+                return -1;\r
+        }\r
+\r
+        avs_board_init(&rk30_avs_ctr);\r
+        DVFS_DBG("rk30_dvfs_init\n");\r
+        return 0;\r
+}\r
+\r
+\r
+\r
+/******************************rk30 avs**************************************************/\r
+\r
+#ifdef CONFIG_ARCH_RK3066B\r
+\r
+static void __iomem *rk30_nandc_base = NULL;\r
+\r
+#define nandc_readl(offset)    readl_relaxed(rk30_nandc_base + offset)\r
+#define nandc_writel(v, offset) do { writel_relaxed(v, rk30_nandc_base + offset); dsb(); } while (0)\r
+static u8 rk30_get_avs_val(void)\r
+{\r
+        u32 nanc_save_reg[4];\r
+        unsigned long flags;\r
+        u32 paramet = 0;\r
+        u32 count = 100;\r
+        if(rk30_nandc_base == NULL)\r
+                return 0;\r
+\r
+        preempt_disable();\r
+        local_irq_save(flags);\r
+\r
+        nanc_save_reg[0] = nandc_readl(0);\r
+        nanc_save_reg[1] = nandc_readl(0x130);\r
+        nanc_save_reg[2] = nandc_readl(0x134);\r
+        nanc_save_reg[3] = nandc_readl(0x158);\r
+\r
+        nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
+        nandc_writel(0x5, 0x130);\r
+\r
+        nandc_writel(3, 0x158);\r
+        nandc_writel(1, 0x134);\r
+\r
+        while(count--) {\r
+                paramet = nandc_readl(0x138);\r
+                if((paramet & 0x1))\r
+                        break;\r
+                udelay(1);\r
+        };\r
+        paramet = (paramet >> 1) & 0xff;\r
+        nandc_writel(nanc_save_reg[0], 0);\r
+        nandc_writel(nanc_save_reg[1], 0x130);\r
+        nandc_writel(nanc_save_reg[2], 0x134);\r
+        nandc_writel(nanc_save_reg[3], 0x158);\r
+\r
+        local_irq_restore(flags);\r
+        preempt_enable();\r
+        return (u8)paramet;\r
+\r
+}\r
+\r
+void rk30_avs_init(void)\r
+{\r
+        rk30_nandc_base = ioremap(RK30_NANDC_PHYS, RK30_NANDC_SIZE);\r
+}\r
+static struct avs_ctr_st rk30_avs_ctr = {\r
+        .avs_init              = rk30_avs_init,\r
+        .avs_get_val   = rk30_get_avs_val,\r
+};\r
+#endif\r
+\r
+\r
index 8981798b1fd506f0f0ee85ff4ce634ee4fc79f3e..10dd7e30f7e50d0a34ebff16a855afc66c9a0069 100755 (executable)
@@ -109,6 +109,11 @@ config DVFS
        depends on REGULATOR&&CPU_FREQ
        default y
 
+config DVFS_WITH_UOC
+       bool "Use dvfs with uoc, no voltage difference"
+       depends on DVFS && ARCH_RK3066B
+       default y
+
 config RK_CLOCK_PROC
        bool "/proc/clocks support"
        depends on PROC_FS