resume ZQ1CR[0]

diff --git a/arch/arm/mach-rk30/ddr.c b/arch/arm/mach-rk30/ddr.c
index a50e3e8b836e76134937fb77b2f075472682db0d..db644378fc36cf5a24e6b70093fe8989522707de 100755 (executable)
--- a/arch/arm/mach-rk30/ddr.c
+++ b/arch/arm/mach-rk30/ddr.c
@@ -2757,7 +2757,7 @@ void __sramlocalfunc ddr_update_odt(void)
     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
     if(cs > 1)
     {
-        pPHY_Reg->ZQ1CR[1] = tmp;
+        pPHY_Reg->ZQ1CR[0] = tmp;
         dsb();
     }
     pPHY_Reg->ZQ0CR[0] = tmp;
@@ -3225,7 +3225,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
     uint32_t cs,die=1;
     uint32_t gsr,dqstr;
 
-    ddr_print("version 1.00 20120820 \n");
+    ddr_print("version 1.00 20120822 \n");
 
     mem_type = pPHY_Reg->DCR.b.DDRMD;
     ddr_speed_bin = dram_speed_bin;