fix some fp condition codes

use non trapping comparison instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30962 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index e752778fedd7417ea5482466b9eb836262a8f50a..8076757580761a560c67a7979c84d2addc94fd16 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -92,7 +92,6 @@ namespace llvm {
       RET_FLAG,
 
       CMP,
-      CMPE,
 
       SELECT,
 
@@ -120,36 +119,42 @@ namespace llvm {
 }
 
 /// DAGFPCCToARMCC - Convert a DAG fp condition code to an ARM CC
+// Unordered = !N & !Z & C & V = V
+// Ordered   =  N | Z | !C | !V = N | Z | !V
 static ARMCC::CondCodes DAGFPCCToARMCC(ISD::CondCode CC) {
   switch (CC) {
   default:
     assert(0 && "Unknown fp condition code!");
-// For the following conditions we use a comparison that throws exceptions,
-// so we may assume that V=0
+// SETOEQ = (N | Z | !V) & Z = Z                               = EQ
+  case ISD::SETEQ:
   case ISD::SETOEQ: return ARMCC::EQ;
+// SETOGT = (N | Z | !V) & !N & !Z = !V &!N &!Z = (N = V) & !Z = GT
+  case ISD::SETGT:
   case ISD::SETOGT: return ARMCC::GT;
+// SETOGE = (N | Z | !V) & !N = (Z | !V) & !N = !V & !N        = GE
+  case ISD::SETGE:
   case ISD::SETOGE: return ARMCC::GE;
-  case ISD::SETOLT: return ARMCC::LT;
-  case ISD::SETOLE: return ARMCC::LE;
+// SETOLT = (N | Z | !V) & N = N                               = MI
+  case ISD::SETLT:
+  case ISD::SETOLT: return ARMCC::MI;
+// SETOLE = (N | Z | !V) & (N | Z) = N | Z = !C | Z            = LS
+  case ISD::SETLE:
+  case ISD::SETOLE: return ARMCC::LS;
+// SETONE = (N | Z | !V) & !Z = (N | !V) & Z = !V & Z = Z      = NE
+  case ISD::SETNE:
   case ISD::SETONE: return ARMCC::NE;
-// For the following conditions the result is undefined in case of a nan,
-// so we may assume that V=0
-  case ISD::SETEQ:  return ARMCC::EQ;
-  case ISD::SETGT:  return ARMCC::GT;
-  case ISD::SETGE:  return ARMCC::GE;
-  case ISD::SETLT:  return ARMCC::LT;
-  case ISD::SETLE:  return ARMCC::LE;
-  case ISD::SETNE:  return ARMCC::NE;
-// For the following we may not assume anything
-//    SETO      =  N | Z | !C | !V              = ???
-//    SETUO     = (!N & !Z & C & V)             = ???
-//    SETUEQ    = (!N & !Z & C & V) | Z         = ???
-//    SETUGT    = (!N & !Z & C & V) | (!Z & !N) = ???
-//    SETUGE    = (!N & !Z & C & V) | !N        = !N  = PL
+// SETO   = N | Z | !V = Z | !V = !V                           = VC
+  case ISD::SETO:   return ARMCC::VC;
+// SETUO  = V                                                  = VS
+  case ISD::SETUO:  return ARMCC::VS;
+// SETUEQ = V | Z                                              = ??
+// SETUGT = V | (!Z & !N) = !Z & !N = !Z & C                   = HI
+  case ISD::SETUGT: return ARMCC::HI;
+// SETUGE = V | !N = !N                                        = PL
   case ISD::SETUGE: return ARMCC::PL;
-//    SETULT    = (!N & !Z & C & V) | N         = ???
-//    SETULE    = (!N & !Z & C & V) | Z | N     = ???
-//    SETUNE    = (!N & !Z & C & V) | !Z        = !Z  = NE
+// SETULT = V | N                                              = ??
+// SETULE = V | Z | N                                          = ??
+// SETUNE = V | !Z = !Z                                        = NE
   case ISD::SETUNE: return ARMCC::NE;
   }
 }
@@ -179,7 +184,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
   case ARMISD::SELECT:        return "ARMISD::SELECT";
   case ARMISD::CMP:           return "ARMISD::CMP";
-  case ARMISD::CMPE:          return "ARMISD::CMPE";
   case ARMISD::BR:            return "ARMISD::BR";
   case ARMISD::FSITOS:        return "ARMISD::FSITOS";
   case ARMISD::FTOSIS:        return "ARMISD::FTOSIS";
@@ -586,15 +590,7 @@ static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS,
   MVT::ValueType vt = LHS.getValueType();
   assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
 
-  bool isOrderedFloat = (vt == MVT::f32 || vt == MVT::f64) &&
-    (CC >= ISD::SETOEQ && CC <= ISD::SETONE);
-
-  SDOperand Cmp;
-  if (isOrderedFloat) {
-    Cmp = DAG.getNode(ARMISD::CMPE, MVT::Flag, LHS, RHS);
-  } else {
-    Cmp = DAG.getNode(ARMISD::CMP,  MVT::Flag, LHS, RHS);
-  }
+  SDOperand Cmp = DAG.getNode(ARMISD::CMP,  MVT::Flag, LHS, RHS);
 
   if (vt != MVT::i32)
     Cmp = DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index fde132aaea00222fb7b8f505044cd1c0cd6db77d..17e0eecf971e430ab912fe6b4b5b97df2f6aa24e 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -76,7 +76,6 @@ def armbr          : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
 
 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
-def armcmpe      : SDNode<"ARMISD::CMPE", SDTVoidBinOp, [SDNPOutFlag]>;
 
 def armfsitos      : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
 def armftosis      : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
@@ -192,14 +191,6 @@ def fcmps   : InstARM<(ops FPRegs:$a, FPRegs:$b),
                       "fcmps $a, $b",
                       [(armcmp FPRegs:$a, FPRegs:$b)]>;
 
-def fcmpes  : InstARM<(ops FPRegs:$a, FPRegs:$b),
-                      "fcmpes $a, $b",
-                      [(armcmpe FPRegs:$a, FPRegs:$b)]>;
-
-def fcmped  : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
-                      "fcmped $a, $b",
-                      [(armcmpe DFPRegs:$a, DFPRegs:$b)]>;
-
 def fcmpd   : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
                       "fcmpd $a, $b",
                       [(armcmp DFPRegs:$a, DFPRegs:$b)]>;

diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll
index 5c120ea65c893103d14c187620615ed70ddd55fd..16e9a1b14050258c82b06ea25e5c8e02f293c31b 100644 (file)
--- a/test/CodeGen/ARM/fpcmp.ll
+++ b/test/CodeGen/ARM/fpcmp.ll
@@ -1,12 +1,10 @@
 ; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm  | grep movlt &&
+; RUN: llvm-as < %s | llc -march=arm  | grep movmi &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep moveq &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep movgt &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep movge &&
-; RUN: llvm-as < %s | llc -march=arm  | grep movle &&
-; RUN: llvm-as < %s | llc -march=arm  | grep fcmpes &&
+; RUN: llvm-as < %s | llc -march=arm  | grep movls &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep fcmps &&
-; RUN: llvm-as < %s | llc -march=arm  | grep fcmped &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep fcmpd
 
 int %f1(float %a) {