return get(Opcode).numOperands;
}
-
InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
return get(Opcode).schedClass;
}
#ifndef LLVM_TARGET_TARGETINSTRITINERARIES_H
#define LLVM_TARGET_TARGETINSTRITINERARIES_H
+#include "llvm/Support/Debug.h"
+
namespace llvm {
//===----------------------------------------------------------------------===//
};
+
+//===----------------------------------------------------------------------===//
+// Instruction itinerary Data - Itinerary data supplied by a subtarget to be
+// used by a target.
+//
+class InstrItineraryData {
+ InstrStage *Stages; // Array of stages selected
+ unsigned NStages; // Number of stages
+ InstrItinerary *Itineratries; // Array of itineraries selected
+ unsigned NItineraries; // Number of itineraries (actually classes)
+
+public:
+
+ //
+ // Ctors.
+ //
+ InstrItineraryData()
+ : Stages(NULL), NStages(0), Itineratries(NULL), NItineraries(0)
+ {}
+ InstrItineraryData(InstrStage *S, unsigned NS, InstrItinerary *I, unsigned NI)
+ : Stages(S), NStages(NS), Itineratries(I), NItineraries(NI)
+ {}
+
+ //
+ // isEmpty - Returns true if there are no itineraries.
+ //
+ inline bool isEmpty() const { return NItineraries == 0; }
+
+ //
+ // begin - Return the first stage of the itinerary.
+ //
+ inline InstrStage *begin(unsigned ItinClassIndx) const {
+ assert(ItinClassIndx < NItineraries && "Itinerary index out of range");
+ unsigned StageIdx = Itineratries[ItinClassIndx].First;
+ assert(StageIdx < NStages && "Stage index out of range");
+ return Stages + StageIdx;
+ }
+
+ //
+ // end - Return the last+1 stage of the itinerary.
+ //
+ inline InstrStage *end(unsigned ItinClassIndx) const {
+ assert(ItinClassIndx < NItineraries && "Itinerary index out of range");
+ unsigned StageIdx = Itineratries[ItinClassIndx].Last;
+ assert(StageIdx < NStages && "Stage index out of range");
+ return Stages + StageIdx;
+ }
+};
+
+
} // End llvm namespace
#endif
#define LLVM_TARGET_TARGETMACHINE_H
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetInstrItineraries.h"
#include <cassert>
namespace llvm {
/// otherwise return null.
///
virtual TargetJITInfo *getJITInfo() { return 0; }
+
+ /// getInstrItineraryData - Returns instruction itinerary data for the target
+ /// or specific subtarget.
+ ///
+ virtual const InstrItineraryData getInstrItineraryData() const {
+ return InstrItineraryData();
+ }
// These are deprecated interfaces.
virtual const TargetSchedInfo *getSchedInfo() const { return 0; }
PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS)
: StackAlignment(16)
+ , InstrItins()
, IsGigaProcessor(false)
, Is64Bit(false)
, Has64BitRegs(false)
#ifndef POWERPCSUBTARGET_H
#define POWERPCSUBTARGET_H
+#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetSubtarget.h"
#include <string>
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned StackAlignment;
+
+ /// Selected instruction itineraries (one entry per itinerary class.)
+ InstrItineraryData InstrItins;
/// Used by the ISel to turn in optimizations for POWER4-derived architectures
bool IsGigaProcessor;
/// stack frame on entry to the function and which must be maintained by every
/// function for this subtarget.
unsigned getStackAlignment() const { return StackAlignment; }
+
+ /// getInstrItins - Return the instruction itineraies based on subtarget
+ /// selection.
+ const InstrItineraryData getInstrItineraryData() const { return InstrItins; }
+
bool hasFSQRT() const { return HasFSQRT; }
bool has64BitRegs() const { return Has64BitRegs; }
PPCTargetMachine::PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS)
: TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 2, 1, 1),
- Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this) {
+ Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this),
+ InstrItins(Subtarget.getInstrItineraryData()) {
if (TargetDefault == PPCTarget) {
if (Subtarget.isAIX()) PPCTarget = TargetAIX;
if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
class IntrinsicLowering;
class PPCTargetMachine : public TargetMachine {
- PPCInstrInfo InstrInfo;
- PPCSubtarget Subtarget;
- PPCFrameInfo FrameInfo;
- PPCJITInfo JITInfo;
+ PPCInstrInfo InstrInfo;
+ PPCSubtarget Subtarget;
+ PPCFrameInfo FrameInfo;
+ PPCJITInfo JITInfo;
+ InstrItineraryData InstrItins;
public:
PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS);
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
+ virtual const InstrItineraryData getInstrItineraryData() const {
+ return InstrItins;
+ }
+
static unsigned getJITMatchQuality();
for (unsigned i = 0, N = DefList.size(); i < N; i++) {
Record *Def = DefList[i];
- ItinClassMap[Def->getName()] = i + 1;
+ ItinClassMap[Def->getName()] = i;
}
}
// CollectAllItinClasses - Gathers and enumerates all the itinerary classes.
// Returns itinerary class count.
//
-unsigned SubtargetEmitter::CollectAllItinClasses(std::map<std::string, unsigned>
- &ItinClassesMap) {
+unsigned SubtargetEmitter::CollectAllItinClasses(std::ostream &OS,
+ std::map<std::string, unsigned> &ItinClassesMap) {
// Gather and sort all itinerary classes
std::vector<Record*> ItinClassList =
Records.getAllDerivedDefinitions("InstrItinClass");
ItinClassesMap[Name] = i;
}
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" ItinClassesSize = " << N << "\n";
+ OS<<"};\n";
+
// Return itinerary class count
return N;
}
// End stages table
OS << "};\n";
+
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n";
+ OS<<"};\n";
}
//
std::vector<std::vector<InstrItinerary> > ProcList;
// Enumerate all the itinerary classes
- unsigned NItinClasses = CollectAllItinClasses(ItinClassesMap);
- // Emit the stage data
- EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
- // Emit the processor itinerary data
- EmitProcessorData(OS, ProcList);
- // Emit the processor lookup data
- EmitProcessorLookup(OS);
+ unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap);
+ // Make sure the rest is worth the effort
+ HasItineraries = NItinClasses != 0;
+
+ if (HasItineraries) {
+ // Emit the stage data
+ EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
+ // Emit the processor itinerary data
+ EmitProcessorData(OS, ProcList);
+ // Emit the processor lookup data
+ EmitProcessorLookup(OS);
+ }
}
//
OS << " " << Attribute << " = (Bits & " << Instance << ") != 0;\n";
}
- OS << "\n"
- << " InstrItinerary *Itin = (InstrItinerary *)"
- "Features.getInfo(SubTypeInfoKV, SubTypeInfoKVSize);\n";
+
+ if (HasItineraries) {
+ OS << "\n"
+ << " InstrItinerary *Itinerary = (InstrItinerary *)"
+ "Features.getInfo(SubTypeInfoKV, SubTypeInfoKVSize);\n"
+ " InstrItins = InstrItineraryData(Stages, StagesSize, "
+ "Itinerary, ItinClassesSize);\n";
+ }
+
OS << "}\n";
}
RecordKeeper &Records;
std::string Target;
+ bool HasItineraries;
void Enumeration(std::ostream &OS, const char *ClassName, bool isBits);
void FeatureKeyValues(std::ostream &OS);
void CPUKeyValues(std::ostream &OS);
- unsigned CollectAllItinClasses(std::map<std::string, unsigned>
- &ItinClassesMap);
+ unsigned CollectAllItinClasses(std::ostream &OS,
+ std::map<std::string, unsigned> &ItinClassesMap);
void FormItineraryString(Record *ItinData, std::string &ItinString,
unsigned &NStages);
void EmitStageData(std::ostream &OS, unsigned NItinClasses,
void ParseFeaturesFunction(std::ostream &OS);
public:
- SubtargetEmitter(RecordKeeper &R) : Records(R) {}
+ SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
// run - Output the subtarget enumerations, returning true on failure.
void run(std::ostream &o);
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